Compound semiconductor device and method of manufacturing same

[0001] This application is a divisional of application Ser. No. 13/089,981, filed Apr. 19, 2011, which is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2010-107654, filed on May 7, 2010, the entire contents of which are incorporated herein by reference.

[0002] The present invention relates to a compound semiconductor device and a method of manufacturing a compound semiconductor device.

[0003] Nitride semiconductor devices have features, such as high saturated electron velocity and wide band gaps, and thus have been actively developed as high-voltage, high-power semiconductor devices. With respect to nitride semiconductor devices, many reports of field-effect transistors, in particular, high electron mobility transistors (HEMTs) have been published. In particular, AlGaN/GaN HEMTs including electron transit layers composed of GaN and electron supply layers composed of AlGaN have been attracting attention. For AlGaN/GaN HEMTs, the difference in lattice constant between GaN and AlGaN causes strain in AlGaN. The strain-induced piezoelectric polarization and the spontaneous polarization of AlGaN results in a high-density two-dimensional electron gas (2DEG), thereby achieving high breakdown voltage and high output power. AlGaN/GaN HEMTs have been attracting attention as semiconductor devices for use in power supplies and high-frequency amplifiers.

[0004] Nitride semiconductor devices, such as AlGaN/GaN HEMTs, include gate electrodes, source electrodes, and drain electrodes on nitride semiconductor layers including, for example, electron transit layers and electron supply layers. The gate electrodes, the source electrodes, and the drain electrodes are formed using what is called a lift-off process.

[0005] To form a source electrode and a drain electrode, a resist is applied on a nitride semiconductor layer and processed by lithography to form a resist mask having openings located at portions of the mask corresponding to portions of the layer where the source electrode and the drain electrode will be formed. For example, Ti/Al is used as an electrode material. Ti/Al is deposited by vapor evaporation or the like on the resist mask in such a manner that the openings are filled with Ti/Al. The resist mask and Ti/Al deposited on the mask are removed by the lift-off process. Then heat treatment of a substrate forms ohmic contacts. Thereby, the source electrode and the drain electrode are formed on the nitride semiconductor layer.

[0006] To form the gate electrode, the resist is applied on the nitride semiconductor layer and processed by lithography to form a resist mask having an opening located at a portion of the mask corresponding to a portion of the layer where the gate electrode will be formed. For example, Ni/Au is used as an electrode material. Ni/Au is deposited by vapor evaporation or the like on the resist mask in such a manner that the opening is filled with Ni/Au. The resist mask and Ni/Au deposited on the mask are removed by the lift-off process. Thereby, the gate electrode is formed between the source electrode and the drain electrode on the nitride semiconductor layer.

[0007] Japanese Unexamined Patent Application Publication No. 2008-270521 is an example of related art.

[0008] According to an aspect of the invention, a method of manufacturing a compound semiconductor device, includes forming a compound semiconductor layer on a substrate; forming a first insulating film on the compound semiconductor layer; forming a first opening in the first insulating film, the first opening being configured to partially expose the compound semiconductor layer; forming a first conductive material on the first insulating film via at least a gate insulator in such a manner that the first opening is filled with the first conductive material; forming a first mask on a portion of the first conductive material corresponding to the first opening; processing at least the first conductive material with the first mask to form a gate electrode; forming a second insulating film on the first insulating film so as to cover the gate electrode; forming a pair of second openings in at least the second insulating film and the first insulating film, the pair of second openings being configured to partially expose the compound semiconductor layer; forming at least a second conductive material on the second insulating film in such a manner that the second openings are filled with the second conductive material; forming second masks on portions of the second conductive material corresponding to the second openings; and processing at least the second conductive material using the second masks to form a source electrode and a drain electrode.

[0009] According to another aspect of the invention, a method of manufacturing a compound semiconductor device, includes forming a compound semiconductor layer on a substrate; forming a first insulating film on the compound semiconductor layer; forming a pair of first openings in the first insulating film, the pair of first openings being configured to partially expose the compound semiconductor layer; forming a first conductive material on the first insulating film in such a manner that the first openings are filled with the first conductive material; forming first masks on portions of the first conductive material corresponding to the first openings; processing at least the first conductive material with the first masks to form a source electrode and a drain electrode; forming a second insulating film on the first insulating film so as to cover the source electrode and the drain electrode; forming a second opening in at least the second insulating film and the first insulating film, the second opening being configured to partially expose the compound semiconductor layer; forming a second conductive material on the second insulating film via at least a gate insulator in such a manner that the second openings are filled with the second conductive material; forming a second mask on a portion of the second conductive material corresponding to the second opening; and processing at least the second conductive material with the second mask to form a gate electrode.

[0010] According to another aspect of the invention, a compound semiconductor device includes a substrate; a compound semiconductor layer formed on the substrate; a first insulating film formed on the compound semiconductor layer; a second insulating film formed on the first insulating film; and a gate electrode, a source electrode, and a drain electrode, each being formed on the compound semiconductor layer, wherein the gate electrode is formed of a first opening filled with a first conductive material via at least a gate insulator, and the first opening is formed in the first insulating film and configured to partially expose the compound semiconductor layer, and wherein the source electrode and the drain electrode are formed of a pair of second openings filled with at least a second conductive material, and the second openings are formed in at least the second insulating film and the first insulating film and configured to partially expose the compound semiconductor layer.

[0011] According to another aspect of the invention, a compound semiconductor device includes a substrate; a compound semiconductor layer formed on the substrate; a first insulating film formed on the compound semiconductor layer; a second insulating film formed on the first insulating film; and a gate electrode, a source electrode, and a drain electrode, each being formed on the compound semiconductor layer, wherein the source electrode and the drain electrode are formed of a pair of first openings filled with at least a first conductive material, and the first openings are formed in the first insulating film and configured to partially expose the compound semiconductor layer, and wherein the gate electrode is formed of a second opening filled with a second conductive material via at least gate insulator, and the second opening is formed in at least the second insulating film and the first insulating film and configured to partially expose the compound semiconductor layer.

[0012] The object and advantages of the invention will be realized and attained by at least those elements, features, and combinations particularly pointed out in the claims.

[0013] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention, as claimed.

[0030] In the case where a gate electrode, a source electrode, and a drain electrode are formed by the lift-off process, part of metal pieces of the electrode material that has been lifted-off may be redeposited on a surface of the substrate. The redeposited metal pieces may cause defects in various patterns when the patterns are formed in the subsequent steps. Examples of the patterns in which defects may be caused include as follows: the gate electrode when the source electrode and the drain electrode are formed before the formation of the gate electrode; the source electrode and the drain electrode when the source electrode and the drain electrode are formed after the formation of the gate electrode; connecting portions connected to the gate electrode, the source electrode, and the drain electrode; and various interlayer insulators. If defects occur in these patterns, device properties of nitride semiconductor devices may be significantly impaired.

[0031] In this embodiment, with respect to an AlGaN/GaN HEMT, the case where a gate electrode is formed before the formation of a source electrode and drain electrode is described.

[0032] FIGS. 1A to 1P are schematic cross-sectional views illustrating a method of manufacturing an AlGaN/GaN HEMT according to a first embodiment.

[0033] As illustrated in FIG. 1A, a buffer layer 2, an electron transit layer 3, an electron supply layer 4, and a cap layer 5 are formed on, for example, a semi-insulating SiC substrate 1 serving as a substrate used for growth.

[0034] For example, the buffer layer 2 is an AlN layer, the electron transit layer 3 is an intentionally undoped GaN (i-GaN) layer, the electron supply layer 4 is an n-AlGaN layer, and the cap layer 5 is an n-GaN layer.

[0035] A silicon substrate may be used in place of the SiC substrate 1. The buffer layer 2 may have a multilayer structure composed of AlN and GaN. Alternatively, the buffer layer 2 may have a concentration gradient of Ga in such a manner that the composition is changed from AlN to AlGaN from the lower portion (adjacent to the SiC substrate 1) to the upper portion. Furthermore, the electron supply layer 4 may be an intentionally undoped AlGaN (i-AlGaN) layer.

[0036] Referring to FIG. 1A, specifically, the following compound semiconductor layers are grown on the SiC substrate 1 by, for example, metal-organic vapor phase epitaxy (MOVPE) using a crystal growth apparatus.

[0037] AlN, i-GaN, n-AlGaN, and n-GaN are deposited on the SiC substrate 1 to form the buffer layer 2, the electron transit layer 3, the electron supply layer 4, and the cap layer 5. The buffer layer 2 has a thickness of about 2 μm. The electron transit layer 3 has a thickness of 1 μm to 3 μm. In this embodiment, the electron transit layer 3 has a thickness of about 3 μm. The electron supply layer 4 has a thickness of about 5 nm to about 40 nm. In this embodiment, the electron supply layer 4 has a thickness of about 40 nm and an Al ratio of, for example, 0.2. The cap layer 5 has a thickness of about 0.1 nm to about 5 nm. In this embodiment, the cap layer 5 has a thickness of about 2 nm.

[0038] In the AlGaN/GaN HEMT, a two-dimensional electron gas (2DEG) indicated by a broken line in the figure is formed in the vicinity of the interface of the electron transit layer 3 and the electron supply layer 4. This is attributed to the formation of a quantum well due to the fact that the band gap of AlGaN constituting the electron supply layer 4 is larger than that of GaN constituting the electron transit layer 3. The accumulation of electrons in the quantum well results in the formation of the 2DEG, which serves as an electron carrier.

[0039] With respect to growth conditions of AlN, i-GaN, n-AlGaN, and n-GaN, a mixed gas of trimethylaluminum gas, trimethylgallium gas, and ammonia gas is used as a source gas. Whether or not to feed the trimethylaluminum gas serving as an Al source, the trinnethylgallium gas serving as a Gs source, and the ammonia gas serving as an N source and the flow rate thereof are appropriately set in response to the compound semiconductor layers to be grown. The flow rate of the ammonia gas, which is a common source, is set to about 100 can to about 10 LM. The growth pressure is set to about 50 Torr to about 300 Torr. The growth temperature is set to about 1000° C. to about 1200° C. In the case of the growth of n-GaN and n-AlGaN, for example, a Si-containing gas, such as SiH₄ gas, serving as an n-type impurity is added to the source gas at a predetermined flow rate to dope GaN and AlGaN with Si. The Si doping concentration is set to about 1×10¹⁸/cm³ to about 1×10²⁰/cm³, for example, about 1×10¹⁸/cm³.

[0040] As illustrated in FIG. 1B, a resist mask 6 is formed on the cap layer 5.

[0041] A resist is applied on the entire surface of the cap layer 5 and processed by lithography, thereby forming the resist mask 6 that covers an element active region and expose an element isolation region on the cap layer 5.

[0042] As illustrated in FIG. 1C, element isolation structures 7 are formed.

[0043] A predetermined element, for example, Ar, is ion-implanted into the element active region extending to the cap layer 5, the electron supply layer 4, the electron transit layer 3, the buffer layer 2, and an upper portion of the SiC substrate 1 using the resist mask 6. The ion implantation is performed at an acceleration energy of, for example, about 100 eV and a dose of, for example, about 1.0×10¹³/cm². The element isolation structures 7 are formed by the ion implantation. In the element isolation structures 7, the crystal structures of AlN, GaN, and AlGaN are broken to eliminate the 2DEG in the element isolation structures 7; hence, the element isolation structures 7 serve as insulating regions.

[0044] Then the resist mask 6 is removed by ashing or the like.

[0045] As illustrated in FIG. 1D, a first protective insulating film 8 is formed.

[0046] An insulating film, for example, a silicon nitride film, having a thickness of about 20 nm to 500 nm, for example, about 300 nm is formed on the entire surface above the SiC substrate 1 by, for example, plasma-enhanced chemical vapor deposition (CVD), thereby forming the first protective insulating film 8. The first protective insulating film 8 may be formed by thermal CVD or atomic layer deposition (ALD) in place of plasma-enhanced CVD. Furthermore, the first protective insulating film 8 may be formed of a silicon oxide film. Alternatively, the first protective insulating film 8 may have a laminated structure of a silicon nitride film and a silicon oxide film.

[0047] As illustrated in FIG. 1E, an opening 10 is formed in the first protective insulating film 8 and the cap layer 5.

[0048] A resist is applied on the entire surface of the first protective insulating film 8 and processed by lithography, thereby forming a resist mask 9 having an opening 9a that exposes a portion of the first protective insulating film 8 where the gate electrode will be formed.

[0049] The first protective insulating film 8 and the cap layer 5 are subjected to dry etching with the resist mask 9 to form the opening 10. The dry etching is performed with a fluorine-containing gas, for example, a mixed gas of CHF₃, CF₃, and Ar, as an etching gas at a pressure of about 1.7 Torr and an RF power of, for example, about 650 W. The opening 10 that partially exposes the surface of the electron supply layer 4 is formed in the cap layer 5 and the first protective insulating film 8 by this dry etching. The exposed portion of the electron supply layer 4 is a portion where the gate electrode will be formed. In this embodiment, as illustrated in the figure, the dry etching is performed so as to expose a surface of the electron supply layer 4 (to form a shallow recess in the surface). This makes it possible to extend a depletion layer directly below the gate electrode and to form a shallow quantum well. That is, the electrical elimination of the 2DEG directly below the gate electrode provides what is called a normally-off operation (a current between the source electrode and the drain electrode is off at a gate electrode of 0 V).

[0050] Then the resist mask 9 is removed by ashing or the like.

[0051] As illustrated in FIG. 1F, after the formation of a gate insulator 11 and a high-work-function film 12, a conductive material 13 is deposited.

[0052] Specifically, the gate insulator 11 and the high-work-function film 12 are sequentially formed on the first protective insulating film 8 so as to cover the inner surface of the opening 10.

[0053] The gate insulator 11 is formed by depositing, for example, an AlO film having a thickness of, for example, about 20 nm by ALD or the like. The gate insulator 11 may be formed of a TaO film, or a high-dielectric (high-k) oxide or oxynitride film of Hf, Ti, or Zr, in place of the AlO film. Alternatively, the gate insulator 11 may have a laminated structure of two or more selected from the AlO film, the TaO film, and the high-k film.

[0054] After the formation of the gate insulator 11, for example, heat treatment may be performed at, for example, 550° C. for about 60 seconds.

[0055] The high-work-function film 12 is formed by depositing, for example, a TaN film having a thickness of, for example, about 40 nm by physical vapor deposition (PVD) or the like. The term “high-work-function film” indicates a film composed of a conductive material having a work function of 4.5 eV or more. The formation of the high-work-function film 12 provides a shallow quantum well directly below the gate electrode, thereby reducing the 2DEG directly below the gate electrode when the gate voltage is 0 V.

[0056] The conductive material 13, such as Al, is deposited on the entire surface of the high-work-function film 12 by PVD or the like in such a manner that the resulting film of the conductive material 13 has a thickness of about 20 nm to about 500 nm, for example, about 400 nm and that the opening 10 is filled with the conductive material 13 via the gate insulator 11 and the high-work-function film 12.

[0057] As illustrated in FIG. 1G, a resist mask 14 is formed on the conductive material 13.

[0058] A resist is applied on the entire surface of the conductive material 13 and processed by lithography, thereby forming the resist mask 14 that covers a portion of the conductive material 13 where the gate electrode will be formed.

[0059] As illustrated in FIG. 1H, a gate electrode 15 is formed.

[0060] The conductive material 13, the high-work-function film 12, and the gate insulator 11 are dry-etched using the resist mask 14, thereby forming the gate electrode 15 in which the opening 10 is filled with the conductive material 13 via the gate insulator 11 and the high-work-function film 12 and which protrudes from the first protective insulating film 8. Here, the conductive material 13 and the high-work-function film 12 may be dry-etched to leave the gate insulator 11 on the first protective insulating film 8.

[0061] Then the resist mask 14 is removed by ashing or the like.

[0062] In this embodiment, the gate electrode 15 of the AlGaN/GaN HEMT is formed by lithography and dry etching. In this case, the first protective insulating film 8 is formed, and then the gate electrode 15 is formed in such a manner that the opening 10 in the first protective insulating film 8 is filled with the conductive material 13. The presence of the first protective insulating film 8 protects the compound semiconductor layers, thereby minimizing damage from, for example, the dry etching during the formation of the gate electrode to the compound semiconductor layers, such as the electron supply layer 4. As described above, in this embodiment, when the gate electrode 15 is formed, the lithography and the dry etching are performed using the first protective insulating film 8, without employing the lift-off process. Unlike the lift-off process, part of the conductive material is not redeposited above the SiC substrate 1, and the satisfactory gate electrode 15 is formed without damaging the compound semiconductor layers.

[0063] As illustrated in FIG. 1I, a second protective insulating film 16 is formed.

[0064] An insulating film, such as a silicon oxide film, having a thickness of about 300 nm is formed on the entire surface of the first protective insulating film 8 by, for example, plasma-enhanced CVD so as to cover the gate electrode 15, thereby forming the second protective insulating film 16. Here, a bump attributed to a projecting portion of the gate electrode 15 is formed on a portion of the second protective insulating film 16 above the gate electrode 15. To remove the bump, surface polishing is preferably performed by, for example, chemical-mechanical polishing (CMP). In this case, the silicon oxide film or the like is deposited so as to have a thickness of about 500 nm to about 1000 nm, and then a surface portion of the silicon oxide film or the like is polished by CMP so as to reduce the thickness of the silicon oxide film or the like by about 100 nm to about 600 nm, thereby planarizing the surface of the silicon oxide film or the like and forming the second protective insulating film 16. In FIG. 1I, the second protective insulating film 16 having a surface planarized by CMP is illustrated.

[0065] With respect to a method for forming the second protective insulating film, a silicon oxide film or the like may be formed by, for example, spin coating in place of plasma-enhanced CVD and is subjected to curing treatment to form the second protective insulating film.

[0066] As illustrated in FIG. 13, a pair of openings 20a and 20b is formed in the second protective insulating film 16, the first protective insulating film 8, and the cap layer 5.

[0067] A resist is applied on the entire surface of the second protective insulating film 16 and processed by lithography, thereby forming a resist mask 17 having a pair of openings 17a and 17b that expose portions of the second protective insulating film 16 where the source electrode and the drain electrode will be formed.

[0068] The second protective insulating film 16, the first protective insulating film 8, and the cap layer 5 are subjected to dry etching with the resist mask 17 to form the openings 20a and 20b. The dry etching is performed with a fluorine-containing gas, for example, a mixed gas of CHF₃, CF₃, and Ar, as an etching gas at a pressure of 1.7 Torr and an RF power of, for example, 650 W. The openings 20a and 20b that partially expose the surface of the electron supply layer 4 are formed in the cap layer 5, the first protective insulating film 8, and the second protective insulating film 16 by the dry etching. The exposed portions of the electron supply layer 4 are portions where the source electrode and the drain electrode will be formed. Here, in order to reliably expose the portions of the surface of the electron supply layer 4, as illustrated in the figure, a surface of the electron supply layer 4 may be etched (to form a shallow recess in the surface).

[0069] Then the resist mask 17 is removed by ashing or the like.

[0070] As illustrated in FIG. 1K, after the formation of a low-work-function film 18, a conductive material 19 is deposited.

[0071] The low-work-function film 18 is formed on the second protective insulating film 16 as an underlying conductive film so as to cover inner surfaces of the openings 20a and 20b. The term “low-work-function film” indicates a film composed of a conductive material having a work function of less than 4.5 eV. The low-work-function film 18 is formed by depositing one selected from Al, Ti, metal-rich TiN, Ta, metal-rich TaN, Zr, metal-rich TaC, NiSi₂, and Ag in such a manner that the deposited film has a thickness of about 1 nm to about 100 nm. The term “metal-rich TIN” indicates TiN in which the composition ratio of Ti is larger than that of N. The term “metal-rich TaN” indicates TaN in which the composition ratio of Ta is larger than that of N. The term “metal-rich TaC” indicates TaC in which the composition ratio of Ta is larger than that of C. Here, for example, a Ta film is deposited by PVD or the like at a DC power of, for example, 1 kW to 10 kW so as to have a thickness of about 10 nm, thereby forming the low-work-function film 18. The formation of the low-work-function film 18 reduces the barrier between the electrode material and a portion of the electron supply layer 4 directly below the gate electrode, thereby forming the source electrode and the drain electrode with low contact resistance.

[0072] The conductive material 19, such as Al, is deposited on the entire surface of the low-work-function film 18 by PVD or the like at a DC power of, for example, 1 kW to 20 kW in such a manner that the resulting film of the conductive material 19 has a thickness of about 300 nm and that the openings 20a and 20b are filled with the conductive material via the low-work-function film 18.

[0073] As illustrated in FIG. 1L, resist masks 21 are formed on the conductive material 19.

[0074] A resist is applied on the entire surface of the conductive material 19 and processed by lithography, thereby forming the resist masks 21 that cover portions of the conductive material 19 where the source electrode and the drain electrode will be formed.

[0075] As illustrated in FIG. 1M, a source electrode 22 and a drain electrode 23 are formed.

[0076] The conductive material 19 and the low-work-function film 18 are dry-etched using the resist masks 21, thereby forming the source electrode 22 and the drain electrode 23 in which the openings 20a and 20b are filled with the conductive material 19 via the low-work-function film 18 and which protrude from the second protective insulating film 16.

[0077] Then the resist mask 21 is removed by ashing or the like.

[0078] In this embodiment, the source electrode 22 and the drain electrode 23 of the AlGaN/GaN HEMT are formed by lithography and dry etching. In this case, the source electrode 22 and the drain electrode 23 are formed in such a manner that the openings 20a and 20b are filled with the conductive material 19. The presence of the first and second protective insulating films 8 and 16 protects the compound semiconductor layers, thereby minimizing damage from, for example, the dry etching during the formation of the source and drain electrodes to the compound semiconductor layers, such as the electron supply layer 4. As described above, in this embodiment, when the source electrode 22 and the drain electrode 23 are formed, the lithography and the dry etching are performed using the second protective insulating film 16, without employing the lift-off process. Unlike the lift-off process, part of the conductive material is not redeposited above the SiC substrate 1, and the satisfactory source electrode 22 and the satisfactory drain electrode 23 are formed without damaging the compound semiconductor layers.

[0079] The SiC substrate 1 is subjected to heat treatment in, for example, an N₂ atmosphere at about 600° C. for about 60 seconds.

[0080] As illustrated in FIG. 1N, the heat treatment allows Ta in the low-work-function film 18 to react with Al in the conductive material 19, so that the low-work-function film 18 is formed into a TaAl₃ film 18a.

[0081] Details of the reaction by the heat treatment are illustrated in FIG. 2. The heat treatment results in the formation of minute spikes 18b of the TaAl₃ film 18a at bottoms of the openings 20a and 20b, i.e., portions of the electron supply layer 4 directly below the source electrode 22 and the drain electrode 23, thereby reducing the contact resistance between the electron supply layer 4 and the source electrode 22 and between the electron supply layer 4 and the drain electrode 23. Furthermore, Al has a low work function. This also contributes to a reduction in contact resistance.

[0082] As illustrated in FIG. 1O, an interlayer insulator 24 is formed.

[0083] An insulating film, such as a silicon oxide film, having a thickness of about 1000 nm is formed on the entire surface of the second protective insulating film 16 by, for example, plasma-enhanced CVD so as to cover the source electrode 22 and the drain electrode 23, thereby forming the interlayer insulator 24. Here, bumps attributed to projecting portions of the source electrode 22 and the drain electrode 23 are formed on portions of the second protective insulating film 16 above the source electrode 22 and the drain electrode 23. To remove the bumps, surface polishing is preferably performed by, for example, chemical-mechanical polishing (CMP). In this case, the silicon oxide film or the like is deposited so as to have a thickness of about 1000 nm to about 1500 nm, and then a surface portion of the silicon oxide film or the like is polished by CMP so as to reduce the thickness of the silicon oxide film or the like by about 100 nm to about 600 nm, thereby planarizing the surface of the silicon oxide film or the like and forming the interlayer insulator 24. In FIG. 1O, the interlayer insulator 24 having a surface planarized by CMP is illustrated.

[0084] With respect to a method for forming the interlayer insulator, a silicon oxide film or the like may be formed by, for example, spin coating in place of plasma-enhanced CVD and is subjected to curing treatment to form the interlayer insulator.

[0085] As illustrated in FIG. 1P, a connecting portion 26a of the gate electrode 15, a connecting portion 26b of the source electrode 22, and a connecting portion 26c of the drain electrode 23 are formed.

[0086] Specifically, the second protective insulating film 16 and the interlayer insulator 24 are processed by lithography and dry etching, thereby forming openings 25a, 25b, and 25c that partially expose respective surfaces of the gate electrode 15, the source electrode 22, and the drain electrode 23.

[0087] A conductive material, such as Al, is deposited on the interlayer insulator 24 by, for example, sputtering or plating in such a manner that the openings 25a, 25b, and 25c are filled with the conductive material. The conductive material is polished by CMP using a surface of the interlayer insulator 24 as a polishing stopper. In this way, the openings 25a, 25b, and 25c are filled with the conductive material to form the connecting portion 26a of the gate electrode 15, the connecting portion 26b of the source electrode 22, and the connecting portion 26c of the drain electrode 23.

[0088] Subsequently, steps of forming, for example, an upper interlayer insulator and a line are performed to form the AlGaN/GaN HEMT according to this embodiment.

[0089] As described above, according to this embodiment, the gate electrode 15, the source electrode 22, and the drain electrode 23 of the AlGaN/GaN HEMT are formed not by the lift-off process but by a simple method without causing a defect in any pattern, thereby simply and reliably manufacturing the AlGaN/GaN HEMT with excellent device properties.

[0090] Furthermore, in this embodiment, the gate electrode 15 is formed before the formation of the source electrode 22 and the drain electrode 23. This makes it possible to form the gate electrode 15 having a low profile, i.e., a low aspect ratio. In this case, dry etching to form the opening 10 where the gate electrode 15 will be formed can be performed with high accuracy without damaging the electron supply layer 4.

[0091] A modification of the first embodiment will be described below. In this modification, although the structure of an AlGaN/GaN HEMT and a method of manufacturing the AlGaN/GaN HEMT are disclosed as in the first embodiment, the structure of the underlying layers of the gate electrode in the modification differs slightly from that in the first embodiment. Note that components equivalent to those in the first embodiment are designated using the same reference numerals.

[0092] In this modification, the steps illustrated in FIGS. 1A to 1E are performed as in the first embodiment. Note that in this modification, the case where the opening 10 formed in the first protective insulating film 8 and the cap layer 5 slightly has a tapered shape is exemplified.

[0093] As illustrated in FIG. 3A, a gate insulator 31, a high-work-function film 32, and a barrier film 33 are formed. Next, in a step the same as that illustrated in FIG. 1F, the conductive material 13 is deposited so as to come into contact with the barrier film 33.

[0094] The gate insulator 31, the high-work-function film 32, and the barrier film 33 are formed on the first protective insulating film 8 so as to cover the inner surface of the opening 10.

[0095] The gate insulator 31 is formed of an oxide or oxynitride film of one selected from Si, Al, Ti, Ta, Hf, La, Y, and Ni. Alternatively, the gate insulator 31 has a laminated structure of two or more selected from these films. Here, for example, an AlO film is deposited so as to have a thickness of, for example, about 1 nm to about 50 nm, thereby forming the gate insulator 31.

[0096] The high-work-function film 32 is formed by depositing one selected from Au, Ni, Co, nitrogen-rich TiN, nitrogen-rich TaN, carbon-rich TaC, Pt, W, Ru, Ni₃Si, and Pd in such a manner that the deposited film has a thickness of about 1 nm to about 100 nm. The term “nitrogen-rich TIN” indicates TiN in which the composition ratio of N is larger than that of Ti. The term “nitrogen-rich TaN” indicates TaN in which the composition ratio of N is larger than that of Ta. The term “carbon-rich TaC” indicates TaC in which the composition ratio of C is larger than that of Ta. Here, for example, TiN is deposited so as to have a thickness of about 20 nm, thereby forming the high-work-function film 32.

[0097] The barrier film 33 is formed by depositing, for example, a TaN film using PVD, ALD, or the like in such a manner that the TaN film has a thickness of, for example, about 0.1 nm to about 50 nm.

[0098] The barrier film 33 is provided between the high-work-function film 32 and the conductive material 13. The presence of the barrier film 33 prevents Al in the conductive material 13 from reaching a portion of the electron supply layer 4 directly below the gate electrode through the gate insulator 31 when the SiC substrate 1 is subjected to heat treatment at 550° C. to 650° C. in the subsequent step. As described below, a higher proportion of nitrogen in the barrier film 33 results in higher barrier properties of the barrier film 33. In the case where nitrogen-rich TaN is formed as the barrier film 33, the resulting nitrogen-rich TaN film preferably has a thickness of 0.1 nm to 10 nm.

[0099] Alternatively, without forming the barrier film 33, the high-work-function film 32 may be formed of a nitrogen-rich TaN film in the same way as the barrier film 33 (that is, the high-work-function film 32 is formed so as to also serve as a barrier film), and then the conductive material 13 may be deposited so as to come into contact with the high-work-function film 32.

[0100] Steps the same as those illustrated in FIGS. 1G to 1M according to the first embodiment are performed.

[0101] In the step illustrated in FIG. 1H, the conductive material 13, the barrier film 33, and the high-work-function film 32 are dry-etched using the resist mask 14 to form the gate electrode 15. Here, the case where the gate insulator 31 is not etched and is left on the first protective insulating film 8 is exemplified. Alternatively, the gate insulator 31 may also be etched.

[0102] As illustrated in FIG. 3B, the SiC substrate 1 is subjected to heat treatment. This heat treatment is performed for 0 to 180 seconds at about 550° C. to about 650° C. in an atmosphere selected from the group consisting of noble gases, nitrogen, oxygen, ammonia, hydrogen gas, and mixtures thereof. Here, for example, the heat treatment is performed in an N₂ atmosphere at 600° C. for 60 seconds. As described in the first embodiment, the low-work-function film 18 is formed into the TaAl₃ film 18a by the heat treatment to form spikes, thereby reducing the contact resistance between the electron supply layer 4 and the source electrode 22 and between the electron supply layer 4 and the drain electrode 23. As described below, with respect to the temperature in the heat treatment, the reactivity between Ta and Al is increased at 550° C. or higher, maximized at 650° C., and satisfactorily maintained at 700° C. For this reason, an appropriate temperature in the heat treatment is in the range of about 550° C. to about 700° C. and preferably about 550° C. to about 650° C. as described above.

[0103] In this modification, the barrier film 33 is provided between the gate electrode 15 and the high-work-function film 32. The presence of the barrier film 33 prevents the diffusion of Al in the gate electrode 15 to the high-work-function film 32 during the heat treatment. Thus, spikes of Al of the gate electrode 15 are not formed for the gate insulator 31, so that the occurrence of gate leakage is suppressed. Furthermore, the presence of the barrier film 33 results in a predetermined shallow quantum well without diffusing Al having a low work function into a portion directly above the gate insulator 31.

[0104] Subsequently, steps the same as those illustrated in FIGS. 1N and 1O according to the first embodiment are performed to form the connecting portions 26a, 26b, and 26c of the gate electrode 15, the source electrode 22, and the drain electrode 23.

[0105] Subsequently, steps of forming, for example, an upper interlayer insulator and a line are performed to form the AlGaN/GaN HEMT according to this modification.

[0106] Some experiments to check the effects of this modification will be described below.

[0107] Thermal oxide films (silicon oxide films) were formed on predetermined blanket substrates. A Ta film was formed on each of the thermal oxide films so as to have a thickness of about 10 nm. Subsequently, an Al film was formed on the Ta film so as to have a thickness of about 300 nm. In this way, samples were manufactured. These samples were subjected to heat treatment at different temperatures and then characterized by X-ray diffraction spectroscopy (XRD). FIG. 4 illustrates the results. The results demonstrated that the peak of TaAl₃ was observed at the heat treatment temperature of about 550° C. This experiment demonstrated that heat treatment at 550° C. to 650° C. allowed Ta and Al to interdiffuse, thereby forming a TaAl₃ film.

[0108] In FIG. 4 of Experiment 1, the relationship between the intensity of a peak attributed to TaAl₃ <101> and the heat treatment temperature was studied. FIG. 5 illustrates the results. The results demonstrated that the intensity of the peak attributed to TaAl₃ <101> was significantly increased at a heat treatment temperature of 550° C. or higher. This experiment demonstrated that in the case where the source electrode 22 and the drain electrode 23, which are contact portions, were subjected to heat treatment, the heat treatment temperature was preferably 550° C. or higher.

[0109] Samples manufactured as in Experiment 1 were subjected to heat treatment at different temperatures. The sheet resistance of each heat-treated sample was measured. FIG. 6 illustrates the results. The results demonstrated that the sheet resistance was increased by the heat treatment. This experiment demonstrated that the heat treatment allowed Ta and Al to interdiffuse.

[0110] Thermal oxide films were formed on blanket substrates. A Ta film, a TaN film, a Ta₂N (metal-rich) film, and a TiN film were formed on the respective thermal oxide films. Furthermore, an Al film was formed on each of the Ta film, the TaN film, the Ta₂N film, and the TiN film so as to have a thickness of about 300 nm, thereby manufacturing samples. The samples were subjected to heat treatment at different temperatures. The sheet resistance of each heat-treated sample was measured. FIG. 7 illustrates the results. The results demonstrated that the degree of an increase in sheet resistance varied depending on the samples. Ta, TaN, and TiN have work functions of 4.3 eV, 4.6 eV, and 4.8 eV, respectively. FIG. 7 demonstrates that the degree of the increase in the sheet resistance of the sample including TiN having the highest work function is the highest and that TiN and Al interdiffuse easily.

[0111] Thermal oxide films were formed on blanket substrates. TaN films were formed on the respective thermal oxide films at different deposition conditions. The TaN films of the samples were formed by PVD at different DC power levels, provided that the deposition time and the N₂ partial pressure (N₂/Ar+N₂) were fixed to about 3 seconds and about 60%, respectively. Furthermore, an Al film was formed on each of the TaN films so as to have a thickness of about 300 nm, thereby manufacturing samples. The samples were subjected to heat treatment at about 600° C. The sheet resistance of each heat-treated sample was measured. FIG. 8 illustrates the results. It is commonly known that in the case of forming a TaN film by PVD, a reduction in DC power results in an increase in the proportion of nitrogen in TaN. Also in this experiment, nitrogen-rich TaN films were manufactured at lower DC power levels. The experimental results demonstrate that an increase in the proportion of nitrogen in TaN results in a reduction in sheet resistance, which means a reduction in the impurity content in Al. This indicates that a higher proportion of nitrogen in TaN results in effective suppression of the reaction with Al, i.e., higher barrier properties against Al.

[0112] A thermal oxide film was formed on a blanket substrate. A TiN film and a nitrogen-rich TaN were formed on the thermal oxide films. Furthermore, an Al film is formed on the TaN film so as to have a thickness of about 300 nm, thereby manufacturing a sample. As reference samples, thermal oxide films were formed on blanket substrates. A TiN film, a TaN film, and a TaN film+a nitrogen-rich TaN film were formed on the respective thermal oxide films. An Al film was formed on each of the films so as to have a thickness of about 300 nm. Each of the nitrogen-rich TaN films was formed by PVD at a DC power as low as about 1 kW so as to have a thickness of about 1 nm, provided that the N₂ partial pressure (N₂/Ar+N₂) was fixed to about 60%. The resulting TaN film had a very high nitrogen content. The sample and the reference samples were subjected to heat treatment at about 600° C. The sheet resistance of each of the sample and reference samples was measured. FIG. 9 illustrates the results. The sample in which the nitrogen-rich TaN film was arranged between the TiN film and the Al film had a low sheet resistance. This demonstrates that the nitrogen-rich TaN film prevents the TiN film and the Al film from being mixed. This experiment demonstrated that the nitrogen-rich TaN film had excellent barrier properties against Al and is thus suitable as a barrier film against Al.

[0113] As described above, according to this modification, the gate electrode 15, the source electrode 22, and the drain electrode 23 of the AlGaN/GaN HEMT are formed not by the lift-off process but by a simple method without causing a defect in any pattern, thereby simply and reliably manufacturing the AlGaN/GaN HEMT having excellent device properties, in which the occurrence of gate leakage is prevented.

[0114] In this embodiment, with respect to an AlGaN/GaN HEMT, the case where a source electrode and a drain electrode are formed before the formation of a gate electrode. Note that components equivalent to those in the first embodiment are designated using the same reference numerals.

[0115] In this embodiment, the steps illustrated in FIGS. 1A to 1D are performed as in the first embodiment.

[0116] As illustrated in FIG. 10A, a resist mask 41 is formed on the first protective insulating film 8.

[0117] A resist is applied on the entire surface of the first protective insulating film 8 and processed by lithography, thereby forming the resist mask 41 having a pair of openings 41a and 41b that exposes portions of the first protective insulating film 8 where the source electrode and the drain electrode will be formed.

[0118] As illustrated in FIG. 10B, a pair of openings 40a and 40b is formed in the first protective insulating film 8 and the cap layer 5.

[0119] The first protective insulating film 8 and the cap layer 5 are subjected to dry etching with the resist mask 41 to form the openings 40a and 40b. The dry etching is performed with a fluorine-containing gas, for example, a mixed gas of CHF₃, CF₃, and Ar, as an etching gas at a pressure of about 1.7 Torr and an RF power of, for example, about 650 W. The openings 40a and 40b that partially expose the surface of the electron supply layer 4 are formed in the cap layer 5 and the first protective insulating film 8 by the dry etching. The exposed portions of the electron supply layer 4 are portions where the source electrode and the drain electrode will be formed. Here, in order to reliably expose the portions of the surface of the electron supply layer 4, as illustrated in the figure, a surface of the electron supply layer 4 may be etched (to form a shallow recess in the surface).

[0120] Then the resist mask 41 is removed by ashing or the like.

[0121] As illustrated in FIG. 10C, after the formation of a low-work-function film 42, a conductive material 43 is deposited.

[0122] The low-work-function film 42 is formed on the first protective insulating film 8 as an underlying conductive film so as to cover inner surfaces of the openings 40a and 40b. The low-work-function film 42 is formed by depositing one selected from Al, Ti, metal-rich TiN, Ta, metal-rich TaN, Zr, metal-rich TaC, NiSi₂, and Ag in such a manner that the deposited film has a thickness of about 1 nm to about 100 nm. Here, for example, a Ta film is deposited by PVD or the like at a DC power of, for example, 1 kW to 10 kW so as to have a thickness of about 10 nm, thereby forming the low-work-function film 42. The formation of the low-work-function film 42 reduces the barrier between the electrode material and a portion of the electron supply layer 4 directly below the gate electrode, thereby forming the source electrode and the drain electrode with low contact resistance.

[0123] The conductive material 43, such as Al, is deposited on the entire surface of the low-work-function film 42 by PVD or the like at a DC power of, for example, 1 kW to 10 kW in such a manner that the resulting film of the conductive material 19 has a thickness of about 300 nm and that the openings 40a and 40b are filled with the conductive material via the low-work-function film 42.

[0124] As illustrated in FIG. 10D, a resist mask 44 is formed on the conductive material 43.

[0125] A resist is applied on the entire surface of the conductive material 43 and processed by lithography, thereby forming the resist mask 44 that covers portions of the conductive material 43 where the source electrode and the drain electrode will be formed.

[0126] As illustrated in FIG. 10E, a source electrode 45 and a drain electrode 46 are formed.

[0127] The conductive material 43 and the low-work-function film 42 are dry-etched using the resist mask 44. Here, in order to reliably separate the source electrode and the drain electrode from each other, as illustrated in the figure, etching may be performed so as to expose a surface of the first protective insulating film 8. This dry etching results in the formation of the source electrode 45 and the drain electrode 46 in which the openings 40a and 40b are filled with the conductive material 43 via the low-work-function film 42 and which protrude from the first protective insulating film 8.

[0128] Then the resist mask 44 is removed by ashing or the like.

[0129] In this embodiment, the source electrode 45 and the drain electrode 46 of the AlGaN/GaN HEMT are formed by lithography and dry etching. Here, the first protective insulating film 8 is formed, and then the source electrode 45 and the drain electrode 46 are formed in such a manner that the openings 40a and 40b are filled with the conductive material 43. The presence of the first protective insulating film 8 protects the compound semiconductor layers, thereby minimizing damage from, for example, the dry etching during the formation of the source and drain electrodes to the compound semiconductor layers, such as the electron supply layer 4. As described above, in this embodiment, when the source electrode 45 and the drain electrode 46 are formed, the lithography and the dry etching are performed using the first protective insulating film 8, without employing the lift-off process. Unlike the lift-off process, part of the conductive material is not redeposited above the SiC substrate 1, and the satisfactory source electrode 45 and the drain electrode 46 are formed without damaging the compound semiconductor layers.

[0130] The SiC substrate 1 is subjected to heat treatment in, for example, an N₂ atmosphere at about 600° C. for about 60 seconds.

[0131] As illustrated in FIG. 10F, the heat treatment allows Ta in the low-work-function film 42 to react with Al in the conductive material 43, so that the low-work-function film 42 is formed into a TaAl₃ film 42a. The heat treatment results in the formation of minute spikes of the TaAl₃ film 42a at bottoms of the openings 40a and 40b, i.e., portions of the electron supply layer 4 directly below the source electrode 45 and the drain electrode 46, thereby reducing the contact resistance between the electron supply layer 4 and the source electrode 45 and between the electron supply layer 4 and the drain electrode 46. Furthermore, Al has a low work function. This also contributes to a reduction in contact resistance.

[0132] As illustrated in FIG. 10G, the second protective insulating film 16 is formed.

[0133] An insulating film, such as a silicon oxide film, having a thickness of about 300 nm is formed on the entire surface of the first protective insulating film 8 by, for example, plasma-enhanced CVD so as to cover the source electrode 45 and the drain electrode 46, thereby forming the second protective insulating film 16. Here, bumps attributed to projecting portions of the source electrode 45 and the drain electrode 46 are formed on portions of the second protective insulating film 16 above the source electrode 45 and the drain electrode 46. To remove the bumps, surface polishing is preferably performed by, for example, CMP. In this case, for example, the silicon oxide film or the like is deposited so as to have a thickness of about 500 nm to about 1000 nm, and then a surface portion of the silicon oxide film or the like is polished by CMP so as to reduce the thickness of the silicon oxide film or the like by about 100 nm to about 600 nm, thereby planarizing the surface of the silicon oxide film or the like and forming the second protective insulating film 16. In FIG. 10G, the second protective insulating film 16 having a surface planarized by CMP is illustrated.

[0134] With respect to a method for forming the second protective insulating film, a silicon oxide film or the like may be formed by, for example, spin coating in place of plasma-enhanced CVD and is subjected to curing treatment to form the second protective insulating film.

[0135] As illustrated in FIG. 10H, a resist mask 47 is formed on the second protective insulating film 16.

[0136] A resist is applied on the entire surface of the second protective insulating film 16 and processed by lithography, thereby forming the resist mask 47 having an opening 47a that exposes a portion of the second protective insulating film 16 where the gate electrode will be formed.

[0137] As illustrated in FIG. 10I, the second protective insulating film 16, the first protective insulating film 8, and the cap layer 5 are subjected to dry etching to form an opening 50. The dry etching is performed with a fluorine-containing gas, for example, a mixed gas of CHF₃, CF₃, and Ar, as an etching gas at a pressure of about 1.7 Torr and an RF power of, for example, about 650 W. The opening 50 that partially exposes the surface of the electron supply layer 4 is formed in the second protective insulating film 16, the first protective insulating film 8, and the cap layer 5 by this dry etching. The exposed portion of the electron supply layer 4 is a portion where the gate electrode will be formed. In this embodiment, as illustrated in the figure, a surface of the electron supply layer 4 is also subjected to dry etching (to form a shallow recess in the surface). This makes it possible to extend a depletion layer directly below the gate electrode and to form a shallow quantum well. That is, the electrical elimination of the 2DEG directly below the gate electrode provides a normally-off operation.

[0138] Then the resist mask 47 is removed by ashing or the like.

[0139] As illustrated in FIG. 10J, after the formation of a gate insulator 48 and a high-work-function film 49, a conductive material 51 is deposited.

[0140] The gate insulator 48 and the high-work-function film 49 are sequentially formed on the second protective insulating film 16 so as to cover the inner surface of the opening 50.

[0141] The gate insulator 48 is formed by depositing, for example, an AlO film having a thickness of, for example, about 20 nm by ALD or the like. The gate insulator 48 may be formed of a TaO film, or a high-dielectric (high-k) oxide or oxynitride film of Hf, Ti, or Zr, in place of the AlO film. Alternatively, the gate insulator 48 may have a laminated structure of two or more selected from the AlO film, the TaO film, and the high-k film.

[0142] The high-work-function film 49 is formed by depositing, for example, a TaN film having a thickness of, for example, about 40 nm by physical vapor deposition (PVD) or the like. The formation of the high-work-function film 49 provides a shallow quantum well directly below the gate electrode, thereby reducing the 2DEG directly below the gate electrode when the gate voltage is 0 V.

[0143] The conductive material 51, such as Al, is deposited on the entire surface of the high-work-function film 49 by PVD or the like in such a manner that the resulting film of the conductive material 51 has a thickness of about 20 nm to about 500 nm, for example, about 400 nm and that the opening 50 is filled with the conductive material 51 via the gate insulator 48 and the high-work-function film 49.

[0144] As illustrated in FIG. 10K, a resist mask 52 is formed on the conductive material 51.

[0145] A resist is applied on the entire surface of the conductive material 51 and processed by lithography, thereby forming the resist mask 52 that covers a portion of the conductive material 51 where the gate electrode will be formed.

[0146] As illustrated in FIG. 10L, a gate electrode 53 is formed.

[0147] The conductive material 51, the high-work-function film 49, and the gate insulator 48 are dry-etched using the resist mask 52, thereby forming the gate electrode 53 in which the opening 50 is filled with the conductive material 51 via the gate insulator 48 and the high-work-function film 49 and which protrudes from the second protective insulating film 16. Here, the conductive material 51 and the high-work-function film 49 may be dry-etched to leave the gate insulator 48 on the second protective insulating film 16.

[0148] Then the resist mask 52 is removed by ashing or the like.

[0149] In this embodiment, the gate electrode 53 of the AlGaN/GaN HEMT is formed by lithography and dry etching. In this case, the first and second protective insulating films 8 and 16 are formed, and then the gate electrode 53 is formed in such a manner that the opening 50 is filled with the conductive material 51. The presence of the first and second protective insulating films 8 and 16 protects the compound semiconductor layers, thereby minimizing damage from, for example, the dry etching during the formation of the gate electrode to the compound semiconductor layers, such as the electron supply layer 4. As described above, in this embodiment, when the gate electrode 53 is formed, the lithography and the dry etching are performed using the first and second protective insulating films 8 and 16, without employing the lift-off process. Unlike the lift-off process, part of the conductive material is not redeposited above the SiC substrate 1, and the satisfactory gate electrode 53 is formed without damaging the compound semiconductor layers.

[0150] In this embodiment, the source electrode 45 and the drain electrode 46 are formed before the formation of the gate electrode 53. Thus, heat treatment to reduce the contact resistance of the source electrode 45 and the drain electrode 46 can be performed in a state in which the gate electrode is not formed. So, the barrier layer against Al as described in the modification of the first embodiment may not be formed, thereby leading to a simple manufacturing process.

[0151] As illustrated in FIG. 10M, the interlayer insulator 24 is formed.

[0152] An insulating film, such as a silicon oxide film, having a thickness of about 1000 nm is formed on the entire surface of the second protective insulating film 16 by, for example, plasma-enhanced CVD so as to cover the gate electrode 53, thereby forming the interlayer insulator 24. Here, a bump attributed to a projecting portion of the gate electrode 53 is formed on a portion of the interlayer insulator 24 above the gate electrode 53. To remove the bump, surface polishing is preferably performed by, for example, chemical-mechanical polishing (CMP). In this case, the silicon oxide film or the like is deposited so as to have a thickness of about 1000 nm to about 1500 nm, and then a surface portion of the silicon oxide film or the like is polished by CMP so as to reduce the thickness of the silicon oxide film or the like by about 100 nm to about 600 nm, thereby planarizing the surface of the silicon oxide film or the like and forming the interlayer insulator 24. In FIG. 10M, the interlayer insulator 24 having a surface planarized by CMP is illustrated.

[0153] With respect to a method for forming the interlayer insulator, a silicon oxide film or the like may be formed by, for example, spin coating in place of plasma-enhanced CVD and is subjected to curing treatment to form the interlayer insulator.

[0154] As illustrated in FIG. 10N, a connecting portion 55a of the gate electrode 53, a connecting portion 55b of the source electrode 45, and a connecting portion 55c of the drain electrode 46 are formed.

[0155] The second protective insulating film 16 and the interlayer insulator 24 are processed by lithography and dry etching, thereby forming openings 54a, 54b, and 54c that partially expose respective surfaces of the gate electrode 53, the source electrode 45, and the drain electrode 46.

[0156] A conductive material, such as Al, is deposited on the interlayer insulator 24 by, for example, sputtering or plating in such a manner that the openings 54a, 54b, and 54c are filled with the conductive material. The conductive material is polished by CMP using a surface of the interlayer insulator 24 as a polishing stopper. In this way, the openings 54a, 54b, and 54c are filled with the conductive material to form the connecting portion 55a of the gate electrode 53, the connecting portion 55b of the source electrode 45, and the connecting portion 55c of the drain electrode 46.

[0157] Subsequently, steps of forming, for example, an upper interlayer insulator and a line are performed to form the AlGaN/GaN HEMT according to this embodiment.

[0158] According to this embodiment, the gate electrode 53, the source electrode 45, and the drain electrode 46 of the AlGaN/GaN HEMT are formed not by the lift-off process but by a simple method without causing a defect in any pattern, thereby simply and reliably manufacturing the AlGaN/GaN HEMT having excellent device properties, in which the occurrence of gate leakage is prevented.

[0159] In this embodiment, as with the first embodiment, the case where a gate electrode is formed before the formation of a source electrode and drain electrode is described. This embodiment is characterized by etching to form the gate electrode, the source electrode, and the drain electrode. Note that components equivalent to those in the first embodiment are designated using the same reference numerals.

[0160] In this embodiment, the step illustrated in FIG. 1A is performed as in the first embodiment.

[0161] Subsequently, as illustrated in FIG. 11A, openings 60a, 60b, and 60c are formed in the cap layer 5.

[0162] A resist is applied on the entire surface of the cap layer 5 and processed by lithography, thereby forming a resist mask 61 having openings 61a, 61b, and 61c that exposes portions of the cap layer 5 where the gate electrode, the source electrode, and the drain electrode will be formed.

[0163] The cap layer 5 is dry-etched with the resist mask 61 to form the openings 61a, 61b, and 61c. In the dry etching, chlorine gas is used as an etching gas. A parallel plate-type etching apparatus, an electron cyclotron resonance (ECR) etching apparatus, an inductively coupled plasma (ICP) etching apparatus, or the like is used. In the case of using the parallel plate-type etching apparatus, for example, etching is performed at a substrate temperature of 25° C. to 150° C., a pressure of 10 mTorr to 2 Torr, and an RF power of, for example, 50 W to 500 W. In the case of using the ECR etching apparatus or the ICP etching apparatus, for example, etching is performed at a pressure of 1 mTorr to 50 mTorr and a bias power of, for example, 0 W to 80 W.

[0164] The openings 60a, 60b, and 60c that expose portions of the electron supply layer 4 are formed in the cap layer 5 by the dry etching. The exposed portions of the electron supply layer 4 are portions where the gate electrodes will be formed. In this embodiment, as illustrated in the figure, a surface of the electron supply layer 4 is etched (to form shallow recesses in the surface). As a result, with respect to the opening 61a, it is possible to extend a depletion layer directly below the gate electrode and to form a shallow quantum well. That is, the electrical elimination of the 2DEG directly below the gate electrode provides a normally-off operation.

[0165] In this embodiment, the case where the openings 60a, 60b, and 60c are simultaneously formed is exemplified. Alternatively, each of the openings may be separately formed. Also in this case, as described above, when the opening 60a is formed, the surface of the electron supply layer 4 is subjected to dry etching. Furthermore, in order to reliably etch the cap layer 5, also for the openings 60b and 60c, the surface of the electron supply layer 4 is preferably subjected to dry etching.

[0166] Then the resist mask 61 is removed by ashing or the like.

[0167] Here, the electron supply layer 4 may be physically damaged by etching when the openings 60a, 60b, and 60c are formed. The physical damage indicates the occurrence of the cleavage of interatomic bonds in the electron supply layer 4. In particular, in the case where the shallow recesses are formed in the surface of the electron supply layer 4, care may be required. If the electron supply layer 4 is physically damaged, a predetermined quantum well is not formed, so that the 2DEG is not formed even when a gate voltage is applied.

[0168] In this embodiment, assuming that the electron supply layer 4 is damaged by dry etching, heat treatment is performed in order to recover the damage. As illustrated in FIG. 11B, the SiC substrate 1 is subjected to heat treatment. The heat treatment is performed in, for example, a nitrogen atmosphere for 0 to 180 seconds at about 700° C. to about 900° C. The heat treatment may be performed by what is called 0-second annealing (msec annealing). The heat treatment results in the recombination of the cleaved interatomic bonds in the electron supply layer 4 due to dry etching when the openings 60a, 60b, and 60c are formed, thereby recover the physical damage. As described below, a temperature range in which the physical damage is sufficiently recovered is about 700° C. to about 900° C. Thus, this temperature range is an appropriate temperature range for the heat treatment.

[0169] As illustrated in FIG. 11C, the element isolation structures 7 are formed.

[0170] A resist mask that covers an element active region and exposes element isolation regions on the cap layer 5 is formed. An impurity, such as Ar, is ion-implanted into the element active region extending to the cap layer 5, the electron supply layer 4, the electron transit layer 3, the buffer layer 2, and an upper portion of the SiC substrate 1 using the resist mask. The ion implantation is performed at an acceleration energy of, for example, about 100 eV and a dose of, for example, about 1.0×10¹³/cm². The element isolation structures 7 are formed by the ion implantation. In the element isolation structures 7, the crystal structures of AlN, GaN, and AlGaN are broken to eliminate the 2DEG in the element isolation structures 7; hence, the element isolation structures 7 serve as insulating regions.

[0171] Then the resist mask is removed by ashing or the like.

[0172] The element isolation structures 7 serve as the insulating regions due to the breakage of the crystal structure. Thus, for example, if the heat treatment for damage recovery is performed after the formation of the element isolation structures 7, the cleaved interatomic bonds in the element isolation structures 7 are also recombined, thereby eliminating the insulation required for element isolation. In this embodiment, the heat treatment for damage recovery is thus performed before the formation of the element isolation structures 7. This makes it possible to ensure the damage recovery of the electron supply layer 4 and the formation of the predetermined element isolation structures 7.

[0173] As illustrated in FIG. 11D, the first protective insulating film 8 is formed.

[0174] An insulating film, for example, a silicon nitride film, having a thickness of about 20 nm to 500 nm, for example, about 300 nm is formed on the entire surface above the SiC substrate 1 by, for example, plasma-enhanced CVD, thereby forming the first protective insulating film 8. The first protective insulating film 8 may be formed by thermal CVD or ALD in place of plasma-enhanced CVD. Furthermore, the first protective insulating film 8 may be formed of a silicon oxide film. Alternatively, the first protective insulating film 8 may have a laminated structure of a silicon nitride film and a silicon oxide film.

[0175] As illustrated in FIG. 11E, a resist mask 62 is formed on the first protective insulating film 8.

[0176] A resist is applied on the entire surface of the first protective insulating film 8 and processed by lithography, thereby forming the resist mask 62 having an opening 62a that exposes a portion of the first protective insulating film 8 where the gate electrode will be formed.

[0177] As illustrated in FIG. 11F, an opening 8a is formed by damage-less etching in a portion of the first protective insulating film 8 where the gate electrode will be formed.

[0178] As described above, in a compound semiconductor device, such as an AlGaN/GaN HEMT, if the electron supply layer 4 is physically damaged by etching, a predetermined quantum well is not formed, so that the 2DEG is not formed even when a gate voltage is applied. Thus, special care is required. In this embodiment, in order to prevent physical damage to the electron supply layer 4 also in etching the first protective insulating film 8, the damage-less etching is performed using the resist mask 62. The damage-less etching employed here is what is called isotropic etching. Wet etching or isotropic dry etching under specific conditions is employed.

[0179] In the case where wet etching is performed, a fluorine-containing chemical solution is used as an etching solution. Examples of the etching solution include a mixed solution containing 0.1%-50% hydrofluoric acid and 50%-0.1% water; and a mixed solution containing 0.1%-25% hydrofluoric acid, 0.1%-25% ammonium fluoride, and 50%-99.8% water.

[0180] In the case where dry etching is performed, for example, a parallel plate-type etching process, an ECR etching process, an ICP etching process, or a downflow etching process is employed.

[0181] For example, in the case of the parallel plate-type etching process, etching is performed in an atmosphere selected from CF₄, SF₆, CHF₃, and a fluorine-containing gas at a substrate temperature of about 25° C. to about 200° C., a pressure of 10 mTorr to 2 Torr, and an RF power of 10 W to 400 W.

[0182] For example, in the case of the ECR etching process, etching is performed in an atmosphere selected from CF₄, SF₆, CHF₃, and a fluorine-containing gas at a substrate temperature of about 25° C. to about 200° C., a pressure of 1 mTorr to 1 Torr, and an RF power of 5 W to 80 W.

[0183] For example, in the case of the ICP etching process, etching is performed in an atmosphere selected from CF₄, SF₆, CHF₃, and a fluorine-containing gas at a substrate temperature of about 25° C. to about 200° C., a pressure of 1 mTorr to 50 mTorr, and a bias power of 5 W to 80 W.

[0184] For example, in the case of the downflow etching process, etching is performed in an atmosphere selected from CF₄, SF₆, and a fluorine-containing gas at a substrate temperature of about 25° C. to about 200° C., a pressure of 300 mTorr to 3 Torr, and a power of 100 W to 1500 W.

[0185] The first protective insulating film 8 is subjected to the damage-less etching to form the opening 8a in the first protective insulating film 8, the opening 8a having a shape in which the diameter of an upper portion of the opening 8a is larger than that of the opening 62a in the resist mask 62 and the diameter of a lower portion of the opening 8a is smaller than the diameter of the upper portion. The opening 8a communicates with the opening 60a to form one opening. Although the bottom of the opening 60a, i.e., the recess (where the gate electrode will be formed) of the electron supply layer 4, is exposed at the bottom of the opening 8a, the recess is not physically damaged. Thus, a predetermined satisfactory 2DEG is formed in the vicinity of the interface between the electron transit layer 3 and the electron supply layer 4.

[0186] Then the resist mask 62 is removed by ashing or the like.

[0187] As illustrated in FIG. 11G, a gate insulator 63 and a high-work-function film 64 are formed.

[0188] The gate insulator 63 and the high-work-function film 64 are formed on the first protective insulating film 8 so as to cover inner surfaces of the openings 8a and 60a.

[0189] The gate insulator 63 is formed by depositing, for example, an AlO film having a thickness of, for example, about 20 nm by ALD or the like. The gate insulator 63 may be formed of a TaO film, or a high-dielectric (high-k) oxide or oxynitride film of Hf, Ti, or Zr, in place of the AlO film. Alternatively, the gate insulator 63 may have a laminated structure of two or more selected from the AlO film, the TaO film, and the high-k film.

[0190] After the formation of the gate insulator 63, heat treatment may be performed at, for example, about 550° C. for about 60 seconds.

[0191] The high-work-function film 64 is formed by depositing, for example, a TaN film having a thickness of, for example, about 40 nm by physical vapor deposition (PVD) or the like. The term “high-work-function film” indicates a film composed of a conductive material having a work function of 4.5 eV or more. The formation of the high-work-function film 64 provides a shallow quantum well directly below the gate electrode, thereby reducing the 2DEG directly below the gate electrode when the gate voltage is 0 V.

[0192] As illustrated in FIG. 11H, a conductive material 65 is formed on the high-work-function film 64.

[0193] The conductive material 65, such as Al, is deposited on the entire surface of the high-work-function film 64 by PVD or the like in such a manner that the resulting film of the conductive material 65 has a thickness of about 20 nm to about 500 nm, for example, about 400 nm and that the openings 8a and 60a is filled with the conductive material 65 via the gate insulator 63 and the high-work-function film 64.

[0194] As illustrated in FIG. 11I, a resist mask 66 is formed on the conductive material 65.

[0195] A resist is applied on the entire surface of the conductive material 65 and processed by lithography, thereby forming the resist mask 66 that covers a portion of the conductive material 65 where the gate electrode will be formed.

[0196] As illustrated in FIG. 11J, a gate electrode 67 is formed.

[0197] The conductive material 65, the high-work-function film 64, and the gate insulator 63 are dry-etched using the resist mask 66. Here, in order to reliably form the gate electrode, as illustrated in the figure, etching may be performed so as to expose a surface of the first protective insulating film 8. The dry etching results in the formation of the gate electrode 67 in which the openings 8a and 60a are filled with the conductive material 65 via the gate insulator 63 and the high-work-function film 64 and which protrudes from the first protective insulating film 8.

[0198] Then the resist mask 66 is removed by ashing or the like.

[0199] In this embodiment, the gate electrode 67 of the AlGaN/GaN HEMT is formed by lithography and dry etching. In this case, the first protective insulating film 8 is formed, and then the gate electrode 67 is formed in such a manner that the opening 8a in the first protective insulating film 8 is filled with the conductive material 65. The presence of the first protective insulating film 8 and the damage-less etching prevent physical damage to the electron supply layer 4 when the gate electrode is formed. As described above, in this embodiment, when the gate electrode 67 is formed, the lithography and the damage-less etching are performed using the first protective insulating film 8, without employing the lift-off process. Unlike the lift-off process, part of the conductive material is not redeposited above the SiC substrate 1, and the satisfactory gate electrode 67 is formed without physically damaging the compound semiconductor layers.

[0200] As illustrated in FIG. 11K, the second protective insulating film 16 is formed.

[0201] An insulating film, such as a silicon oxide film, having a thickness of about 300 nm is formed on the entire surface of the first protective insulating film 8 by, for example, plasma-enhanced CVD so as to cover the gate electrode 67, thereby forming the second protective insulating film 16. Here, a bump attributed to a projecting portion of the gate electrode 67 is formed on a portion of the second protective insulating film 16 above the gate electrode 67. To remove the bump, surface polishing is preferably performed by, for example, CMP. In this case, the silicon oxide film or the like is deposited so as to have a thickness of about 500 nm to about 1000 nm, and then a surface portion of the silicon oxide film or the like is polished by CMP so as to reduce the thickness of the silicon oxide film or the like by about 100 nm to about 600 nm, thereby planarizing the surface of the silicon oxide film or the like and forming the second protective insulating film 16. In FIG. 11K, the second protective insulating film 16 having a surface planarized by CMP is illustrated.

[0202] With respect to a method for forming the second protective insulating film, a silicon oxide film or the like may be formed by, for example, spin coating in place of plasma-enhanced CVD and is subjected to curing treatment to form the second protective insulating film.

[0203] As illustrated in FIG. 11L, a resist mask 68 is formed on the second protective insulating film 16.

[0204] A resist is applied on the entire surface of the second protective insulating film 16 and processed by lithography, thereby forming the resist mask 68 having a pair of openings 68a and 68b that exposes portions of the second protective insulating film 16 where the source electrode and the drain electrode will be formed.

[0205] In steps illustrated in FIGS. 11M and 11N, two-stage etching is performed.

[0206] As illustrated in FIG. 11M, a pair of openings 69a and 69b is formed so as to extend from a surface of the second protective insulating film 16 to the middle portion of the first protective insulating film 8.

[0207] The openings 69a and 69b are formed by dry etching from the surface of the second protective insulating film 16 to the middle portion of the first protective insulating film 8 using the resist mask 68. The dry etching is performed at a pressure of about 1.7 Torr and an RF power of, for example, about 650 W using a fluorine-containing gas, such as a mixed gas of CHF₃, CF₃, and Ar, as an etching gas in such a manner that etching is stopped at the middle of the first protective insulating film 8. This dry etching results in the formation of the openings 69a and 69b, each extending to the middle portion of the first protective insulating film 8 through the second protective insulating film 16, and the first protective insulating film 8 being left at the bottom of each of the openings 69a and 69b.

[0208] Then the resist mask 69 is removed by ashing or the like.

[0209] The dry etching illustrated in FIG. 11M is performed so as to expose the middle portion of the first protective insulating film 8. Thus, the first protective insulating film 8 is left at the bottom of each of the openings 69a and 69b. So, the dry etching does not physically damage the electron supply layer 4.

[0210] As illustrated in FIG. 11N, a resist mask 70 is formed.

[0211] A resist is applied on the entire surface of the second protective insulating film 16 in such a manner that the openings 69a and 69b are filled with the resist. The resist is processed by lithography, thereby forming the resist mask 70 having a pair of openings 70a and 70b that are located in the openings 69a and 69b, the resist mask 70 covering the second protective insulating film 16 and inner side walls of the openings 69a and 69b, and the diameter (width) of each of the openings 70a and 70b being a smaller than that of a corresponding one of the openings 69a and 69b.

[0212] As illustrated in FIG. 11O, a pair of openings 71a and 71b is formed in the first protective insulating film 8 by damage-less etching.

[0213] For a compound semiconductor device, such as an AlGaN/GaN HEMT, if the electron supply layer 4 is physically damaged by etching, a predetermined quantum well is not formed, so that the 2DEG is not formed even when a gate voltage is applied. Thus, special care is required. In this embodiment, in order to prevent physical damage to the electron supply layer 4 also in etching the first protective insulating film 8, the damage-less etching is performed using the resist mask 70. The damage-less etching employed here is isotropic etching. Wet etching or isotropic dry etching under specific conditions is employed.

[0214] In the case where wet etching is performed, it is possible to use an etching solution the same as that used in the wet etching of the damage-less etching described in FIG. 11E.

[0215] In the case where dry etching is performed, it is possible to use an etching apparatus and etching conditions the same as those in the dry etching of the damage-less etching described in FIG. 11F.

[0216] The first protective insulating film 8 is subjected to the damage-less etching to form the openings 71a and 71b in the first protective insulating film 8, the openings 71a and 71b each having a shape in which the diameter of an upper portion of each of the openings 71a and 71b is larger than that of the opening 70a in the resist mask 70 and the diameter of a lower portion of each of the openings 71a and 71b is smaller than the diameter of the upper portion. The openings 71a and 69a communicate with the opening 60b to form one opening. The openings 71b and 69b communicate with the opening 60c to form one opening. The bottom of the opening 60b, i.e., the recess (where the source electrode will be formed) of the electron supply layer 4, is exposed at the bottom of the opening 71a. The bottom of the opening 60c, i.e., the recess (where the drain electrode will be formed) of the electron supply layer 4, is exposed at the bottom of the opening 71b. These recesses are not physically damaged because of the damage-less etching. Thus, a predetermined satisfactory 2DEG is formed in the vicinity of the interface between the electron transit layer 3 and the electron supply layer 4.

[0217] Then the resist mask 70 is removed by ashing or the like.

[0218] As illustrated in FIG. 11P, after the formation of a low-work-function film 72, a conductive material 73 is deposited.

[0219] The low-work-function film 72 is formed on the second protective insulating film 16 as an underlying conductive film so as to cover the inner surface of the opening (referred to as an “opening A”) into which the openings 60b, 71a, and 69a are integrally formed and to cover the inner surface of the opening (referred to as an “opening B”) into which the openings 60c, 71b, and 69b are integrally formed. The low-work-function film 72 is formed by depositing one selected from Al, Ti, metal-rich TiN, Ta, metal-rich TaN, Zr, metal-rich TaC, NiSi₂, and Ag in such a manner that the deposited film has a thickness of about 1 nm to about 100 nm. Here, for example, a Ta film is deposited by PVD or the like at a DC power of, for example, 1 kW to 10 kW so as to have a thickness of about 10 nm, thereby forming the low-work-function film 72. The formation of the low-work-function film 72 reduces the barrier between the electrode material and a portion of the electron supply layer 4 directly below the gate electrode, thereby forming the source electrode and the drain electrode with low contact resistance.

[0220] The conductive material 73, such as Al, is deposited on the entire surface of the low-work-function film 72 by PVD or the like at a DC power of, for example, 1 kW to 10 kW in such a manner that the resulting film of the conductive material 73 has a thickness of about 300 nm and that the openings A and B are filled with the conductive material via the low-work-function film 72.

[0221] As illustrated in FIG. 11Q, a resist mask 74 is formed on the conductive material 73.

[0222] A resist is applied on the entire surface of the conductive material 73 and processed by lithography, thereby forming the resist mask 74 that covers portions of the conductive material 73 where the source electrode and the drain electrode will be formed.

[0223] As illustrated in FIG. 11R, a source electrode 75 and a drain electrode 76 are formed.

[0224] The conductive material 73 and the low-work-function film 72 are dry-etched using the resist mask 74, thereby forming the source electrode 75 and the drain electrode 76 in which the openings A and B are filled with the conductive material 73 via the low-work-function film 72 and which protrude from the second protective insulating film 16.

[0225] Then the resist mask 74 is removed by ashing or the like.

[0226] In this embodiment, the source electrode 75 and the drain electrode 76 of the AlGaN/GaN HEMT are formed by lithography and dry etching. In this case, the source electrode 75 and the drain electrode 76 are formed in such a manner that the openings A and B are filled with the conductive material 73. The presence of the first and second protective insulating films 8 and 16 and the damage-less etching of the first protective insulating film 8 prevent physical damage to the electron supply layer 4 when the source and drain electrodes are formed. As described above, in this embodiment, when the source electrode 75 and the drain electrode 76 are formed, the lithography and the damage-less etching are performed using the first protective insulating films 8 and 16, without employing the lift-off process. Unlike the lift-off process, part of the conductive material is not redeposited above the SiC substrate 1, and the satisfactory source electrode 75 and the satisfactory drain electrode 76 are formed without physically damaging the electron supply layer 4.

[0227] The SiC substrate 1 is subjected to heat treatment in, for example, an N₂ atmosphere at about 600° C. for about 60 seconds.

[0228] As illustrated in FIG. 11S, the heat treatment allows Ta in the low-work-function film 72 to react with Al in the conductive material 73, so that the low-work-function film 72 is formed into a TaAl₃ film 72a. The heat treatment results in the formation of minute spikes of the TaAl₃ film 72a at bottoms of the openings A and B, i.e., portions of the electron supply layer 4 directly below the source electrode 75 and the drain electrode 76, thereby reducing the contact resistance between the electron supply layer 4 and the source electrode 75 and between the electron supply layer 4 and the drain electrode 76. Furthermore, Al has a low work function. This also contributes to a reduction in contact resistance.

[0229] As illustrated in FIG. 11T, the interlayer insulator 24 is formed.

[0230] An insulating film, such as a silicon oxide film, having a thickness of about 1000 nm is formed on the entire surface of the second protective insulating film 16 by, for example, plasma-enhanced CVD so as to cover the source electrode 75 and the drain electrode 76, thereby forming the interlayer insulator 24. Here, bumps attributed to projecting portions of the source electrode 75 and the drain electrode 76 are formed on portions of the second protective insulating film 16 above the source electrode 75 and the drain electrode 76. To remove the bumps, surface polishing is preferably performed by, for example, chemical-mechanical polishing (CMP). In this case, the silicon oxide film or the like is deposited so as to have a thickness of about 1000 nm to about 1500 nm, and then a surface portion of the silicon oxide film or the like is polished by CMP so as to reduce the thickness of the silicon oxide film or the like by about 100 nm to about 600 nm, thereby planarizing the surface of the silicon oxide film or the like and forming the interlayer insulator 24. In FIG. 11T, the interlayer insulator 24 having a surface planarized by CMP is illustrated.

[0231] With respect to a method for forming the interlayer insulator, a silicon oxide film or the like may be formed by, for example, spin coating in place of plasma-enhanced CVD and is subjected to curing treatment to form the interlayer insulator.

[0232] As illustrated in FIG. 11U, a connecting portion 77a of the gate electrode 67, a connecting portion 77b of the source electrode 75, and a connecting portion 77c of the drain electrode 76 are formed.

[0233] The second protective insulating film 16 and the interlayer insulator 24 are processed by lithography and dry etching, thereby forming openings 76a, 76b, and 76c that partially expose respective surfaces of the gate electrode 67, the source electrode 75, and the drain electrode 76.

[0234] A conductive material, such as Al, is deposited on the interlayer insulator 24 by, for example, sputtering or plating in such a manner that the openings 76a, 76b, and 76c are filled with the conductive material. The conductive material is polished by CMP using a surface of the interlayer insulator 24 as a polishing stopper. In this way, the openings 76a, 76b, and 76c are filled with the conductive material to form the connecting portion 77a of the gate electrode 67, the connecting portion 77b of the source electrode 75, and the connecting portion 77c of the drain electrode 76.

[0235] Subsequently, steps of forming, for example, an upper interlayer insulator and a line are performed to form the AlGaN/GaN HEMT according to this embodiment.

[0236] According to this embodiment, the gate electrode 67, the source electrode 75, and the drain electrode 76 of the AlGaN/GaN HEMT are formed not by the lift-off process but by a simple method without causing a defect in any pattern, thereby simply and reliably manufacturing the AlGaN/GaN HEMT with excellent device properties.

[0237] Some experiments to check the effects of this modification will be described below.

[0238] Predetermined blanket substrates, for example, structures illustrated in FIG. 12B (structures illustrated in FIG. 1A), were subjected to plasma-induced damage and heat treatment (RTA treatment), thereby forming samples. The heat treatment was performed at about 700° C. or about 800° C. Mercury (Hg) electrodes were appropriately formed on each sample as illustrated in the figure. The 2DEG was evaluated using the samples. FIG. 12A illustrates the results. The evaluation of the 2DEG was performed by C-V measurement using the Hg electrodes. In the case where C-V characteristics are measured when the voltage of the periphery of a surface of each sample is maintained at 0 V, the central electrode has capacitance at 0 V. Furthermore, when a negative voltage is applied, the capacitance of the central electrode is eliminated at a specific voltage. In general, the voltage is referred to as Vp. Vp shifts toward 0 V when the 2DEG is eliminated by physical damage. That is, the results demonstrated that the 2DEG that had been eliminated by the heat treatment at about 700° C. or about 800° C. was recovered. The degree of the recovery of the sample subjected to heat treatment at about 800° C. is higher than that of the sample subjected to heat treatment at about 700° C.

[0239] An element isolation structure (the same as the element isolation structure 7 illustrated in FIG. 11C) having a width of about 2 μm (distance between effective regions) was formed in the structures illustrated in FIG. 1A. The source electrode 75 and the drain electrode 76 illustrated in FIG. 11U were formed in the structure with the element isolation structure provided therebetween, thereby manufacturing a sample. A current was measured when a contact voltage of 10 V was applied using the sample. FIG. 13 illustrates the results. In FIG. 13, the heat treatment (RTA) temperature of the horizontal axis indicates the heat treatment temperature at which the source electrode 75 and the drain electrode 76 are formed. The results indicate that the slight recovery of the interatomic bonds in the electron supply layer 4 by the heat treatment is started. This demonstrates that the heat treatment for damage recovery illustrated in FIG. 11B is preferably performed before the step of forming the element isolation structures 7.

[0240] According to this embodiment, electrical properties of an actually manufactured pattern for the measurement of contact resistance were measured. FIG. 14 illustrates the results. The pattern had a chain of 100 electrodes. The horizontal axis indicates a value obtained by dividing the chain resistance by the number of the electrodes. In FIG. 14, the chain resistance varies depending on the heat treatment temperature at which the source and drain electrodes are formed. A higher temperature at which the source and drain electrodes are formed results in a lower contact resistance. In this embodiment, it was found that suitable low contact resistance was obtained.

[0241] A modification of the third embodiment will be described below. In this modification, although the structure of an AlGaN/GaN HEMT and a method for manufacturing the AlGaN/GaN HEMT are disclosed as in the third embodiment, the structure of the underlying layers of the gate electrode in the modification differs slightly from that in the third embodiment. Note that components equivalent to those in the third embodiment are designated using the same reference numerals.

[0242] In this modification, the steps illustrated in FIG. 1A and FIGS. 11A to 11F are performed as in the third embodiment.

[0243] As illustrated in FIG. 15A, a gate insulator 81, a high-work-function film 82, and a barrier film 83 are formed. In a step the same as that illustrated in FIG. 11H, the conductive material 65 is deposited so as to come into contact with the barrier film 83.

[0244] The gate insulator 81, the high-work-function film 82, and the barrier film 83 are formed on the first protective insulating film 8 so as to cover inner surfaces of the openings 8a and 60a.

[0245] The gate insulator 81 is formed of an oxide or oxynitride film of one selected from Si, Al, Ti, Ta, Hf, La, Y, and Ni. Alternatively, the gate insulator 81 has a laminated structure of two or more selected from these films. Here, for example, an AlO film is deposited so as to have a thickness of, for example, about 1 nm to about 50 nm, thereby forming the gate insulator 81.

[0246] The high-work-function film 82 is formed by depositing one selected from Au, Ni, Co, nitrogen-rich TiN, nitrogen-rich TaN, carbon-rich TaC, Pt, W, Ru, Ni₃Si, and Pd in such a manner that the deposited film has a thickness of about 1 nm to about 100 nm. Here, for example, nitrogen-rich TiN is deposited so as to have a thickness of about 20 nm, thereby forming the high-work-function film 82.

[0247] The barrier film 83 is formed by depositing, for example, a TaN film using PVD, ALD, or the like in such a manner that the TaN film has a thickness of, for example, about 0.1 nm to about 50 nm.

[0248] The barrier film 83 is provided between the high-work-function film 82 and the conductive material 65. The presence of the barrier film 83 prevents Al in the conductive material 65 from reaching a portion of the electron supply layer 4 directly below the gate electrode through the gate insulator 81 when the SiC substrate 1 is subjected to heat treatment at 550° C. to 650° C. in the subsequent step. A higher proportion of nitrogen in the barrier film 83 results in higher barrier properties of the barrier film 83. In the case where nitrogen-rich TaN is formed as the barrier film 83, the resulting nitrogen-rich TaN film preferably has a thickness of 0.1 nm to 10 nm.

[0249] Alternatively, without forming the barrier film 83, the high-work-function film 82 may be formed of a nitrogen-rich TaN film in the same way as the barrier film 83 (that is, the high-work-function film 82 is formed so as to also serve as a barrier film), and then the conductive material 65 may be deposited so as to come into contact with the high-work-function film 82.

[0250] Steps the same as those illustrated in FIGS. 11I to 11R according to the first embodiment are performed.

[0251] In the step illustrated in FIG. 11J, the conductive material 65, the barrier film 83, the high-work-function film 82, and the gate insulator 81 are dry-etched using the resist mask 66 to form the gate electrode 67.

[0252] As illustrated in FIG. 15B, the SiC substrate 1 is subjected to heat treatment. This heat treatment is performed for 0 to 180 seconds at 550° C. to 650° C. in an atmosphere selected from the group consisting of noble gases, nitrogen, oxygen, ammonia, hydrogen gas, and mixtures thereof. Here, for example, the heat treatment is performed in an N₂ atmosphere at about 600° C. for about 60 seconds. As described in the first embodiment, the low-work-function film 72 is formed into the TaAl₃ film 72a by the heat treatment to form spikes, thereby reducing the contact resistance between the electron supply layer 4 and the source electrode 75 and between the electron supply layer 4 and the drain electrode 76.

[0253] In this modification, the barrier film 83 is provided between the gate electrode 67 and the high-work-function film 82. The presence of the barrier film 83 prevents the diffusion of Al in the gate electrode 67 to the high-work-function film 82 during the heat treatment. Thus, spikes of Al of the gate electrode 67 are not formed for the gate insulator 81, so that the occurrence of gate leakage is suppressed. Furthermore, the presence of the barrier film 83 results in a predetermined shallow quantum well without diffusing Al having a low work function into a portion directly above the gate insulator 81.

[0254] Steps the same as those illustrated in FIGS. 11T and 11U according to the first embodiment are sequentially performed to form the connecting portions 77a, 77b, and 77c of the gate electrode 67, the source electrode 75, and the drain electrode 76.

[0255] Subsequently, steps of forming, for example, an upper interlayer insulator and a line are performed to form the AlGaN/GaN HEMT according to this modification.

[0256] According to this modification, the gate electrode 67, the source electrode 75, and the drain electrode 76 of the AlGaN/GaN HEMT are formed not by the lift-off process but by a simple method without causing a defect in any pattern, thereby simply and reliably manufacturing the AlGaN/GaN HEMT having excellent device properties, in which the occurrence of gate leakage is prevented.

[0257] In this embodiment, with respect to an AlGaN/GaN HEMT, the case where a source electrode and a drain electrode are formed before the formation of a gate electrode. Note that components equivalent to those in the third embodiment are designated using the same reference numerals.

[0258] In this embodiment, the steps illustrated in FIG. 1A and FIGS. 11A to 11D are performed as in the third embodiment.

[0259] As illustrated in FIG. 16A, a resist mask 91 is formed on the first protective insulating film 8.

[0260] A resist is applied on the entire surface of the first protective insulating film 8 and processed by lithography, thereby forming the resist mask 91 having a pair of openings 91a and 91b that exposes portions of the first protective insulating film 8 where the source electrode and the drain electrode will be formed.

[0261] As illustrated in FIG. 16B, a pair of openings 8b and 8c is formed by damage-less etching in a portion of the first protective insulating film 8 where the source electrode and the drain electrode will be formed.

[0262] The damage-less etching is what is called isotropic etching. Wet etching or isotropic dry etching under specific conditions is employed.

[0263] In the case where wet etching is performed, it is possible to use an etching solution the same as that used in the wet etching of the damage-less etching described in FIG. 11F according to the third embodiment.

[0264] In the case where dry etching is performed, it is possible to use an etching apparatus and etching conditions the same as those in the dry etching of the damage-less etching described in FIG. 11F according to the third embodiment.

[0265] The first protective insulating film 8 is subjected to the damage-less etching to form the openings 8b and 8c in the first protective insulating film 8, the openings 8b and 8c each having a shape in which the diameter of an upper portion of each of the openings 8b and 8c is larger than that of a corresponding one of the openings 91a and 91b in the resist mask 91 and the diameter of a lower portion of each of the openings 8b and 8c is smaller than that of the corresponding upper portion. Each of the openings 8b and 8c communicates with a corresponding one of openings 60b and 60c to form one opening. The bottom of the opening 60b, i.e., the recess (where the source electrode will be formed) of the electron supply layer 4, is exposed at the bottom of the opening 8b. The bottom of the opening 60c, i.e., the recess (where the drain electrode will be formed) of the electron supply layer 4, is exposed at the bottom of the opening 8c. These recesses are not physically damaged because of the damage-less etching. Thus, a predetermined satisfactory 2DEG is formed in the vicinity of the interface between the electron transit layer 3 and the electron supply layer 4.

[0266] Then the resist mask 91 is removed by ashing or the like.

[0267] As illustrated in FIG. 16C, after the formation of a low-work-function film 92, a conductive material 93 is deposited.

[0268] The low-work-function film 92 is formed on the second protective insulating film 16 as an underlying conductive film so as to cover inner surfaces of the openings 8b and 60b and the inner surface of an opening into which the openings 8c and 60c are integrally formed. The low-work-function film 92 is formed by depositing one selected from Al, Ti, metal-rich TiN, Ta, metal-rich TaN, Zr, metal-rich TaC, NiSi₂, and Ag in such a manner that the deposited film has a thickness of about 1 nm to about 100 nm. Here, for example, a Ta film is deposited by PVD or the like at a DC power of, for example, 1 kW to 10 kW so as to have a thickness of about 10 nm, thereby forming the low-work-function film 92. The formation of the low-work-function film 92 reduces the barrier between the electrode material and a portion of the electron supply layer 4 directly below the gate electrode, thereby forming the source electrode and the drain electrode with low contact resistance.

[0269] The conductive material 93, such as Al, is deposited on the entire surface of the low-work-function film 92 by PVD or the like at a DC power of, for example, 1 kW to 10 kW in such a manner that the resulting film of the conductive material 93 has a thickness of about 300 nm and that the openings 8b and 60b and the openings 8c and 60c are filled with the conductive material via the low-work-function film 92.

[0270] As illustrated in FIG. 16D, a resist mask 94 is formed on the conductive material 93.

[0271] A resist is applied on the entire surface of the conductive material 93 and processed by lithography, thereby forming the resist mask 94 that covers portions of the conductive material 93 where the source electrode and the drain electrode will be formed.

[0272] As illustrated in FIG. 16E, a source electrode 95 and a drain electrode 96 are formed.

[0273] The conductive material 93 and the low-work-function film 92 are dry-etched using the resist mask 94, thereby forming the source electrode 95 and the drain electrode 96 in which the openings 8b and 60b and the openings 8c and 60c are filled with the conductive material 93 via the low-work-function film 92 and which protrude from the second protective insulating film 16.

[0274] Then the resist mask 94 is removed by ashing or the like.

[0275] In this embodiment, the source electrode 95 and the drain electrode 96 of the AlGaN/GaN HEMT are formed by lithography and dry etching. In this case, the source electrode 95 and the drain electrode 96 are formed in such a manner that the openings 8b and 60b and the openings 8c and 60c are filled with the conductive material 93. The presence of the first protective insulating film 8 and the damage-less etching prevent physical damage to the electron supply layer 4 when the source and drain electrodes are formed. As described above, in this embodiment, when the source electrode 95 and the drain electrode 96 are formed, the lithography and the damage-less etching are performed using the first protective insulating film 8, without employing the lift-off process. Unlike the lift-off process, part of the conductive material is not redeposited above the SiC substrate 1, and the satisfactory source electrode 95 and the satisfactory drain electrode 96 are formed without physically damaging the electron supply layer 4.

[0276] The SiC substrate 1 is subjected to heat treatment in, for example, an N₂ atmosphere at about 600° C. for about 60 seconds.

[0277] As illustrated in FIG. 16F, the heat treatment allows Ta in the low-work-function film 92 to react with Al in the conductive material 93, so that the low-work-function film 92 is formed into a TaAl₃ film 92a. The heat treatment results in the formation of minute spikes of the TaAl₃ film 92a at bottoms of the openings 8b and 60b and the openings 8c and 60c, i.e., portions of the electron supply layer 4 directly below the source electrode 95 and the drain electrode 96, thereby reducing the contact resistance between the electron supply layer 4 and the source electrode 95 and between the electron supply layer 4 and the drain electrode 96. Furthermore, Al has a low work function. This also contributes to a reduction in contact resistance.

[0278] As illustrated in FIG. 16G, the second protective insulating film 16 is formed.

[0279] An insulating film, such as a silicon oxide film, having a thickness of about 300 nm is formed on the entire surface of the first protective insulating film 8 by, for example, plasma-enhanced CVD so as to cover the source electrode 95 and the drain electrode 96, thereby forming the second protective insulating film 16. Here, bumps attributed to projecting portions of the source electrode 95 and the drain electrode 96 are formed on portions of the second protective insulating film 16 above the source electrode 95 and the drain electrode 96. To remove the bumps, surface polishing is preferably performed by, for example, CMP. In this case, the silicon oxide film or the like is deposited so as to have a thickness of about 500 nm to about 1000 nm, and then a surface portion of the silicon oxide film or the like is polished by CMP so as to reduce the thickness of the silicon oxide film or the like by about 100 nm to about 600 nm, thereby planarizing the surface of the silicon oxide film or the like and forming the second protective insulating film 16. In FIG. 16G, the second protective insulating film 16 having a surface planarized by CMP is illustrated.

[0280] With respect to a method for forming the second protective insulating film, a silicon oxide film or the like may be formed by, for example, spin coating in place of plasma-enhanced CVD and is subjected to curing treatment to form the second protective insulating film.

[0281] As illustrated in FIG. 16H, a resist mask 110 is formed on the second protective insulating film 16.

[0282] A resist is applied on the entire surface of the second protective insulating film 16 and processed by lithography, thereby forming the resist mask 110 having an opening 110a that exposes a portion of the second protective insulating film 16 where the gate electrode will be formed.

[0283] In steps illustrated in FIGS. 16I and 16J, two-stage etching is performed.

[0284] As illustrated in FIG. 16I, an opening 90 is formed so as to extend from a surface of the second protective insulating film 16 to the middle portion of the first protective insulating film 8. Here, the case where the opening 90 is formed so as to extend to the surface of the first protective insulating film 8.

[0285] The opening 90 is formed by dry etching from the surface of the second protective insulating film 16 to the middle portion of the first protective insulating film 8 using the resist mask 110. The dry etching is performed at a pressure of about 1.7 Torr and an RF power of, for example, about 650 W using a fluorine-containing gas, such as a mixed gas of CHF₃, CF₃, and Ar, as an etching gas in such a manner that etching is stopped at the surface of the first protective insulating film 8. This dry etching results in the formation of the opening 90 extending to the surface of the first protective insulating film 8 through the second protective insulating film 16, the first protective insulating film 8 being left at the bottom of the opening 90.

[0286] Then the resist mask 110 is removed by ashing or the like.

[0287] The dry etching illustrated in FIG. 16I is performed so as to expose the surface of the first protective insulating film 8. Thus, the first protective insulating film 8 is left at the bottom of the opening 90. So, the dry etching does not physically damage the electron supply layer 4.

[0288] As illustrated in FIG. 16J, a resist mask 97 is formed.

[0289] A resist is applied on the entire surface of the second protective insulating film 16 in such a manner that the opening 90 is filled with the resist. The resist is processed by lithography, thereby forming the resist mask 97 having an opening 97a that is located in the opening 90, the resist mask 97 covering the second protective insulating film 16 and the inner side wall of the opening 90, and the diameter (width) of the opening 97a being a smaller than that of the opening 90.

[0290] As illustrated in FIG. 16K, an opening 98 is formed in the first protective insulating film 8 by damage-less etching.

[0291] The damage-less etching employed here is what is called isotropic etching. Wet etching or isotropic dry etching under specific conditions is employed.

[0292] In the case where wet etching is performed, it is possible to use an etching solution the same as that used in the wet etching of the damage-less etching described in FIG. 11F according to the third embodiment.

[0293] In the case where dry etching is performed, it is possible to use an etching apparatus and etching conditions the same as those in the dry etching of the damage-less etching described in FIG. 11F according to the third embodiment.

[0294] The first protective insulating film 8 is subjected to the damage-less etching to form the opening 98 in the first protective insulating film 8, the opening 98 having a shape in which the diameter of an upper portion of the opening 98 is larger than that of the opening 97a in the resist mask 97 and the diameter of a lower portion of the opening 98 is smaller than that of the upper portion. The opening 98 and opening 90 communicate with the opening 60a to form one opening. The bottom of the opening 60a, i.e., the recess (where the gate electrode will be formed) of the electron supply layer 4, is exposed at the bottom of the opening 98. The recess is not physically damaged because of the damage-less etching. Thus, a predetermined satisfactory 2DEG is formed in the vicinity of the interface between the electron transit layer 3 and the electron supply layer 4.

[0295] Then the resist mask 97 is removed by ashing or the like.

[0296] As illustrated in FIG. 16L, a gate insulator 99 and a high-work-function film 101 are formed.

[0297] The gate insulator 99 and the high-work-function film 101 are formed on the second protective insulating film 16 so as to cover the inner surface of the opening (referred to as an “opening C”) into which the openings 60a, 90, and 98 are integrally formed.

[0298] The gate insulator 99 is formed by depositing, for example, an AlO film having a thickness of, for example, about 20 nm by ALD or the like. The gate insulator 99 may be formed of a TaO film, or a high-dielectric (high-k) oxide or oxynitride film of Hf, Ti, or Zr, in place of the AlO film. Alternatively, the gate insulator 99 may have a laminated structure of two or more selected from the AlO film, the TaO film, and the high-k film.

[0299] After the formation of the gate insulator 99, heat treatment may be performed at, for example, about 550° C. for about 60 seconds.

[0300] The high-work-function film 101 is formed by depositing, for example, a TaN film having a thickness of, for example, about 40 nm by physical vapor deposition (PVD) or the like. The term “high-work-function film” indicates a film composed of a conductive material having a work function of 4.5 eV or more. The formation of the high-work-function film 101 provides a shallow quantum well directly below the gate electrode, thereby reducing the 2DEG directly below the gate electrode when the gate voltage is 0 V.

[0301] As illustrated in FIG. 16L, a conductive material 102 is formed on the high-work-function film 101.

[0302] The conductive material 102, such as Al, is deposited on the entire surface of the high-work-function film 101 by PVD or the like in such a manner that the resulting film of the conductive material 102 has a thickness of about 20 nm to about 500 nm, for example, about 400 nm and that the opening C is filled with the conductive material 102 via the gate insulator 99 and the high-work-function film 101.

[0303] As illustrated in FIG. 16M, a resist mask 100 is formed on the conductive material 102.

[0304] A resist is applied on the entire surface of the conductive material 102 and processed by lithography, thereby forming the resist mask 100 that covers a portion of the conductive material 102 where the gate electrode will be formed.

[0305] As illustrated in FIG. 16N, a gate electrode 103 is formed.

[0306] The conductive material 102, the high-work-function film 101, and the gate insulator 99 are dry-etched using the resist mask 100. Here, in order to reliably form the gate electrode, as illustrated in the figure, etching may be performed so as to expose a surface of the second protective insulating film 16. The dry etching results in the formation of the gate electrode 103 in which the opening C is filled with the conductive material 102 via the gate insulator 99 and the high-work-function film 101 and which protrudes from the second protective insulating film 16.

[0307] Then the resist mask 100 is removed by ashing or the like.

[0308] In this embodiment, the gate electrode 103 of the AlGaN/GaN HEMT is formed by lithography and dry etching. In this case, the first and second protective insulating films 8 and 16 are formed, and then the gate electrode 102 is formed in such a manner that the opening C is filled with the conductive material 102. The presence of the first and second protective insulating films 8 and 16 and the damage-less etching of the first protective insulating film 8 prevent physical damage to the electron supply layer 4 when the gate electrode is formed. As described above, in this embodiment, when the gate electrode 103 is formed, the lithography and the damage-less etching are performed using the first and second protective insulating films 8 and 16, without employing the lift-off process. Unlike the lift-off process, part of the conductive material is not redeposited above the SiC substrate 1, and the satisfactory gate electrode 103 is formed without physically damaging the compound semiconductor layers.

[0309] In this embodiment, the source electrode 95 and the drain electrode 96 are formed before the formation of the gate electrode 103. Thus, heat treatment to reduce the contact resistance of the source electrode 95 and the drain electrode 96 can be performed in a state in which the gate electrode is not formed. So, the barrier layer against Al as described in the modification of the first embodiment may not be formed, thereby leading to a simple manufacturing process.

[0310] As illustrated in FIG. 16O, the interlayer insulator 24 is formed.

[0311] An insulating film, such as a silicon oxide film, having a thickness of about 1000 nm is formed on the entire surface of the second protective insulating film 16 by, for example, plasma-enhanced CVD so as to cover the gate electrode 103, thereby forming the interlayer insulator 24. Here, a bump attributed to a projecting portion of the gate electrode 103 is formed on a portion of the interlayer insulator 24 above the gate electrode 103. To remove the bump, surface polishing is preferably performed by, for example, chemical-mechanical polishing (CMP). In this case, the silicon oxide film or the like is deposited so as to have a thickness of about 1000 nm to about 1500 nm, and then a surface portion of the silicon oxide film or the like is polished by CMP so as to reduce the thickness of the silicon oxide film or the like by about 100 nm to about 600 nm, thereby planarizing the surface of the silicon oxide film or the like and forming the interlayer insulator 24. In FIG. 16O, the interlayer insulator 24 having a surface planarized by CMP is illustrated.

[0312] With respect to a method for forming the interlayer insulator, a silicon oxide film or the like may be formed by, for example, spin coating in place of plasma-enhanced CVD and is subjected to curing treatment to form the interlayer insulator.

[0313] As illustrated in FIG. 16P, a connecting portion 105a of the gate electrode 103, a connecting portion 105b of the source electrode 95, and a connecting portion 105c of the drain electrode 96 are formed.

[0314] The second protective insulating film 16 and the interlayer insulator 24 are processed by lithography and dry etching, thereby forming openings 104a, 104b, and 104c that partially expose respective surfaces of the gate electrode 103, the source electrode 95, and the drain electrode 96.

[0315] A conductive material, such as Al, is deposited on the interlayer insulator 24 by, for example, sputtering or plating in such a manner that the openings 104a, 104b, and 104c are filled with the conductive material. The conductive material is polished by CMP using a surface of the interlayer insulator 24 as a polishing stopper. In this way, the openings 104a, 104b, and 104c are filled with the conductive material to form the connecting portion 105a of the gate electrode 103, the connecting portion 105b of the source electrode 95, and the connecting portion 105c of the drain electrode 96.

[0316] Subsequently, steps of forming, for example, an upper interlayer insulator and a line are performed to form the AlGaN/GaN HEMT according to this embodiment.

[0317] According to this embodiment, the gate electrode 103, the source electrode 95, and the drain electrode 96 of the AlGaN/GaN HEMT are formed not by the lift-off process but by a simple method without causing a defect in any pattern, thereby simply and reliably manufacturing the AlGaN/GaN HEMT having excellent device properties, in which the occurrence of gate leakage is prevented.

[0318] In each of the first to fourth embodiments and the modifications, the AlGaN/GaN HEMT, which is a nitride semiconductor device, is exemplified as a compound semiconductor device. However, the compound semiconductor device is not limited to the AlGaN/GaN HEMT. Examples of an applicable compound semiconductor device other than a compound semiconductor device including AlGaN and GaN are described below.

[0319] (1) Compound Semiconductor Device Including InAlN and AlN, InAlN and AlN are compound semiconductor materials. The lattice constant of AlN is smaller than that of InAlN. In this case, InAlN is used for an electron transit layer. AlN is used for an electron supply layer. Furthermore, for example, n⁺-InAlN having a high n-type impurity concentration is used for a cap layer.

[0320] (2) Compound Semiconductor Device Including InAlGaN and AlN, InAlGaN and AlN compound semiconductor materials. The lattice constant of AlN is smaller than that of InAlGaN. In this case, InAlGaN is used for an electron transit layer. AlN is used for an electron supply layer. Furthermore, for example, n⁺-InAlGaN having a high n-type impurity concentration is used for a cap layer.

[0321] (3) Compound Semiconductor Device Including InAlN and InAlGaN.

[0322] In the case of InAlN and InAlGaN, the lattice constants of InAlN and InAlGaN are changed by adjusting the proportions of In, Al, and Ga therein. It is possible to make the lattice constant of InAlN smaller or larger than that of InAlGaN by adjusting the proportions of In, Al, and Ga. Here, the case where the lattice constant of InAlGaN is smaller than that of InAlN is exemplified.

[0323] In this case, InAlN is used for an electron transit layer. InAlGaN is used for an electron supply layer. Furthermore, for example, n⁺-InAlN having a high n-type impurity concentration is used for a cap layer.

[0324] (4) Compound Semiconductor Device Including AlGaN materials having different Al contents.

[0325] Even for compound semiconductor materials having similar compositions, different composition ratios result in different lattice constants. With respect to one type of compound semiconductor material that exhibits different lattice constants, for example, in the case of AlGaN, Al_0.3Ga_0.7N and Al_0.5Ga_0.5N may be used. For AlGaN, a higher Al content results in a smaller lattice constant. Thus, the lattice constant of the Al_0.5Ga_0.5N is smaller than that of Al_0.3Ga_0.7N.

[0326] In this case, Al_0.3Ga_0.7N is used for an electron transit layer. Al_0.5Ga_0.5N is used for an electron supply layer. Furthermore, for example, n⁺-Al_0.3Ga_0.7N having a high n-type impurity concentration is used for a cap layer.

[0327] All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the invention and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions. Although the embodiments in accordance with aspects of the present invention have been described in detail, it should be understood that various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.