Hybrid drive balancing execution times for non-volatile semiconductor memory and disk

[0001] The present application claims priority from co-pending provisional U.S. Patent Application Ser. No. 61/378,842, filed on Aug. 31, 2010, the specification of which is incorporated herein by reference.

[0002] Hybrid drives are conventional disk drives augmented with a non-volatile semiconductor memory (NVSM) such as a flash which helps improve certain aspects of the disk drive. For example, the non-volatile semiconductor memory may store boot data in order to expedite the boot operation of a host computer. Another use of a NVSM may be to store frequently accessed data and/or non-sequential data for which the access time is typically much shorter than the disk (which suffers from mechanical latency including seek and rotational latency). Other policies may reduce write amplification of the NVSM in order to maximize its longevity, such as storing frequently written data to the disk (or data having a write/read ratio that exceeds a predetermined threshold).

[0022] FIG. 1A shows a hybrid drive according to an embodiment of the present invention comprising a head 2 actuated over a disk 4, and a non-volatile semiconductor memory (NVSM) 6. The hybrid drive further comprises control circuitry 8 operable to execute the flow diagram of FIG. 1B wherein a first execution time needed to execute commands in a NVSM command queue 10 is estimated, and a second execution time needed to execute commands in a disk command queue 12 is estimated (step 14). When an access command is received or internally generated (step 16), it is inserted into (or transferred to) a selected one of the NVSM command queue and the disk command queue in response to the first and second execution times (step 18), and one of the first and second execution times is updated in response to an estimated execution time of the access command (step 20).

[0023] In the embodiment of FIG. 1A, any suitable NVSM 6 may be employed, such as any suitable electrically erasable/programmable memory (e.g., a flash memory). In one embodiment, the NVSM 6 comprises a plurality of blocks, where each block comprises a plurality of memory segments referred to as pages. The blocks are programmed a page at a time, and an entire block is erased in a unitary operation. In embodiments described in more detail below, a garbage collection operation may be executed on previously written blocks in order to copy valid pages to new blocks (or to the disk) so that the previously written blocks may be erased and re-used.

[0024] The disk 4 shown in the embodiment of FIG. 1A comprises a plurality of data tracks 22 defined by servo sectors 24₀-24_N, wherein each data track comprises a plurality of data sectors accessed indirectly through a logical block address (LBA). The control circuitry 8 processes a read signal 26 emanating from the head 2 to demodulate the servo sectors 24₀-24_N into a position error signal (PES) representing a position error of the head relative to a target data track. The control circuitry 8 comprises a servo compensator for filtering the PES to generate a control signal 28 applied to a voice coil motor (VCM) 30 that rotates an actuator arm 32 about a pivot in order to actuate the head 2 radially over the disk 4 in a direction that reduces the PES.

[0025] FIG. 2A shows a disk command queue comprising a plurality of access commands and a corresponding execution time, and a NVSM command queue comprising a plurality of access commands and a corresponding execution time. In one embodiment, the execution time for the disk command queue is based on the data rate of the disk, the amount of data in each access command, and the mechanical latency in seeking the head to a target track and waiting for the disk to rotate to a target data sector. A rotational position optimization (RPO) algorithm may be employed to sort the commands in the disk command queue in an order that minimizes the mechanical latency, and in one embodiment the RPO algorithm may also be used to estimate the execution time for all of the access commands stored in the disk command queue. When an access command is inserted into the disk command queue, the RPO algorithm may reorder the access commands and then update the estimated execution time. In one embodiment, the execution time for the NVSM command queue is based on the data rate of the semiconductor memory and the amount of data in each access command. In one embodiment, the write data rate of the NVSM may differ from the read data rate, and therefore the execution time for the NVSM command queue may also be based on the types of access commands.

[0026] In yet another embodiment, the execution time of the NVSM may be based on the frequency of access to each individual memory device within the NVSM. For example, if a number of access commands in the NVSM command queue are targeted to a single memory device within the NVSM, it will reduce the throughput of the NVSM and therefore increase the execution time of the NVSM command queue.

[0027] In the example of FIG. 2A, the execution time for the disk command queue is longer than the execution time for the NVSM command queue. Therefore in an embodiment shown in FIG. 2B, when an access command is received or internally generated it is inserted into the NVSM command queue in order to closer balance the execution times. FIG. 2C is a flow diagram according to an embodiment of the present invention wherein when an access command is selected for execution from one of the command queues (step 34), the selected access command is executed (step 36) and the execution time for the corresponding command queue is updated (step 38). In one embodiment, the execution time is updated by subtracting the estimated execution time for the access command that was executed.

[0028] FIG. 3 is a flow diagram according to an embodiment of the present invention wherein when an access command is received or internally generated (step 16) an estimated execution time for the access command is computed for the NVSM command queue and for the disk command queue (step 40). The access command is then inserted into one of the command queues based on the execution times of the command queues and the estimated execution time for the access command (step 42). In one embodiment, an updated execution time for each command queue is estimated based on the addition of the access command to each command queue. The updated execution times are then compared in order to determine which command queue to insert the access command (e.g., insert the access command into the command queue that results in the best balance of execution times).

[0029] FIG. 4A is a flow diagram according to an embodiment of the present invention wherein when an access command is selected for execution from one of the command queues (step 44), the selected access command is executed (step 46). If the actual execution time for the access command is substantially longer than an estimated execution time (step 48), an access command is transferred to the other command queue (step 50) in order to balance the execution times for the command queues. This embodiment is illustrated in FIG. 4B wherein an access command selected from the disk command queue has an estimated execution time that corresponds to the execution time for two commands in the NVSM command queue. If the actual execution time of the access commands substantially matches the estimated execution time (no access errors), then the execution times remain substantially balanced as illustrated in FIG. 4C. FIG. 4D illustrates an example where an error in accessing the disk causes the actual execution time for a selected access command to be substantially longer (e.g., due to retry operations). As a result, more access commands are executed from the NVSM command queue resulting in an imbalance in the execution times. Accordingly, in one embodiment one or more commands are transferred from the disk command queue to the NVSM command queue as illustrated in FIG. 4E. The access commands that are transferred may be selected using any suitable algorithm, including one of embodiments disclosed below with reference to FIGS. 6A-6C.

[0030] An error may also occur when accessing the NVSM (during write or read operations) which may significantly extend the actual execution time of an access command. For example, a write/read error to a page in a target block may require the entire block be relocated to a new block which may take a significant amount of time. Accordingly, in one embodiment when an actual execution time of an NVSM access command is substantially longer than an estimated execution time, one or more access commands are transferred from the NVSM command queue to the disk command queue in order to balance the execution times.

[0031] FIG. 5A is a flow diagram according to an embodiment of the present invention wherein when the access command is a write command (step 52), the write command is inserted into one of the disk and NVSM command queue based on a migration policy (step 54). Any suitable migration policy may be employed, such as inserting write commands identifying sequentially accessed logical block addresses (LBAs) into the disk command queue and non-sequentially accessed LBAs into the NVSM command queue. Another migration policy may include inserting write commands identifying frequently written LBAs into the disk command queue in order to reduce write amplification of the NVSM. After inserting the write command into the respective command queue based on the migration policy, the updated execution times are evaluated to determine whether either execution time exceeds a threshold (step 56). If one of the execution times exceeds a threshold, indicating that there is a high workload of access commands, the difference between the execution times is evaluated. If the difference between the execution times exceeds a threshold (step 58), indicating the execution times require rebalancing, one or more eligible access commands are transferred between the disk and NVSM command queues, thereby overriding the migration policy in order to balance the execution times (step 60). In this embodiment, the performance benefit of balancing the execution times to better utilize the bandwidth of both channels outweighs the benefit of the migration policy. In one embodiment, a hysteresis may be employed at the threshold comparison of step 56 to prevent thrashing.

[0032] In one embodiment, one or more of the access commands may be ineligible for transfer because they identify LBAs that are pinned to one of the disk or the NVSM. For example, LBAs that identify certain operating system data may be pinned to the NVSM to ensure the performance benefit of accessing the system data from the NVSM is maintained. The access commands that are eligible for transfer may be selected using any suitable algorithm, including one of embodiments disclosed below with reference to FIGS. 6A-6C.

[0033] FIG. 5B is a flow diagram according to an embodiment of the present invention wherein when the access command is a read command (step 62), the read command is evaluated to determine whether the data is stored on both the disk and the NVSM (step 64). If the data is stored on both the disk and NVSM, the read command is inserted into one of the disk and NVSM command queue based on the execution times of the command queues (step 66) to balance the execution times. If the data is stored on only one of the disk and NVSM, the read command is inserted into the respective command queue (step 68), and then one or more of the pending access commands is transferred between the command queues in order to balance the execution times (step 70).

[0034] Any suitable algorithm may be employed to select access commands to transfer between the command queues in order to balance the execution times. FIG. 6A is a flow diagram according to an embodiment of the present invention wherein when a transfer of an access command is needed to balance the execution times (step 72), the access commands to transfer are selected based on a migration policy, such as transferring read commands from the disk command queue to the NVSM command queue to reduce write amplification of the NVSM (step 74). In another embodiment, write commands that are more appropriately suited for storing in the NVSM are selected for transfer to the NVSM command queue, such as write commands that are near non-sequential or write commands that identify LBAs having a lower write frequency than the LBAs of other write commands.

[0035] FIG. 6B is a flow diagram according to an embodiment of the present invention wherein when a transfer of an access command is needed to balance the execution times (step 76), the access commands to transfer are selected based on the resulting impact on the execution time of the command queues (step 78). For example, in one embodiment an access command may be transferred from the NVSM command queue to the disk command queue that results in the shortest execution time for the disk command queue (most optimal for the RPO algorithm). In another example, multiple short access commands may be transferred from the disk command queue to the NVSM command queue rather than one longer access command in order to maximally reduce the execution time of the disk command queue (by reducing the total number of access commands for the RPO algorithm).

[0036] FIG. 6C is a flow diagram according to an embodiment of the present invention wherein when a transfer of an access command is needed to balance the execution times (step 80), the access commands to transfer are selected based on an execution time limit of the access commands (step 82). In this embodiment, each access command may be assigned an execution time limit within which the access command must be executed. If for example an access command in the disk command queue is reaching its execution time limit, it may be selected for transfer to the NVSM command queue in order to expedite its execution, as well as avoid disrupting the order of execution of disk access commands determined by the RPO algorithm.

[0037] FIG. 7 is a flow diagram according to an embodiment of the present invention wherein it may be necessary to re-order one of the command queues (step 84), such as when a command is inserted into the command queue, or when a pending access command is selected for out-of-order execution. After re-ordering the command queue (step 86), the execution time for the reordered command queue is updated (step 88) and the updated execution time evaluated to determine whether a rebalancing of execution times is needed.

[0038] Access commands may be received from a host, and in one embodiment, a large host access command may be split into two access commands in order to balance the execution times of the command queues. In one embodiment, a large host access command may be divided in half and the two resulting access commands inserted into the NVSM command queue or the disk command queue in order to balance the execution times. In another embodiment, a large host access command may be divided by a fraction that is based on the execution times of the command queues. For example, to balance the execution times two-thirds of a host access command may be inserted into the NVSM command queue and the remaining third inserted into the disk command queue (or vice versa depending on the execution times of the command queues).

[0039] In another embodiment, access commands may be generated internally by the hybrid drive. For example, in one embodiment the NVSM may require periodic garbage collection wherein the valid pages of previously written blocks are copied to new blocks so that the old blocks may be erased and reused. Accordingly, the garbage collection operation may generate internal read commands to read valid data corresponding to valid pages of an old block, and internal write commands to write the valid data to a new block or to the disk. FIG. 8A illustrates an example wherein the NVSM command queue comprises a number of host write and read commands (H_W and H_R), as well as two garbage collection read commands (GC_R).

[0040] In an embodiment illustrated in FIG. 8B, a copy of valid data in a block of the NVSM may be stored on the disk, and therefore a garbage collection read command (GC_R) stored in the NVSM command queue may be transferred to the disk command queue in order to balance the execution times of the command queues. The valid data is read from the disk and written to a new block in the NVSM so that the old block may be erased and reused while retaining a copy of the data in both the NVSM and on the disk. In another embodiment, a garbage collection read command may be inserted into the disk command queue when generated (rather than transferred from the NVSM command queue).

[0041] In an embodiment illustrated in FIG. 8C, a garbage collection write command (GC_W) generated for a valid page in the NVSM may be inserted into the disk command queue rather than the NVSM command queue in order to balance the execution times of the command queues. In this embodiment, the valid data is read from a block of the NVSM, and when the garbage collection write command is executed, the valid data is effectively migrated to the disk rather then being written to a new block in the NVSM. In an alternative embodiment, a garbage collection write command may be transferred from the NVSM command queue to the disk command queue in order to balance the execution times of the command queues.

[0042] Any suitable control circuitry may be employed to implement the flow diagrams in the embodiments of the present invention, such as any suitable integrated circuit or circuits. For example, the control circuitry may be implemented within a read channel integrated circuit, or in a component separate from the read channel, such as a disk controller and/or NVSM controller, or certain steps described above may be performed by a read channel and others by a disk controller and/or NVSM controller. In one embodiment, the read channel and controllers are implemented as separate integrated circuits, and in an alternative embodiment they are fabricated into a single integrated circuit or system on a chip (SOC). In addition, the control circuitry may include a suitable preamp circuit implemented as a separate integrated circuit, integrated into the read channel or disk controller circuit, or integrated into an SOC.

[0043] In one embodiment, the control circuitry comprises a microprocessor executing instructions, the instructions being operable to cause the microprocessor to perform the steps of the flow diagrams described herein. The instructions may be stored in any computer-readable medium. In one embodiment, they may be stored on a non-volatile semiconductor memory external to the microprocessor, or integrated with the microprocessor in a SOC. In another embodiment, the instructions are stored on the disk and read into a volatile semiconductor memory when the hybrid drive is powered on. In yet another embodiment, the control circuitry comprises suitable logic circuitry, such as state machine circuitry.