Bidirectional dual-SCR circuit for ESD protection

[0001] In integrated circuits, electrostatic discharge (ESD) stress events may arise when a charged object, such as a human body or another machine, is placed in proximity to an integrated circuit device and a static discharge occurs. The conductive leads on a packaged integrated circuit (IC) constitute an efficient surface for receiving electrostatic discharge. If the voltage stress that is caused by the discharge into an IC pin is not protected against, physical damage including breakdown, metal electromigration, gate oxide rupture and other damage due to an ESD stress may destroy or damage the physical devices within the integrated circuit.

[0002] Prior art ESD protection approaches involve a variety of circuit elements that are associated with the pads of the integrated circuit. Typically, a bond wire couples the input/output pad, which is a metallic or conductive surface, to a package pin. The pins may be gold, copper, palladium and nickel plated material or the like. The ESD protection circuit provides a path to a safe terminal, typically a power supply pin or ground pin, and causes the electro-static current (called a “strike”) to bypass the susceptible semiconductor devices formed within the integrated circuit. An effective ESD circuit can protect a device and prolong its life.

[0003] The level of ESD protection needed for integrated circuits varies widely depending on the application and the type of integrated circuits. Circuits intended for use in automobile applications require particularly robust ESD protection. Similarly, integrated circuits that are intended to be handled by a consumer, such as flash cards and DIMM modules that a consumer physically inserts into a board or slot are particularly vulnerable to human body ESD strikes. In contrast, circuits that are installed into a robust circuit board inside a factory setting and placed on a well protected system in a highly controlled environment may require far less robust ESD protection. The work stations, workers, and the tools used in such an environment can be strapped to a ground terminal, and the humidity and materials used in the environment can be controlled to lower the probability of a static discharge event. In some cases, this protection may lower the ESD probability to a level such that on-board protection circuitry may not be required. This is a rare case, however, and most integrated circuits have some on-board ESD circuitry.

[0004] The electronics industry has created standards and classes for ESD ratings of devices, so that the purchasers of an integrated circuit may know what level of protection or class of ESD event the integrated circuit is designed for. These may be described as classes of protection for a human body model (HBM) event, for example. Class 0 may be for events from 0-2 kilovolts, Class 1 may be from 2 kilovolts to 4 kilovolts, Class 2 may be for greater than 4 kilovolts. Machine model (MM) events are also specified. This information is typically provided by an IC manufacturer so that the buyer understands what ESD stresses the device typically can withstand. Another test framework known as the charged device model (CDM) has been gaining popularity recently for ESD testing because it provides a more practical real world ESD test. The CDM simulates what happens when an IC, in an automated manufacturing environment, becomes electrically charged (e.g., by coming into contact with another material and then being separated from that other material) and then discharges due to contact or proximity with a conductor referenced to another potential or to ground.

[0005] ESD events typically happen between an input, input/output or output pad and another terminal, either VSS (ground) and VDD (positive power supply). Four modes of ESD stress are commonly described. A positive voltage from a pad to VSS may be referred to as a PS strike, a positive voltage from a pad to VDD may be referred to as a PD strike, a negative voltage from a pad to VSS may be referred to as an NS strike, and a negative voltage from a pad to VDD may be referred to as a ND strike. These terms for ESD stress modes are used herein.

[0006] ESD circuits have used silicon controlled rectifier (SCR) structures previously to provide a current path. SCR devices are known in the art to be formed from p-n-p-n or n-p-n-p junctions. Once an SCR device is triggered, it will continue to conduct current so long as an adequate hold current is present, and the low on-resistance R_on for SCR devices and low triggering voltage renders SCR devices particularly useful in ESD protection circuits.

[0007] A challenge associated with the use of SCR structures as ESD clamps has been the relatively low turn-on speed (i.e., relatively long turn-on time) provided by such an approach, which has resulted in low CDM performance. The CDM discharge is a fast transient pulse, which may occur over several nanoseconds as an upper limit. Turn-on efficiency is therefore a factor that impacts ESD performance, e.g., for CDM testing.

[0008] In some embodiments, an electrostatic discharge (ESD) protection structure includes first and second semiconductor structures, an RC power clamp circuit, and at least one gated diode. The first semiconductor structure includes a first semiconductor substrate of a first conductivity type, a first well of the first conductivity type formed into the first semiconductor substrate, and a second well of a second conductivity type formed into the first semiconductor substrate adjacent to the first well. The conductivity types can be P or N type. An intersection of the first and second wells forms a p-n junction. The first semiconductor structure also includes a first diffused region of the first conductivity type formed at the surface of the second well and electrically coupled to a positive power supply terminal, a second diffused region of the second conductivity type formed at the surface of the first well and electrically coupled to a pad terminal, and a third diffused region of the first conductivity type formed at the surface of the first well and electrically coupled to a ground terminal. The second semiconductor structure includes a second semiconductor substrate of the first conductivity type, a third well of the first conductivity type formed into the second semiconductor substrate, and a fourth well of the second conductivity type formed into the second semiconductor substrate adjacent to the first well. An intersection of the first and second wells forms a p-n junction. The second semiconductor structure also includes a fourth diffused region of the second conductivity type formed at the surface of the fourth well and electrically coupled to the positive power supply terminal, a fifth diffused region of the first conductivity type formed at the surface of the fourth well and electrically coupled to the pad terminal, and a sixth diffused region of the second conductivity type formed at the surface of the third well and electrically coupled to the ground terminal. The RC power clamp circuit is coupled between the positive power supply terminal and the ground terminal. The gated diode(s) is configured to selectively provide an electrical path between two of the diffused regions in one of the wells.

[0009] In some embodiments, an electrostatic discharge (ESD) protection structure includes first and second semiconductor structures, an RC power clamp circuit, and at least one conductor. The first semiconductor structure includes a first semiconductor substrate of a first conductivity type, a first well of the first conductivity type formed into the first semiconductor substrate, and a second well of a second conductivity type formed into the first semiconductor substrate adjacent to the first well. An intersection of the first and second wells forms a p-n junction. The first semiconductor structure also includes a first diffused region of the first conductivity type formed at the surface of the second well and electrically coupled to a positive power supply terminal, a second diffused region of the second conductivity type formed at the surface of the first well and electrically coupled to a pad terminal, and a third diffused region of the first conductivity type formed at the surface of the first well and electrically coupled to a ground terminal. The second semiconductor structure includes a second semiconductor substrate of the first conductivity type, a third well of the first conductivity type formed into the second semiconductor substrate, and a fourth well of the second conductivity type formed into the second semiconductor substrate adjacent to the first well. An intersection of the first and second wells forms a p-n junction. The second semiconductor structure also includes a fourth diffused region of the second conductivity type formed at the surface of the fourth well and electrically coupled to the positive power supply terminal, a fifth diffused region of the first conductivity type formed at the surface of the fourth well and electrically coupled to the pad terminal, and a sixth diffused region of the second conductivity type formed at the surface of the third well and electrically coupled to the ground terminal. The RC power clamp circuit is coupled between the positive power supply terminal and the ground terminal. The conductor(s) is configured to selectively provide an electrical path at least partially between one of the diffused regions of the first conductivity type, formed at the surface of one of the wells of the second conductivity type, and one of the diffused regions of the second conductivity type, formed at the surface of one of the wells of the first conductivity type, via the one well of the first conductivity type and the one well of the second conductivity type.

[0010] In some embodiments, an electrostatic discharge (ESD) protection circuit includes a conductive pad of an integrated circuit, typically a contact pad, with circuitry coupled to the pad for buffering data, an RC power clamp circuit on the integrated circuit, and first and second silicon controlled rectifier (SCR) circuits. The RC power clamp is coupled between a positive power supply terminal and a ground terminal. The first SCR circuit is coupled between the pad and the positive power supply terminal. The first SCR circuit has a first trigger input coupled to the RC power clamp circuit. The second SCR circuit is coupled between the pad and the ground terminal. The second SCR circuit has a second trigger input coupled to the RC power clamp circuit. At least one of the SCR circuits includes a gated diode configured to selectively provide an electrical path between the pad and either the positive power supply terminal or the ground terminal.

[0011] In some embodiments, an electrostatic discharge (ESD) protection circuit includes a pad of an integrated circuit, circuitry coupled to the pad for buffering data, an RC power clamp on the integrated circuit, and first and second silicon controlled rectifier (SCR) circuits. The RC power clamp is coupled between a positive power supply terminal and a ground terminal. The first SCR circuit is coupled between the pad and the positive power supply terminal. The first SCR circuit has a first trigger input coupled to the RC power clamp circuit. The second SCR circuit is coupled between the pad and the ground terminal. The second SCR circuit has a second trigger input coupled to the RC power clamp circuit. At least one of the SCR circuits includes a conductor configured to selectively provide an electrical path at least partially between the pad and one of the positive power supply terminal and the ground terminal. The electrical path is a p-n-p, n-p-n, or p-n-p-n path.

[0016] This description of certain exemplary embodiments is intended to be read in connection with the accompanying drawings, which are to be considered part of the entire written description.

[0017] FIGS. 1A and 1B illustrate cross-sectional views of semiconductor structures 100a and 100b that may form part of an electrostatic discharge (ESD) protection structure in some embodiments. The cross-sections of semiconductor structures 100a and 100b are first described below, and then the relationship between the structures and a circuit representation is described further below.

[0018] Referring to FIG. 1A, semiconductor structure 100a includes a semiconductor substrate 120a of a first conductivity type. The first conductivity type may be a P-type or an N-type; a P-type substrate P-SUB is shown in FIG. 1A as an example. A well 109 of the first conductivity type (e.g., P-well in FIG. 1A) is formed into substrate 120a. This well is referred to in the description below as a P-well, although it is understood that in other examples of opposite polarities, the well may be an N-well. A well 108 of a second conductivity type (e.g., N-type or P-type; FIG. 1A shows N-type) is formed into substrate 120a adjacent to P-well 109. An intersection of P-well 109 and N-well 108 forms a p-n junction. P-well 109 and N-well 108 may be formed using any of several known semiconductor fabrication techniques. These may be doped regions, or the N region may be doped and the P-well may be undoped P semiconductor substrate material. The wells may be deposited or grown in an epitaxial process. Thermal diffusion and/or ion implantation may be used to form the wells as is known in the art. SOI techniques may also form N and P-wells as shown.

[0019] A diffused region (diffusion) 101, which may be an N+ diffusion, is formed at the surface of N-well 108 and is electrically coupled to a positive power supply terminal (e.g., VDD). A diffusion 107, which may be a P+ diffusion, is formed at the surface of N-well 108 and is electrically coupled to an input/output (I/O) pad terminal denoted PAD. Diffusions 110 and 106, which may be N+ and P+ diffusions, respectively, are formed at the surface of P-well 109 and are electrically coupled to a ground terminal (e.g., VSS). An isolation region 131, which may be a shallow trench isolation (STI), a LOCOS (local oxidation of silicon) isolation region, or another isolation region, is formed in P-well 109 as shown, separating diffusions 110 and 106. Isolation region 131 may be formed above a non-n-well, non-p-well, bulk material denoted NTN, which is a native device implant block layer that is used to increase the well resistance. Such a bulk material is described at U.S. Pat. No. 7,777,585 to Sonntag. A similar bulk material may be present below comparable isolation regions of FIGS. 1C, 1E, and/or 1G, but is not shown for graphical convenience only. Use of the NTN bulk material improves (reduces) SCR turn-on time. With the NTN layer, the well resistance is increased, causing the trigger current of the SCR to be reduced. Thus, the turn-on time of the SCR is reduced.

[0020] A gated diode 151 is configured to selectively provide an electrical path between N+ regions 101 and P+ region 107. A conductor 152 is configured to selectively provide an electrical path at least partially between P+ region 107 and N+ region 110, via N-well 108 and P-well 109. FIG. 1A shows an example in which conductor 152 is configured to selectively provide an electrical path between P+ region 107 and N+ region 110, and FIG. 1G shows an example in which a similar conductor 152′ provides a partial electrical path between P+ region 107 and N+ region 110.

[0021] For a positive strike from the terminal PAD to the VSS terminal, the arrow labeled “PS” depicts the path from P+ diffusion 107, to N-well 108, into P-well 109, and to the N+ diffusion 110 that is coupled to VSS. This path PS, which is a p-n-p-n path that is characteristic of a silicon controlled rectifier (SCR), is effectuated by conductor 152 when the voltage is high enough to turn on the SCR.

[0022] For a positive strike with respect to the VDD terminal, the arrow labeled “PD” depicts the path from P+ diffusion 107, to N-well 108, to the N+ diffusion 101 that is coupled to VDD. This path PD, which is a p-n path, is effectuated by gated diode 151 when the voltage exceeds the diode's forward bias (turn-on) voltage.

[0023] Referring to FIG. 1B, semiconductor structure 100b includes a semiconductor substrate 120b of the first conductivity type. This substrate is shown as P-SUB in FIG. 1B and may be the same as substrate 120a of FIG. 1A. A well 104 of the first conductivity type (e.g., P-type as in FIG. 1B) is formed into substrate 120b. A well 103 of the second conductivity type (e.g., N-type) is formed into substrate 120b adjacent to P-well 104. An intersection of P-well 104 and N-well 103 forms a p-n junction. A diffusion 106, which may be a P+ diffusion, is formed at the surface of P-well 104 and is electrically coupled to VSS. A diffusion 105, which may be an N+ diffusion, is formed at the surface of P-well 104 and is electrically coupled to PAD. Diffusions 101 and 102, which may be N+ and P+ diffusions, respectively, are formed at the surface of N-well 103 and are electrically coupled to VDD. An isolation region 132, which may be an STI or other isolation region, is disposed between diffusions 101 and 102.

[0024] A gated diode 153 is configured to selectively provide an electrical path between N+ regions 105 and P+ region 106. A conductor 154 is configured to selectively provide an electrical path at least partially between P+ region 102 and N+ region 105, via N-well 103 and P-well 104.

[0025] FIG. 1B shows an example in which conductor 154 is configured to selectively provide an electrical path between P+ region 102 and N+ region 105, and FIG. 1H shows an example in which a similar conductor 154′ provides a partial electrical path between P+ region 102 and N+ region 105.

[0026] For a negative strike from the terminal PAD to the VSS terminal, the arrow labeled “NS” depicts the path from N+ diffusion 105, to P-well 104, to the P+ diffusion 106 that is coupled to VSS. This path NS, which is an n-p path, is effectuated by gated diode 153 when the voltage exceeds the diode's forward bias voltage.

[0027] For a negative strike from the terminal PAD to the VDD terminal, the arrow labeled “ND” depicts the path from N+ diffusion 105, to P-well 104, into N-well 103, and to the P+ diffusion 102 that is coupled to VDD. This path ND, which is an n-p-n-p path that is characteristic of an SCR, is effectuated by conductor 154 when the voltage is high enough to turn on the SCR.

[0028] Thus, embodiments of the present disclosure provide discharge pathways for the four ESD stress modes PS, PD, NS, and ND, thereby providing bidirectional ESD protection using a dual SCR configuration. According to one aspect, the disclosed embodiments are characterized by particularly high speed (fast) turn-on during the onset of a strike event. Relatively faster turn-on is enabled by providing certain current pathways that are more direct (shorter) than current pathways that might otherwise be provided. For example, prior art techniques employ isolation regions (e.g., shallow trench isolation “STI” regions) in places where the present embodiments comprise gated diodes 151 and 153 and conductors 152 and 154 at the surface of the corresponding wells. Such STI regions in conventional approaches effectively cause current paths to traverse a more circuitous route that ventures down into the corresponding well to pass around the isolation region. The embodiments of the present disclosure are configured to enable operation with shorter and more direct current paths from point to point, as opposed to proceeding around an obstructing isolation region. The shorter current path enables faster turn-on of the SCR for improved CDM performance. This short path includes the path along which the strike current is sinked.

[0029] In various embodiments, one or more of gated diode 151, conductor 152, conductor 154, and gated diode 153 is provided in place of (i.e., instead of) an STI region. Providing at least one gated diode or at least one conductor in place of an STI region is for the purpose of providing a current path that becomes conductive during turn-on, along a short ESD current path. The various combinations may be understood with the following notational convention. For each of the gated diodes or conductors 151, 152, 153, and 154, a binary ‘1’ denotes that the corresponding gated diode or conductor is provided (is present), and a binary ‘0’ denotes that an STI region is provided instead of that gated diode or conductor. Thus, a four-bit code XYZW may categorize certain alternative embodiments, where X represents presence of 151, Y represents presence of 152, Z represents presence of 154, and W represents presence of 153. FIGS. 1A and 1B correspond to the code 1111, because gated diode 151, conductor 152, conductor 154, and gated diode 153 are all present.

[0030] FIGS. 1C and 1D correspond to the code 0110, because STI 141 is provided instead of gated diode 151, and STI 143 is provided instead of gated diode 153. Current travels a longer distance (relative to the situation in FIGS. 1A and 1B) for the PD and NS modes in this case, in order to travel around STI regions 141 and 143, respectively. FIGS. 1E and 1F correspond to the code 1001, because STI 142 is provided instead of conductor 152, and STI 144 is provided instead of conductor 154. Current travels a longer distance (relative to the situation in FIGS. 1A and 1B) for the PS and ND modes in this case, in order to travel around STI regions 142 and 144, respectively. In FIGS. 1C-1F, the substrates, wells, and diffusions are the same as in FIGS. 1A-1B, with the changes being in the replacement of some gated diodes or conductors with STI regions, so some reference characters are omitted in FIGS. 1C-1F for graphical convenience only.

[0031] Thus, various combinations of gated diode/conductor or STI may be used, with semiconductor configurations corresponding to codes 0001 through 1111 (i.e., counting up in binary from 0001 to 1111) in various embodiments. In contrast, a conventional configuration might correspond to code 0000, with relatively long paths used for all four ESD modes PS, PD, NS, and ND.

[0032] Gated diodes 151 and 153 and conductors 152 and 154 may be configured in various ways (denoted options I-IV) as shown in Tables 1A-1B.

[0033]

TABLE 1A
Configuration options for gated diode 151 and conductor 152
	Conductor 152
	Bias
	Gated diode 151		Bias	(Normal
Option	Material	Bias	Material	(ESD)	operation)	RPO
I	P-gated	Float	N-PO or	VSS	VSS	no
	diode		high-k
II	P-gated	Float	N-PO or	VSS	VDD	yes
	diode		high-k
III	P-gated	Float	N-PO or	Float	Float	yes
	diode		high-k
IV	P-gated	Float	P-PO or	VSS	VDD	yes
	diode		high-k

[0034]

TABLE 1B
Configuration options for gated diode 153 and conductor 154
	Conductor 154
	Bias
	Gated diode 153		Bias	(Normal
Option	Material	Bias	Material	(ESD)	operation)	RPO
I	N-gated	Float	P-PO or	VDD	VDD	no
	diode		high-k
II	N-gated	Float	P-PO or	VDD	VSS	yes
	diode		high-k
III	N-gated	Float	P-PO or	Float	Float	yes
	diode		high-k
IV	N-gated	Float	N-PO or	VDD	VSS	yes
	diode		high-k

[0035] In option I, which is illustrated by FIG. 2A, gated diode 151 may be of the first conductivity type (e.g., P-type), and gated diode 153 may be of the second conductivity type (e.g., N-type). These gated diodes may be formed without a lightly doped drain (LDD). Without an LDD, capacitance is less, and turn-on time may be reduced. Gated diodes 151 and 153 may be made electrically floating, which also reduces capacitance and thus may reduce turn-on time. Conductors 152 and 154 may be formed from polycrystalline silicon (also known as polysilicon, denoted PO in Tables 1A-1B) or a high-k material. As known in the art, “high-k” stands for high dielectric constant, which is a measure of how much charge a material can hold. High-k materials are generally defined as materials having a dielectric constant (k) higher than that of silicon dioxide, which has a dielectric constant of 3.9. In option I, conductor 152 may be an N-type implant (thus “N-PO” in Table 1A), and conductor 154 may be a P-type implant (“P-PO”).

[0036] RC power clamp 200a can be a known type of power clamp comprising resistor 210, capacitor 212, inverter 214 and field effect transistor (FET) 216. Power clamp 200a is coupled between VDD and VSS. An exemplary such power clamp is described in U.S. Pat. Pub. No. 20100103570 to Song et al., e.g., at FIG. 4 therein. Referring to FIG. 2A of the present disclosure, power clamp 200a provides ESD protection between the power supply terminals VSS and VDD. Inverter 214 will turn on FET 216 during a positive event from VDD to VSS, providing a path for current to flow and protecting sensitive circuitry that might otherwise be damaged. The resistance for resistor 210 and capacitance for capacitor 212 are chosen to cause FET 216 to turn on for an appropriate ESD event, but also chosen to try and keep it from turning on during normal switching operations. Diode Dio_CL provides a path from VSS to VDD for a negative voltage ESD strike between the power supplies.

[0037] In option II, which is illustrated by FIG. 2B, conductors 152′ and 154′ are coupled to nodes A and B, respectively, which are maintained at opposite polarities by inverter 220 of power clamp 200b. The charging of the RC detector at the input to the power clamp inverter 214 distinguishes an ESD event from operational signal rise times. Inverter 220 forces both the pull-up and pull-down SCRs into the required state. FIG. 2B is otherwise similar to FIG. 2A and does not require further description.

[0038] In option III, which is illustrated by FIG. 2C, conductors 152′ and 154′ are electrically floating. The limited capacitance of a floating gate from either of conductors 152 and 154 to PAD is advantageous for high frequency applications. In many RF and switching applications, time intervals for charging capacitance through a resistance slows performance.>

[0039] Option IV, which is also illustrated by FIG. 2B, is similar in some respects to option II, except that the conductivity types of the implants for conductors 152′ and 154′ may be interchanged.

[0040] In each of options II, III, and IV, a resist protection oxide (RPO) layer (silicide block layer) may be used to shorten the discharge current path or to increase the conductivity of the discharge current path. For example, an RPO layer 162 may be used in conjunction with conductor 152′, and an RPO layer 164 may be used in conjunction with conductor 154′. These RPO layers are also shown in the cross-section views of FIGS. 1G and 1H. One purpose of the RPO layer is to reduce leakage during standby conditions. With RPO, the channel current path is obstructed below conductor 152′ and/or conductor 154′. For option I, a higher threshold voltage V_th may reduce leakage, but charging the gate of the gated diode requires time.

[0041] An aspect of the circuit shown in FIG. 2B is that the trigger circuit (e.g., with an RC power clamp circuit) as in options II and IV is coupled to conductors 152′ and 154′. Holding the pull-down SCR with the gate bias turned off during standby mode (i.e., absence of ESD event) accelerates turn-on speed during an ESD event while reducing current leakage in the standby mode.

[0042] The selective use of materials, dopings, and biases to gated diodes and/or conductors as in Tables 1A-1B affects standby current leakage (e.g., reduces the level of disadvantageous leakage in non-ESD scenarios in various embodiments), and timing. Use of dopings or using a high-k material can increase the switching threshold voltage of the parasitic metal oxide semiconductor (MOS) in the corresponding SCR structure to reduce standby current leakage.

[0043] FIG. 3 is a circuit diagram depicting an illustrative exemplary embodiment of an ESD circuit. FIG. 3 provides a circuit equivalent of the semiconductor structures of FIGS. 1A-1B. In FIG. 3, a victim circuit (e.g., an input output buffer) 309 is coupled to the PAD terminal. Circuit 309 includes an input buffer 305 for supplying incoming data to the remaining circuitry, an output signal OUT coupled to a CMOS inverter of PMOS transistor P1 and NMOS transistor N1, input impedance Rin (which may be the parasitic or inherent impedance of the transistors that form buffer 305), and a node Node1 coupled to pad.

[0044] RC power clamp circuit 317 is provided to protect from strikes between VSS and VDD, and vice versa and has an inverter 214 and resistor 210 and capacitor 212 providing the input to the inverter to turn on the FET device 216 to provide a current path between these terminals during an ESD event. Similarly, diode Dio_CL provides a current path from VSS to VDD for a negative ESD strike between these terminals. Gated diodes 151 and 153 provide connections from PAD to VDD and VSS, respectively.

[0045] An ESD protection circuit 371 is also shown in FIG. 3. From PAD to VSS, p-n-p bipolar junction transistor (BJT) 377 is coupled to n-p-n BJT 379 to form an SCR device labeled SCR_D. This SCR may be referred to as a pull-down SCR because when conducting it clamps or pulls the voltage at PAD down to VSS. The p-n-p-n path of SCR_D may correspond to the p-n-p-n path PS of FIG. 1A. The p-n junction from the emitter to the base of p-n-p BJT 377 also provides a diode labeled Dio_U. The resistance in a P-well (e.g., P-well 109) for the n-p-n BJT 379 provides the bias resistor R_pwD for the base of BJT 379. P-n-p BJT 377 is coupled to complete the SCR_D. The N-well (e.g., N-well 108) resistance labeled R_nwD between the power clamp VDD and the base of BJT 377 provides the bias to the base of that transistor. The p-type emitter of transistor 377 couples SCR_D to the pad terminal PAD and provides a p-n diode between the PAD and VDD through the well resistor R_nwD.

[0046] A second SCR provides the upper ESD protection circuit, labeled SCR_U. Typically, functional devices between PAD and VDD are referred to as pull-up circuits, because when PAD is floating, such pull-up circuits may pull the PAD potential up to VDD. Therefore, an SCR (such as SCR_U) as in various embodiments that protects such a pull-up circuit is referred to as a “pull-up” SCR. An SCR such a SCR_D that protects a pull-down circuit likewise is referred to as a pull-down SCR. This SCR, which may correspond to the n-p-n-p path ND of FIG. 1B, is formed of the N-well (e.g., N-well 103) resistance R_nwU from VDD to the base of p-n-p BJT 373, n-p-n BJT 375 and the P-well (e.g., P-well 104) resistance R_pwU from the base of BJT 375 to voltage VSS. The p-n base-emitter junction of BJT 375 also forms a diode labeled Dio_D that is forward biased from VSS to the PAD terminal.

[0047] In FIG. 3, the ESD protection circuit 371 may be placed at each protected input, output or input/output pad for the integrated circuit. There may be dozens, or hundreds, of such pads. The power clamp circuit 317 is only placed in the integrated circuit once, or a few times at most. There is no trigger circuit required for each SCR and for each pad; instead injection current into the wells is used with the RC power clamp circuit to forward bias a transistor during an ESD event, and trigger the SCR to conduct so as to protect the victim circuit.

[0048] Table 2 depicts, for each of the four modes of ESD strike described above, the primary and supporting current flow paths for the ESD protection circuit of FIG. 3.

[0049]

TABLE 2
Primary and supporting current flow paths for ESD protection circuit
	ESD Mode	Main Path	Supporting Path
	PS	SCR_D	Dio_U + FET 216
	PD	Dio_U	SCR_D + Dio_CL
	NS	DIO_D	Dio_CL + SCR_U
	ND	SCR_U	FET 216 + Dio_D

[0050] From Table 2, it can be seen that for an ESD mode PS event, a positive voltage from the PAD terminal to the VSS terminal, the main path is SCR_D. This means that the SCR_D, formed from BJTs 377 and 379 and the well resistors R_pwD and R_nwD as shown in FIG. 3 is triggered and conducts current away from the victim circuit. In the embodiment of FIG. 3, the triggering is done not by a trigger circuit, but instead by means of injection current flowing into wells. Therefore, when current is injected, all of the SCRs of all the protected PADs can become conductive at the same time. In this example, the PS event puts a positive voltage on the PAD with respect to VSS. The voltage at the pad will forward bias the p-n junction of the emitter of BJT 377 with respect to the base of BJT 377 and inject current into the N-well 108. In a PS ESD event, positive ESD current will inject into emitter/base junction of BJT 377 (Dio_U which now is forward biased). The VDD bus is then charged up and the RC power clamp is triggered on to provide a low resistance path to VSS to sustain the emitter/base current of BJT 377. As the ESD (emitter) current increases, significant hole current will flow into the collector (P-well) of BJT 377, which is also the base of BJT 379, then on to VSS through the resistor R_pwD. When the voltage drop of R_pwD exceeds the base/emitter voltage of BJT 379, BJT 379 will turn on. BJT 379 is then coupled with BJT 377 to form a low resistance p-n-p-n device (SCR D). This SCR device provides a direct current discharge path of positive ESD current from the pad to VSS.

[0051] Table 2 further describes that the supporting paths of Dio_U and the transistor 210 in the RC power clamp conduct current during the PS ESD mode event. This improves the effectiveness of the ESD protection by providing additional conductive paths away from the victim circuit coupled to the terminal PAD.

[0052] In Table 2, the next mode depicted is a PD event. In PD mode, a positive voltage from the pad to the VDD supply, the main path for current is the diode Dio_U. Referring to the circuit diagram of FIG. 3, in this mode the p-n junction of diode Dio_U is forward biased and there is a path from the base of BJT 377 through the N-well 108 to voltage VDD; thus a direct path is provided. In addition, SCR_D and the clamp diode Dio_CL provide supporting paths for current to flow. Regarding the supporting path, as the pad to VDD current flow increases, the base voltage of BJT 377 goes up and significant hole current flows into the collector of BJT 377 and turns on the SCR_D. A portion of ESD current will then flow from the pad to VSS through SCR_D, then to VDD through diode Dio_CL.

[0053] ESD events in mode NS, where there is a negative voltage on the PAD with respect to terminal VSS, are also described in Table 2. In this mode, the p-n junction of the base emitter of BJT 375 in FIG. 3, labeled Dio_D, is forward biased and provides a path back to VSS through a P-well (e.g., P-well 104) to the RC clamp circuit. The supporting paths of Dio_CL and SCR_U provide additional current paths to protect the victim circuit from the ESD current.

[0054] The bottom row of Table 2 depicts the paths for an ESD event in ND mode, or a negative voltage at the terminal PAD with respect to the positive voltage supply VDD. In this event, the upper SCR circuit SCR_U in FIG. 3 is triggered by current injection into the P-well 104 the n-p-n transistor is formed in, and there is a path through Dio_D and the transistor 210 that provides supporting paths for the ND event. The protection for ND mode is very similar to that of PS mode. In a ND mode event, negative current is injected to emitter/base of BJT 375. Negative voltage is developed at VSS. The RC power clamp is triggered on to sustain the current. As the negative current increases, significant electron current flows into the collector (N-well 103) of BJT 375, which is also the base of BJT 373, then on to VDD through resistor R_nwU. When the voltage drop of R_nwU exceeds the base/emitter voltage of BJT 373, BJT 373 will turn on. BJT 373 is coupled with BJT 375 to form a low resistance p-n-p-n device (SCR_U). This SCR device provides a direct discharge current path of negative ESD current from PAD to VSS.

[0055] Although examples are illustrated and described herein, embodiments are nevertheless not limited to the details shown, since various modifications and structural changes may be made therein by those of ordinary skill within the scope and range of equivalents of the claims. For example, conductivity types may be interchanged in the examples above, e.g., with P-type replacing all occurrences of N-type and N-type replacing all occurrences of P-type.