System and method for charging back-up charge storage element for data storage device using spindle phase switching elements

[0001] A data storage system may comprise a data storage device (e.g., solid state drive) comprising non-volatile semiconductor memory (NVSM) (e.g., flash memory) and may be employed as mass storage for a computer device (e.g., desktop, laptop, portable, etc.) or other suitable application. The data storage device may also comprise a controller for controlling data operations to the NVSM (i.e., reading data from or writing data to the NVSM), volatile memory (e.g., DRAM) for providing temporary storage for write data coming from the host to the NVSM and read data going to the host from the NVSM, and an I/O interface for communicating between the controller and the host.

[0002] The data storage device is typically coupled to an external power supply for providing power to components of the data storage device, such as the NVSM, the controller, the volatile memory, and the I/O interface. The data storage system may also comprise one or more capacitors that can be charged to provide back-up power to the data storage device to ensure that user data is fully protected in an event of an interruption of power to the data storage device.

[0009] The present disclosure is directed to data storage systems and methods using two spindle phase switching elements in a power device to generate a boost output voltage for charging a charge storage element, wherein the charge storage element provides back-up power for a data storage device in an event of an interruption of power. In an embodiment, an inductor is coupled across the two spindle phase switching elements and control circuitry in the power device controls the two spindle phase switching elements to generate the boost output voltage. In an embodiment, a boost switching regulator in the power device is used to trickle charge the charge storage element when the charge storage element has been charged to the boost output voltage. In an embodiment, a controller in the data storage device is enabled when the charge storage element has been charged to the boost output voltage. In an embodiment, the charge storage element is used to provide back-up power to the data storage device when an input voltage fails below a threshold level.

[0010] Certain embodiments of the invention will now be described. These embodiments are presented by way of example only, and are not intended to limit the scope of the invention. Indeed, the novel systems and methods described herein may be embodied in a variety of forms. Furthermore, various omissions, substitutions and changes in the form of the systems and methods described herein may be made without departing from the spirit of the invention. To illustrate some of the embodiments, reference will now be made to the figures.

[0011] FIG. 1A shows a data storage system 100 according to an embodiment of the present invention comprising a power device 102, a charge storage element 104, an inductor 106, a rectification block 108, switchover circuit 110, and a secondary power rail 112. The data storage system 100 also comprises a data storage device 150 (shown in FIG. 1B). As shown in the embodiment in FIG. 1A, the power device 102 comprises control circuitry 114, a boost switching regulator (BSR) 116, sense logic 118, regulator block 120, timer 122, spindle phase switching elements (SPSE) A, B, and C, and a common power rail 124. In an embodiment, the control circuitry 114, the BSR 116, the sense logic 118, the regulator block 120, and spindle phase switching elements A, B, and C are situated on one integrated circuit (IC), such as an Application-Specific IC (ASIC). In the embodiment in FIG. 1A, the switchover circuit 110 comprises switch control logic 126, switches S1 and S2, and a regulator 128. In one embodiment, the regulator 128 is not utilized in the switchover circuit 110.

[0012] As shown in FIG. 1A, SPSE A comprises high side transistor Q1 coupled to low side transistor Q2, SPSE B comprises high side transistor Q3 coupled to low side transistor Q4, and SPSE C comprises high side transistor Q5 coupled to low side transistor Q6. In the embodiment of FIG. 1A, transistors Q1-Q6 each comprise an N-channel field-effect transistor (NFET). In another embodiment, each of transistors Q1-Q6 may comprise a P-channel FET (PFET) or other type of transistor. The input terminal of each of transistors Q1-Q6 is coupled to the control circuitry 114 to enable the control circuitry 114 to independently control each transistor. As shown in FIG. 1A, SPSE A, B, and C are coupled between the common power rail 124 and ground and the respective outputs of SPSE A, B, and C (provided at the junctions of the high side and low side transistors) are coupled to output terminals 130, 132, and 134 of the power device 102.

[0013] In the embodiment of FIG. 1A, a DC input side of the inductor 106 is coupled to output terminal 130 (i.e., the output of SPSE A) and the switching side of the inductor 106 is coupled to output terminal 132 (i.e., the output of SPSE B). Alternatively, the inductor 106 may be coupled between different SPSE outputs (e.g., between the outputs of SPSE A and C or the outputs of SPSE B and C). In an embodiment, the inductor 106 is coupled between first and second SPSE outputs (e.g., SPSE A and B outputs) and the third SPSE output (e.g., SPSE C output) is coupled to the first or the second SPSE output. For example, in an embodiment in which the inductor 106 is coupled between the outputs of SPSE A and SPSE B, the output of SPSE C may be coupled to the output of SPSE A or the output of SPSE B.

[0014] As shown in FIG. 1A, rectification block 108 for rectifying AC voltage is coupled between the switching side of the inductor 106 at output terminal 132 and the secondary power rail 112 and is operable to rectify an AC voltage at the switching side of the inductor 106. In the embodiment of FIG. 1A, the rectification block 108 comprises a diode. In another embodiment, the rectification block 108 may comprise a transistor or other type of device capable of rectifying AC voltage.

[0015] As shown in FIG. 1A, the charge storage element 104 is coupled between the secondary power rail 112 and ground. In the embodiment of FIG. 1A, the charge storage element 104 comprises a plurality of capacitors (e.g., a bank of capacitors) coupled together in a parallel configuration. In one embodiment, each capacitor in the charge storage element 104 is a ceramic capacitor. Alternatively, the charge storage element 104 may comprise, for example, one or more tantalum capacitors, super capacitors, or other types of non-polarized or polarized capacitors.

[0016] In an embodiment of the invention, during power up of the data storage system 100, switch S1 in the switchover circuit is initially in a closed position, thereby allowing input voltage (Vin) on the primary power rail 138 to be coupled to the common power rail 124 of the power device 102 at the input voltage terminal 136. When Vin is applied to the common power rail 124, a boost mode is triggered in the power device 102. In an embodiment of the invention, during the boost mode the control circuitry 114 is operable to control SPSE A and SPSE B to generate a boost output voltage (Vboostout) on the secondary power rail 112 for charging the charge storage element 104, wherein Vboostout is greater than Vin. For example, Vin may be 5V and Vboostout may be 12V or greater.

[0017] In an embodiment, the control circuitry 114 is operable to generate Vboostout by switching the high side FET Q1 of SPSE A on and the low side FET Q2 off, thereby causing Vin to be coupled to the DC input side of the inductor 106, switching the high side FET Q3 of SPSE B off, and switching the low side FET Q4 on and off continuously so as to generate an AC voltage at the switching side of the inductor 106. The AC voltage is rectified by the rectification block 108 (e.g., a diode) to provide Vboostout on the secondary power rail 112 for charging the charge storage element 104. In an embodiment, the control circuitry 114 is operable to switch the low side FET Q4 on and off with a controlled duty cycle. For example, the control circuitry 114 may adjust the duty cycle of the low side FET Q4 to achieve a desired level of Vboostout or to control how long to charge the charge storage element 104. In one embodiment, the control circuitry 114 controls the switching frequency of the low side FET Q4 in addition to its duty cycle.

[0018] In an embodiment, the control circuitry 114 is coupled to the secondary power rail 112 via a feedback line coupled to a center tap (CT) terminal 140 and the control circuitry 114 is operable to turn off the high side FET Q1 and the low side FET Q4 when the charge storage element 104 is fully charged to Vboostout. In one embodiment, the control circuitry 114 is not coupled to the secondary power rail 112 and the control circuitry 114 is operable to turn off the high side FET Q1 and the low side FET Q4 after Vin has been applied to the common power rail 124 for a predetermined amount of time. For example, the control circuitry 114 may turn off the high side FET Q1 and the low side FET Q4 approximately 20 milliseconds after Vin has been applied to the common power rail 124. In an embodiment, the control circuitry 114 is operable to turn off the unused spindle phase switching element (i.e., SPSE C in the embodiment in FIG. 1A).

[0019] As shown in FIG. 1A, an input of the BSR 116 is coupled to an output of the control circuitry 114 and an output of the BSR 116 is coupled to the secondary power rail 112 via output terminal 142 of the power device 102. In an embodiment, the BSR 116 is operable to provide a trickle charge to the charge storage element 104 via the secondary power rail 112 when the charge storage element 104 has been charged to Vboostout. The trickle charge provided by the BSR 116 enables the charge storage element 104 to remain charged to Vboostout when the control circuitry 114 turns off the spindle phase switching elements (SPSE A and SPSE B) that are coupled to the inductor 106. The BSR 116 uses significantly less current to trickle charge the charge storage element 104 compared to an amount of current required to charge the storage element 104 to Vboostout.

[0020] In one embodiment, the BSR 116 determines when the charge storage element 104 has been charged to Vboostout by monitoring the secondary power rail 112 via a feedback line. In one embodiment, the BSR 116 provides a trickle charge to the charge storage element 104 when the BSR 116 is enabled by the control circuitry 114. In an embodiment, the BSR 116 provides the trickle charge to the charge storage element 104 a predetermined amount of time after input voltage Vin has been applied to the common power rail 124 (i.e., a predetermined amount of time after the boost mode has been initiated). In an embodiment, the control circuitry 114 turns off the high side FET Q1 and the low side FET Q4 after the BSR 116 begins to provide the trickle charge to the charge storage element 104 via the secondary power rail 112.

[0021] In the embodiment of FIG. 1A, the secondary power rail 112 is coupled to an input terminal of switch S2, the output terminal of switch S2 is coupled to the input of a regulator 128, and the output of the regulator 128 is coupled to the input voltage terminal 136 of the power device 102. In an embodiment in which the regulator 128 is not utilized, the output terminal of switch S2 is coupled directly to the input voltage terminal 136. As shown in FIG. 1A, a primary power rail 138, which provides power from an external power supply (not shown in FIG. 1A), is coupled to the input terminal of switch S2 and the output terminal of switch S2 is coupled to the input voltage terminal 136 of the power device 102. Switches 51 and S2 may each be implemented by one or more transistors or other types of semiconductor devices.

[0022] Also shown in FIG. 1A, the outputs of the switch control logic 126 are coupled to respective control terminals of switches S1 and S2, the input of the switch control logic 126 is coupled to the output of the sense logic 118, and the input of the sense logic 118 is coupled to the common power rail 124. The switch control logic 126 is operable to control the operation of switches S1 and S2 in response to an appropriate control signal from the sense logic 118. In an embodiment, the sense logic 118 is operable to monitor Vin on the common power rail and to cause the switch control logic 126 to open or close switches S1 and S2 depending on the level of Vin. For example, if the sense logic 118 detects that Vin has fallen below a threshold level, the sense logic 118 causes the switch control logic 126 to open switch S1 and close switch S2. For example, Vin will fall below the threshold level in an event of an interruption of power to the data storage system 100. In an embodiment, switch S1 opens prior to switch S2 closing to decouple the primary power rail 138 from the common power rail 124, thereby preventing Vboostout on the secondary power rail 112 from being coupled to the primary power rail 138 and, consequently, to the external power supply.

[0023] In the embodiment of FIG. 1A, the regulator block 120 is coupled to the common power rail 124 and comprises regulators A, B, C, and D for providing respective regulated output voltages (Reg. Vout) A, B, C, and D to the data storage device 150 shown in FIG. 1B. It is noted that although the regulator block 120 comprises four regulators in the embodiment shown in FIG. 1A, the number of regulators in the regulator block 120 is dependent on the power requirements of the particular data storage device in the data storage system. Thus, in another embodiment, the regulator block 120 may comprise more or less than four regulators to provide power to a data storage device.

[0024] In an embodiment, whenever Vin falls below a threshold level, Vboostout on the secondary power rail 112 is coupled to the common power rail 124, thereby enabling the regulator block 120 to provide power to the data storage device 150 in FIG. 1B for an amount of time that depends on the storage capacity of the charge storage element 104. For example, in an embodiment in which the charge storage element 104 comprises a plurality of capacitors coupled together in a parallel configuration, the number of capacitors determines the storage capacity of the charge storage element 104 and, consequently, how long the regulator block 120 can provide power to the data storage device when the charge storage element 104 is providing power to the regulator block 120.

[0025] As shown in FIG. 1A, the timer 122 is coupled to the common power rail 124 and generates an enable/disable signal 144, which is coupled to a controller in the data storage device 150 in FIG. 1B. In an embodiment, the timer 122 is operable to enable the controller in the data storage device via the enable/disable signal 144 after input voltage Vin has been applied to the common power rail 124 for a predetermined amount of time. For example, the timer 122 may enable the controller in the data storage device after the input voltage Vin has been applied to the common power rail 124 for approximately 20 milliseconds.

[0026] FIG. 1B shows data storage device 150 according to an embodiment of the present invention comprising a controller 152, a non-volatile semiconductor memory (NVSM) 154, a volatile memory 156, and an I/O interface 158. As shown in the embodiment in FIG. 1B, the controller 152 is communicatively coupled to the NVSM 154 and is operable to control data operations to the NVSM 154 (e.g., reading data from and writing data to the NVSM 154) and is operable to read data from and write data to the volatile memory 156. The NVSM 154 may be used by the host for reading and writing data and may comprise, for example, as flash memory (e.g., NAND or NOR flash memory), Ferroelectric Memory (FeRAM), Phase Change Memory (PC-RAM or PRAM), Resistance RAM (RRAM), Single-Level Cell (SLC) memory, Multi-Level Cell (MLC) memory, or other discrete non-volatile memory chips.

[0027] In the embodiment in FIG. 1B, the controller 152 is further operable to receive the enable/disable signal 144 from the timer 122 shown in FIG. 1A and to begin controlling the aforementioned data operations when enabled by the enable/disable signal 144. In an embodiment, the controller 152 is enabled by the enable/disable signal 144 from the timer 122 (FIG. 1A) after the input voltage Vin (FIG. 1A) has been applied to the common power rail 124 (FIG. 1A) for a predetermined amount of time. In an embodiment, the controller 152 is disabled by the enable/disable signal 144 when Vin falls below a threshold voltage during a power down process.

[0028] As shown in FIG. 1B, the volatile memory 156 is communicatively coupled to the controller 152 and provides temporary storage for write data from the host and read data from the NVSM 154. For example, the volatile memory 156 may comprise dynamic random access memory (DRAM) or static random access memory (SRAM). As shown in FIG. 1B, the I/O interface 158 is communicatively coupled to the host and the controller 152 and enables communication between the host and the controller 152. In the embodiment in FIG. 1B, regulated input voltages (Reg. Vin) A, B, C, and D are received from respective regulators A, B, C, and D in the regulator block 120 (FIG. 1A) in the power device 102 (FIG. 1A).

[0029] FIG. 2A shows a data storage system 200 according to an embodiment of the present invention. In the embodiment in FIG. 2A, the data storage system 200 comprises a power device 202 comprising control circuitry 214 and data storage device 250 (shown in FIG. 2B) comprising controller 252, wherein the control circuitry 214 is operable to send an I/O signal 260 to the controller 252 when the charge storage element 104 in the data storage system 200 has been charged to the boost output voltage Vboostout on the secondary power rail 112. In an embodiment, the I/O signal 260 notifies the controller 252 that the charge storage element 104 has been charged to Vboostout and, consequently, the charge storage element 104 is ready to provide back-up power in an event of an interruption of power to the data storage device 250 (FIG. 2B). In an embodiment, the control circuitry 214 is operable to determine when to send the I/O signal 260 to the controller 252 (FIG. 2B) by monitoring a voltage level on the secondary power rail 112 via a feedback line.

[0030] In the embodiment in FIG. 2B, the controller 252 in the data storage device 250 begins data operations after the controller 252 receives the I/O signal 260 from the control circuitry 214 (FIG. 1A). For example, the controller 252 may read data from the NVSM 154 or write data to the NVSM 154 after the I/O signal 260 has been received.

[0031] FIG. 3 shows a data storage system 300 according to an embodiment of the present invention comprising power device 302, which comprises control circuitry 314. In the embodiment in FIG. 3, the control circuitry 314 is operable to enable a controller in a data storage device (such as the controller 152 in the data storage device 150 shown in FIG. 1B) by enable/disable signal 344 when the charge storage element 104 has been charged to the boost output voltage Vboostout provided at the output of the rectification block 108. In one embodiment, the control circuitry 314 is operable to enable the controller 152 (FIG. 1B) to begin data operations when the input voltage Vin is above a threshold level. In an embodiment, the controller in a data storage device is disabled by the enable/disable signal 344 when Vin falls below a threshold voltage during a power down process.

[0032] FIG. 4 shows a data storage system 400 according to an embodiment of the present invention comprising a voltage monitoring circuit 470. In the embodiment in FIG. 4, the voltage monitoring circuit 470 is coupled to the charge storage element 104 via the secondary power rail 112 and is operable to monitor a voltage level on the charge storage element 104 and enable a controller in a data storage device (such as the controller 152 in the data storage device 150 shown in FIG. 1B) via an enable/disable signal 444 when the charge storage element 104 has been charged to Vboostout.

[0033] The features and attributes of the specific embodiments disclosed above may be combined in different ways to form additional embodiments, all of which fall within the scope of the present disclosure. Although certain embodiments have been disclosed, other embodiments that are apparent to those of ordinary skill in the art, including embodiments which do not provide all of the features and advantages set forth herein, are also within the scope of this disclosure. Accordingly, the scope of protection is defined only by the claims.