Analog-to-digital converter with input voltage biasing DC level of resonant oscillator

[0001] Analog-to-digital converters are ubiquitous in electronic devices, including consumer and industrial devices. Converting an analog input voltage into a digital value enables digital processing to achieve any desirable result, such as converting an analog voltage generated by a sensor into a digital value that can be processed to detect any particular condition. For example, disk drives may employ one or more sensors for detecting vibrations that may adversely affect the servo control system responsible for maintaining the head over a data track during write/read operations. It may be desirable to process these vibration signals digitally in order to provide feed-forward compensation to the servo control system, thereby compensating for the vibrations in real time.

[0011] FIG. 1 shows an analog-to-digital converter according to an embodiment of the present invention comprising a resonant oscillator 1 comprising an input operable to receive an analog input signal 3 and an output operable to output an oscillating signal 5. A DC offset detector 7 is operable to detect a DC offset in the oscillating signal 5 caused by the analog input signal 3, wherein the DC offset is converted into a digital output signal 9 representing the analog input signal 3.

[0012] In the embodiment shown in FIG. 1, the analog-to-digital converter comprises a suitable inverting amplifier 11 which is coupled to the resonant oscillator 1 so that the resonant oscillator oscillates at a resonant frequency. Any suitable resonant oscillator 1 may be employed in the embodiments of the present invention, such as a crystal, or ceramic resonator, or a silicon oscillator. In one embodiment, the analog input signal 3 biases the resonant oscillator 1 which causes a DC offset in the oscillating signal 5. The DC offset detector 7 is operable to convert the DC offset in the oscillating signal 5 into the digital output signal 9.

[0013] The analog input signal 3 may be generated by any suitable source, and in one embodiment shown in FIG. 2, the analog input signal 3 is generated by a suitable sensor, such as a suitable accelerometer in a disk drive for transducing a physical vibration into an analog vibration signal. The embodiment of FIG. 2 also shows an embodiment of the DC detector 7 for converting the DC offset in the oscillating signal 5 into the digital output signal 9. A duty cycle corrector 13 processes the oscillating signal 5 and a fast clock 15 oscillating at a frequency significantly higher than the oscillating signal 5 to detect a time delta dt 17 representing a difference in time that the oscillating signal 5 is above a threshold and below a threshold. The time delta dt 17 is accumulated 19 over N cycles of the oscillating signal 5 as counted by a cycle counter 21 to generate an accumulated time delta 23. A bias control 25 processes the accumulated time delta 23 to generate a bias signal 27 that drives the DC offset in the oscillating signal 5 toward zero. The accumulated time delta 23 is scaled 29 to thereby generate the digital output signal 9 representing the analog input signal 3. Accordingly in this embodiment the DC detector 7 operates as a closed-loop feedback system which attempts to maintain the DC offset in the oscillating signal 5 at zero by driving the bias control 25 with a control signal that is a digital representation of the analog input signal 3.

[0014] FIG. 3 is a timing diagram that illustrates operation of the DC offset detector 7 according to an embodiment of the present invention. The DC offset detector 7 comprises a comparator that splits the sine wave of the oscillating signal Fn′ 5 into positive (above threshold) and negative (below threshold) components. Counters then measure the positive half cycle (T1) and the negative half cycle (T2). When there is a DC offset in the oscillating signal Fn′ 5, these two timings will not be equal. The total difference in timing between the two halves of the waveform (T2−T1) is stored as dt. The output positive edge of the square wave 31 shown in FIG. 3 is therefore advanced by dt/2, and the negative edge is delayed by dt/2. The result is a waveform having a substantially fifty percent duty cycle. The top sine wave shown in FIG. 3 shows the case where the DC offset is negative and therefore dt/2 is positive, and the bottom sine wave shown in FIG. 3 shows the case where the DC offset is positive, and therefore dt/2 is negative.

[0015] FIG. 4 shows an embodiment of the DC offset detector 7 wherein a D-type register 22 is clocked by the fast clock Fc 15, and the threshold of the D-type register 22 corresponds to Vfs in FIG. 3 and establishes the DC offset in the oscillating signal Fn′ 5. When the oscillating signal Fn′ 5 rises above the threshold, a Pedge signal 26 is active which loads the output of up counter 28 into register 30, loads an output of an adder 32 into register 34, and loads a down counter 36 with the output of an adder 38. The Pedge signal 26 also clears up counter 28. When the oscillating signal Fn′ 5 falls below the threshold of the D-type register 22, a Nedge signal 40 is active which loads the output of up counter 28 into register 42, and loads a down counter 44 with the output of an adder 46. Accordingly, register 30 will store T after a full cycle of the oscillating signal Fn′ 5, and register 42 will store T1. The output of adder 32 will be (T−T1=T2) which is stored in register 34. The output of adder 48 will be (T2−T1=dt) which is divided by 2 to generate dt/2. The output of adder 46 will be (T2−dt/2), and the output of adder 38 will be (T1+dt/2). The down counter 36 will therefore count the on-time of the square wave 31 shown in FIG. 3, and the down counter 44 will count the off-time of the square wave 31 shown in FIG. 3 via an SR-type register 52. The resulting square wave 31 will have a substantially fifty percent duty cycle after compensating for the DC offset in the oscillating signal Fn′ 5.

[0016] FIG. 5A shows an embodiment of the present invention wherein the fast clock Fc 15 applied to the DC offset detector 7 is generated using a ring oscillator 54. FIG. 5B shows an alternative embodiment for the DC offset detector 7 that implements the same computations as the embodiment shown in FIG. 4. In this embodiment, the Pedge signal 26 loads the output of an up counter 56 (i.e., T) into a register 58, and loads an up counter 60 with the output of register 62 divided by two (i.e., dt/2). The Pedge signal also clears the up counter 56 and an up/down counter 64 after each cycle of the oscillating signal Fn′ 5. The counting direction of the up/down counter 64 is controlled by the polarity of the oscillating signal Fn′ 5 such that the output of the up/down counter 64 after a cycle of the oscillating signal Fn′ 5 equals dt which is loaded into register 62. A comparator 66 compares the output of register 58 (i.e., T) to the output of up counter 60. When time equals T−dt/2, an SR-type register 68 is set high to time the on-time of the square wave 31. A comparator 70 compares the output of register 58 divided by two (T/2) to the output of up counter 60. When time equals T−T/2 the SR-type register 68 is set low to time the off-time of the square wave 31.

[0017] FIG. 6 shows an embodiment of the DC offset detector 7 wherein the output of the accumulator 19 is stored in a register 71 after every N cycles of the oscillating signal Fn′ 5. The value stored in the register 71 is then converted 73 into a suitable pulse width modulated (PWM) signal or a binary rate multiplier (BRM) signal 75 which drives the bias control 25.

[0018] FIG. 7 shows an embodiment of the bias control 25 wherein the PWM/BRM signal 75 controls the on/off time of a current source 79 that is coupled to a current sink 77. The end result is to supply an average amount of bias current 81 to node 83 that cancels the bias current of the analog input signal 3. In one embodiment, the bias signal 27 generated by the bias control 25 (such the current sink/source embodiment of FIG. 7) has substantially no effect on an input impedance of the resonant oscillator 1. In this manner, the bias signal 27 has minimal affect on the operating characteristics of the resonant oscillator 1. In the embodiment of FIG. 7, a START signal 85 disables the DC offset detector 7 (by disabling the current sink 77 and the current source 79) during a startup operation until the resonant oscillator 1 begins oscillating normally.

[0019] The resolution of the analog-to-digital converter is determined by the frequency of the fast clock 15 used to count the time intervals that the oscillating signal Fn′ 5 is above and below the threshold, as well as the frequency of the oscillating signal Fn′ 5. This is illustrated in FIG. 8A wherein the positive and negative intervals of the oscillating signal Fn′ 5 are timed by the fast clock 15 (represented as tick marks) relative to a threshold. In the example shown, the positive interval comprises three cycles of the fast clock 15 (three tick marks), and the negative interval comprises five cycles of the fast clock 15 (five tick marks). This relationship will hold until the DC offset in the oscillating signal Fn′ 5 changes by a relatively large step size, thereby resulting in a relatively low conversion resolution of the analog input signal 3.

[0020] In one embodiment, the low conversion resolution shown in FIG. 8A is ameliorated if the analog input signal 3 comprises a sufficient amount of noise. This is illustrated in FIG. 8B wherein the noise in the analog input signal 3 causes a corresponding dither in the oscillating signal Fn′ 5. The dither in the oscillating signal Fn′ 5 will increase the effective conversion resolution by averaging the positive/negative intervals over multiple cycles of the oscillating signal Fn′ 5. That is, the dither in the oscillating signal Fn′ 5 will cause a different positive/negative interval measurement for different cycles of the oscillating signal Fn′ 5, and the average over N cycles will provide a higher resolution conversion as compared to FIG. 8A. The conversion resolution increases with an increasing N; however, the maximum N is limited by the frequency of the analog input signal 3. Accordingly, in one embodiment the frequency of the resonant oscillator 1, the frequency of the fast clock 15, and the number of cycles N to average the positive/negative intervals are selected based on the maximum frequency of the analog input signal 3 in order to achieve a desired performance.

[0021] FIG. 8C shows an embodiment for increasing the conversion resolution when the noise in the analog input signal 3 is not sufficient to provide the desired dither effect (or when a lower N value is needed). In this embodiment, the fast clock 15 is verniered by selecting a frequency for the fast clock 15 that is a non-integer multiple of the oscillating signal Fn′ 5. For example, in the embodiment of FIG. 8A each cycle of the oscillating signal Fn′ 5 spans 8 cycles of the fast clock 15 with the positive/negative intervals timed over 12 cycles of the oscillating signal Fn′ 5 (N=12) or 8×12=96 cycles of the fast clock 15. After verniering the fast clock 15, in the embodiment shown in FIG. 8C there are (8×12)+1=97 cycles of the fast clock 15. In another embodiment, there may be (8×12)−1=96 cycles of the fast clock 15. In either embodiment, verniering the fast clock 15 has a similar effect as the noise dithering the oscillating signal Fn′ 5 shown in FIG. 8B, thereby increasing the conversion resolution.

[0022] FIG. 8D shows an alternative embodiment for increasing the conversion resolution which may be used instead of, or in addition to, the embodiment shown in FIG. 8C. In the embodiment of FIG. 8D, the threshold used to time the positive/negative intervals is dithered, for example, by dithering the threshold of the D-type register 22 shown in FIG. 4. Dithering the threshold as shown in FIG. 8D increases the conversion resolution by averaging over N cycles of the oscillating signal Fn′ 5 similar to verniering the fast clock 15 and similar to the noise dithering the oscillating signal Fn′ 5 shown in FIG. 8B.

[0023] Any suitable timing circuitry may be employed to vernier the fast clock 15 as shown in FIG. 8C and/or dither the threshold as shown in FIG. 8D. In one embodiment, the frequency of the fast clock 15 and/or the frequency of the threshold dither may be determined theoretically through mathematical derivation, or determined empirically during a calibration procedure. Similarly, the value selected for N may be determined theoretically through mathematical derivation, or determined empirically during a calibration procedure. For example, in an embodiment where the analog-to-digital converter is employed in a disk drive, the control circuitry of the disk drive may execute a calibration procedure to calibrate the various parameters that affect the performance of the analog-to-digital converter based on the desired resolution and conversion speed (sample rate).