Hybrid drive writing extended error correction code symbols to disk for data sectors stored in non-volatile semiconductor memory

[0001] The present application claims priority from co-pending provisional U.S. Patent Application Ser. No. 61/378,869, filed on Aug. 31, 2010, the specification of which is incorporated herein by reference.

[0002] Hybrid drives are conventional disk drives augmented with a non-volatile semiconductor memory (NVSM) such as a flash which helps improve certain aspects of the disk drive. For example, the non-volatile semiconductor memory may store boot data in order to expedite the boot operation of a host computer. Another use of a NVSM may be to store frequently accessed data and/or non-sequential data for which the access time is typically much shorter than the disk (which suffers from mechanical latency including seek and rotational latency). Other policies may reduce write amplification of the NVSM in order to maximize its longevity, such as storing frequently written data to the disk (or data having a write/read ratio that exceeds a predetermined threshold).

[0017] FIG. 1A shows a hybrid drive according to an embodiment of the present invention comprising a head 2 actuated over a disk 4, and a non-volatile semiconductor memory (NVSM) 6. The hybrid drive further comprises control circuitry 8 operable to execute the flow diagram of FIG. 1B wherein a write command is received from a host (step 10), the write command comprising data. First and second error correction code (ECC) symbols are generated over the data (step 12), wherein the second ECC symbols are different than the first ECC symbols. The data and first ECC symbols are written to the NVSM (step 14), and the second ECC symbols are written to the disk (step 16).

[0018] In the embodiment of FIG. 1A, any suitable NVSM 6 may be employed, such as any suitable electrically erasable/programmable memory (e.g., a flash memory). In one embodiment, the NVSM 6 comprises a plurality of blocks, where each block comprises a plurality of memory segments referred to as pages, and each page may store one or more data sectors. The blocks are programmed a page at a time, and an entire block is erased in a unitary operation.

[0019] The disk 4 shown in the embodiment of FIG. 1A comprises a plurality of data tracks 18 defined by servo sectors 20₀-20_N, wherein each data track comprises a plurality of data sectors accessed indirectly through a logical block address (LBA). The control circuitry 8 processes a read signal 22 emanating from the head 2 to demodulate the servo sectors 20₀-20_N into a position error signal (PES) representing a position error of the head relative to a target data track. The control circuitry 8 comprises a servo compensator for filtering the PES to generate a control signal 24 applied to a voice coil motor (VCM) 26 that rotates an actuator arm 28 about a pivot in order to actuate the head 2 radially over the disk 4 in a direction that reduces the PES.

[0020] The NVSM 6 is typically accessed faster than the disk 4, particularly for non-sequential access commands where accessing the disk involves a seek latency of the head and a rotational latency of the disk. Therefore, the NVSM 6 typically improves the performance of a hybrid drive as compared to a conventional disk drive. However, the size of the NVSM 6 is typically limited to reduce cost, thereby limiting the performance benefit. In addition, the reliability of recorded data is a significant concern whether stored on the disk or the NVSM. To increase reliability, data is typically recorded with ECC symbols that enable the detection and correction of errors during read operations. However, the ECC symbols are overhead that decreases the storage capacity of the storage medium, and in the case of the NVSM, reduces the performance benefit.

[0021] Accordingly, in an embodiment of the present invention, when data is written to the NVSM a first number of ECC symbols are generated for detecting and correcting a first number of errors during read operations, and a second (greater) number of ECC symbols are generated for detecting and correcting a second (greater) number of errors. This embodiment is understood with reference to the flow diagram of FIG. 2, wherein when a read command is received from the host (step 30) and the data is stored in the NVSM (step 32), the data and first ECC symbols are read from the NVSM (step 34). If the data sector is unrecoverable using the first ECC symbols (step 36), the second ECC symbols are read from the disk (step 38) and used to recover the data (step 40).

[0022] In one embodiment, the first number of ECC symbols is small enough to increase the user data capacity of the NVSM, but large enough to ensure the correction power is sufficient most of the time to avoid the performance degradation due to accessing the disk to read the second ECC symbols. In one embodiment, the second ECC symbols for a number of the NVSM data sectors may be cached in a volatile semiconductor memory (e.g., RAM) to avoid the latency in accessing the disk. For example, in one embodiment the second ECC symbols for the most frequently read (or most recently read) NVSM data sectors may be read from the disk and cached in a RAM as part of the normal operation of the hybrid drive.

[0023] Any suitable ECC algorithm may be employed to generate the first and second ECC symbols. In one embodiment, a suitable polynomial code (e.g., a Reed-Solomon code) may be used to generate both the first and second ECC symbols. This embodiment is understood with reference to FIG. 3A wherein a first generator polynomial is used to generate the first ECC symbols appended to the NVSM data sectors, and a second (longer) generator polynomial is used to generate the second ECC symbols. In the embodiment shown in FIG. 3A, the second ECC symbols generated for a number of NVSM data sectors may be written to a single disk data sector, wherein third ECC symbols may be generated for appending to the disk data sector. In one embodiment, the second ECC symbols are accumulated in a RAM data sector until the RAM data sector is full, and then the RAM data sector is written to the disk data sector (together with the third ECC symbols). If a power failure occurs prior to flushing the RAM data sector to the disk, the RAM data sector may be rebuilt when the hybrid drive is powered on.

[0024] In one embodiment, the number of second ECC symbols generated for an NVSM data sector equals the number of third ECC symbols generated for a disk data sector as illustrated in FIG. 3A. Referring to FIG. 3B, in one embodiment the same generator polynomial 42 may be used to generate both the second ECC symbols for an NVSM data sector and the third ECC symbols for a disk data sector. Similarly, the same error detection and correction circuitry used to recover a disk data sector may be used to recover an NVSM data sector that is unrecoverable using the first ECC symbols.

[0025] FIG. 4A shows an embodiment of the present invention wherein the NVSM comprises a plurality of NVSM data sectors including a first and second NVSM data sector. Each NVSM data sector comprises data and first ECC symbols, and the second ECC symbols are generated over the data of at least the first and second NVSM data sectors. In the example of FIG. 4A, the second ECC symbols are generated over twelve NVSM data sectors; however, the second ECC symbols may be generated over any suitable number of NVSM data sectors. The second ECC symbols may be generated using any suitable algorithm, wherein in the example shown in FIG. 4A, the second ECC symbols are generated as a parity 44 over the data of the NVSM data sectors. When the parity information (second ECC symbols) is written to the disk, the third ECC symbols are written to the disk to protect the parity information.

[0026] FIG. 4B shows an embodiment wherein the second ECC symbols (parity) are generated over multiple NVSM data sectors as each NVSM data sector is written, and the result stored in a RAM data sector which is then flushed to the disk when full. This embodiment is understood with reference to the flow diagram of FIG. 5 wherein when a write command is received from a host (step 46) and the write command is routed to the NVSM (step 48), the first ECC symbols are generated (step 50) and the second ECC symbols in the RAM data sector are updated (step 52) using the data in the write command. The data and the first ECC symbols are then written to an NVSM data sector (step 54). In one embodiment, the RAM data sector stores the parity of the NVSM data sectors, wherein the RAM data sector is updated each time a new NVSM data sector is written by combining the previous contents of the RAM data sector with the new write data. When the target number of NVSM data sectors have been written meaning that the RAM data sector is full (step 56), the RAM data sector is written to the disk (step 58) together with the third ECC symbols generated for the disk data sector. If a power failure occurs before the RAM data sector is flushed to the disk, the RAM data sector may be rebuilt when the hybrid drive is powered on.

[0027] In one embodiment, a parity data sector is generated for each block of memory in the NVSM, and the parity sector is flushed to the disk when a current open block is filled with data. A new parity sector is then started for the next block opened. In other embodiments, multiple parity sectors may be generated for each block, and in an embodiment described below with reference to FIG. 8B, multiple parity sectors may be generated in multiple dimensions over multiple blocks.

[0028] FIG. 6A is a flow diagram according to an embodiment of the present invention which is further understood with reference to FIG. 6B. When a read command is received from the host (step 60) and the data is stored in the NVSM (step 62), the target NVSM data sector is read (step 64). If the NVSM data sector is unrecoverable using the first ECC symbols (step 66), the other NVSM data sectors corresponding to the parity sector are read (step 68) and the parity sector (second ECC symbols) is read from the disk (step 70). The target NVSM data sector is then recovered by combining the other NVSM data sectors and the parity sector (step 72).

[0029] FIG. 7A is a flow diagram according to an embodiment of the present invention which extends on the flow diagram of FIG. 6A. In this embodiment, if a parity sector is needed to recover a target NVSM data sector (step 72), the recovered data is written to a new NVSM data sector in a new NVSM block (step 74) as illustrated in FIG. 7B. The location of the new NVSM data sector in the new block is saved so that it can be used to recover other data sectors in the old block when needed (step 76). In an alternative embodiment, the parity sector may be regenerated for the old block minus the relocated NVSM data sector, although this embodiment requires the regenerated parity sector to be saved to the disk.

[0030] FIG. 8A shows an embodiment of the present invention wherein the NVSM comprises a plurality of blocks, each block comprises a plurality of NVSM data sectors, and each block is erasable in a unitary operation. A first block comprises a first NVSM data sector and a second block comprises a second NVSM data sector, wherein a parity sector is generated over at least the first and second NVSM data sectors (illustrated as a horizontal combination of the NVSM data sectors across multiple blocks). In this embodiment, if an entire block of the NVSM becomes unrecoverable the NVSM data sectors of the bad block may still be recovered using the parity sectors stored on the disk (assuming the other NVSM blocks are recoverable).

[0031] FIG. 8B shows an embodiment of the present invention wherein disk parity sectors are generated in two dimensions which enables recovering up to two NVSM data sectors per block. In the example shown in FIG. 8B, a first disk parity sector is generated over at least a first NVSM data sector of a first block and a second NVSM data sector of a second block (horizontal direction). A second disk parity sector is generated over the first NVSM block (vertical direction) and a third parity sector is generated over the second NVSM block (vertical direction) and so on. This embodiment enables the recovery of up to two NVSM data sectors per block unrecoverable using the first ECC symbols.

[0032] FIG. 9 is a flow diagram according to an embodiment of the present invention which expands on the flow diagram of FIG. 2, wherein after recovering data using the second ECC symbols (step 40) the recovered data is verified using the first ECC symbols read from the NVSM data sector (step 78). This embodiment assumes that the first ECC symbols are recoverable from the NVSM data sector. When the second ECC symbols are used to recover the data, the first ECC symbols can be used to verify that the NVSM data sector no longer contains errors. If the second ECC symbols incorrectly recover the data (e.g., if the wrong parity sector or a corrupted parity sector is used to recover data), the first ECC symbols will detect the invalidity of the recovered data.

[0033] In one embodiment, the number of times the second ECC symbols are needed to recover an NVSM data sector is used to determine when to retire a block in the NVSM. That is, the occurrence of unrecoverable NVSM data sectors may indicate an NVSM block is failing, and therefore the NVSM block is retired.

[0034] Any suitable control circuitry may be employed to implement the flow diagrams in the embodiments of the present invention, such as any suitable integrated circuit or circuits. For example, the control circuitry may be implemented within a read channel integrated circuit, or in a component separate from the read channel, such as a disk controller and/or NVSM controller, or certain steps described above may be performed by a read channel and others by a disk controller and/or NVSM controller. In one embodiment, the read channel and controllers are implemented as separate integrated circuits, and in an alternative embodiment they are fabricated into a single integrated circuit or system on a chip (SOC). In addition, the control circuitry may include a suitable preamp circuit implemented as a separate integrated circuit, integrated into the read channel or disk controller circuit, or integrated into an SOC.

[0035] In one embodiment, the control circuitry comprises a microprocessor executing instructions, the instructions being operable to cause the microprocessor to perform the steps of the flow diagrams described herein. The instructions may be stored in any computer-readable medium. In one embodiment, they may be stored on a non-volatile semiconductor memory external to the microprocessor, or integrated with the microprocessor in a SOC. In another embodiment, the instructions are stored on the disk and read into a volatile semiconductor memory when the hybrid drive is powered on. In yet another embodiment, the control circuitry comprises suitable logic circuitry, such as state machine circuitry.