Electrostatic discharge protection rail clamp with discharge interruption circuitry

[0001] The invention is directed toward electrostatic discharge protection circuitry.

[0002] The amount of electrostatic charge on an object can be rapidly altered as a result of an electrostatic discharge (ESD) event. An ESD event can alter the electrical characteristics of circuitry including semiconductor components so as to degrade or destroy the components. The voltage potential from accumulated charge may exceed the component's breakdown threshold and lead to damage from excessive voltage or damage from the resulting discharge currents. As electrical devices and components have become smaller, they have become more susceptible to harm from ESD events.

[0003] ESD events impact production yields, product quality, and product reliability. ESD events can occur throughout manufacturing, testing, shipping, handling, or use of a product. Component damage can occur due to a discharge or from the accumulation of charge. Ample opportunities for an ESD event arise during the manufacture and use of electronic circuitry including integrated circuits.

[0004] ESD mitigation approaches are implemented to improve or ensure production yields, product quality, or product reliability. With respect to integrated circuits, ESD protection circuitry is incorporated into the integrated circuits to protect the core of the integrated circuit from ESD events that might occur during manufacture, testing, and use. Integrated circuit ESD protection typically shunts current on integrated circuit pads or voltage rails through a device more suitable for carrying larger currents than the core of the integrated circuit.

[0005] One ESD protection circuit architecture uses a shunt having a trigger with a short time constant. The short time constant enables the ESD protection circuitry to better distinguish between normal transient events such as a power-up and fast events such as ESD, to avoid undue interference with transient operations that are part of the normal operation of the integrated circuit. The smaller time constant can cause the ESD protection circuitry to inadequately dissipate the charge or to take an undesirably long time to dissipate the charge.

[0006] Another ESD protection circuit architecture uses a shunt having a trigger with a long time constant. The long time constant can result in a more complete dissipation of the charge or a faster dissipation of the charge. One disadvantage of the long time constant, however, is that the ESD protection circuit may be less capable of consistently and reliably distinguishing an ESD event from other transient events such as a power-up. Another disadvantage of typical long time constant shunt designs is the relatively large semiconductor die area used to implement the long time constant.

[0007] Methods and apparatus for providing ESD protection are described. One method of protecting a circuit from an ESD event includes providing a selectable shunt between a first node and a second node of the circuit. The shunt is enabled by activation circuitry in response to an ESD event on the first node. The shunt activation circuitry is associated with a time constant τ=τ₁ for detecting the ESD event. The activation circuitry is configured such that τ=τ₂ subsequent to enabling the shunt, wherein τ₂>τ₁.

[0008] In one embodiment, an electrostatic discharge (ESD) protection circuit apparatus includes activation circuitry coupled to a first node. The activation circuitry includes a capacitor and a selectable load. A time constant τ associated with the activation circuitry varies in accordance with the selectable load. The activation circuitry is configured to provide τ=τ₁ for detection of an ESD event. A shunt is selectively enabled by the activation circuitry to short the first node to a second node in accordance with the detection of the ESD event. The activation circuitry is configured subsequent to the detection of the ESD event to provide τ=τ₂/wherein τ₂>τ₁.

[0009] Other features and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows.

[0017] An imbalance of electrical charge on the surface of an object is referred to as an electrostatic charge or static electricity. An electrostatic charge can accumulate onto an object by various means including contact with another charged object, induction, and ion bombardment.

[0018] Electrostatic charge can also be accumulated through triboelectric charging. Triboelectric charging occurs due to the transference of electrons from the surface of one object to the other object. Triboelectric charging can occur as a result of contact and subsequent separation of two objects even if the objects are electrically neutral or at the same electrical potential (i.e., relative neutrality).

[0019] The accumulation of electrostatic charge from typical manufacturing tasks may result in a change in electrical potential by several thousands or even tens of thousands of volts. The amount of charge can be altered by subsequent electrostatic discharge (ESD). ESD is a transfer of charge between objects at different electrical potentials.

[0020] Although the characteristic profile of an ESD event may vary depending upon the manner of charge accumulation and the characteristics of the discharge path, an ESD event is generally a transient event with a fast rise time (up to ten nanoseconds) and a short duration up to one microsecond). In contrast, expected transient events such as a power-up have rise times on the order of milliseconds and last considerably longer than an ESD event.

[0021] ESD events are sometimes caused by contact with the human body, by machinery such as manufacturing or test equipment, or in electrically active environments, as may be incurred in many consumer applications. Opportunities for electrostatic discharge can occur at any point during operation or various stages of device life including manufacturing, testing, shipping, and handling of an assembled device or its components. The damage can result as a result of a discharge to or from the device or individual components. Damage can also result from the electrostatic fields accompanying the charge transfers.

[0022] An ESD event can alter the electrical characteristics of circuitry including semiconductor components. The voltage potential from accumulated charge may exceed the component's breakdown threshold and lead to damage from excessive voltage or damage from the resulting discharge currents. As electrical devices and components have become smaller, they have become more susceptible to harm from ESD events. Even if an ESD event does not destroy a component, the component may be operationally degraded. Degradation can be more detrimental than destruction because the degradation might not be readily detectable. For example, operational degradation can lead to unexpected behavior from an operating device or render components or circuitry unexpectedly vulnerable to a subsequent ESD event.

[0023] A variety of ESD events can occur in electronic components including integrated circuits such as: discharge between the pads of an integrated circuit, discharge between voltage supply terminals, and discharge between pads and voltage supply terminals. Various types of ESD protection circuitry can be used to protect integrated circuitry during manufacture, testing, and operation. In general, ESD protection circuitry is used to protect the input/output circuitry and internal circuitry of an integrated circuit from excessively large and sudden discharges of electrostatic energy.

[0024] The objective for ESD protection in general is to provide a shunting path for each potentially damaging ESD path. Integrated circuit ESD damage typically occurs in metal-oxide semiconductor field effect transistor (MOSFET) devices or interconnecting layers coupling MOSFETs together to form a circuit. Each pin in an integrated circuit must be coupled to an appropriate ESD protection circuit such that the ESD discharge current is shunted away from the internal portions of the chip that are the most sensitive to damage. As such, ESD discharge paths must be provided between every pair of pins in an integrated for both positive and negative polarities.

[0025] For example, a shunting path is required to the top rail for ESD currents produced by ESD potentials applied to the protected node that are significantly more positive than anywhere else on the integrated circuit. Similarly, a shunting path is desirable for ESD currents that are produced by ESD potentials that are significantly more negative than elsewhere on the integrated.

[0026] Just as ESD pulses can be applied between the input/output (I/O) pads and the supply rails, ESD discharges can occur between the power supply rails. For example, for top rail to bottom rail stress, ESD current typically flows through a rail clamp from the top rail to the bottom rail. For bottom rail to top rail stress, ESD current flows from the bottom rail to the top rail.

[0027] A rail clamp may be utilized to provide a coupling between the top and bottom rails for those ESD paths that require such a coupling in order to complete the discharge loop. A rail clamp circuit is typically a fundamental component in providing a discharge path for ESD polarities that cause the first current electrode of the rail clamp to be more positive than its second current electrode. For polarities that cause the second current electrode of the rail clamp to be more positive than the first, a power bus diode can be used for the ESD dissipation path. This power bus diode often exists by default in an integrated circuit and is normally reversed-biased during normal operation. In general, one objective of the ESD protective circuitry is to keep the maximum voltage potential in the discharge loop within acceptable limits.

[0028] ESD events are usually less than one microsecond in duration. The rise times are usually less than approximately ten nanoseconds. ESD events at the input/output (I/O) pads of an integrated circuit can produce rising potentials on the power supply rails. The rail clamp circuit must be able to detect these fast transients and begin conducting so as to shunt the resulting ESD current. However, the rail clamp must distinguish between an ESD event and other transient events that are part of normal operation. For example, the rail clamp should not trigger during a power-up of the integrated circuit.

[0029] Once triggered, the rail clamp circuits should stay in a highly conductive state for the entire duration of the ESD pulse so that all of the ESD energy is safely discharged. If the rail clamp circuit were to shut-off prematurely, the ESD energy may not be fully discharged thus damaging potentials can build up between the power rails resulting in device failure.

[0030] The time constant associated with the trigger typically also controls the length of time the shunt is enabled. The choice of a short time constant leads to fast detection of an ESD event and ease of differentiation between an ESD event and a power-up event. The choice of a longer time constant causes the ESD protection circuit to less reliably differentiate between an ESD event and a power-up event. Instead of selecting a single time constant between these extremes for triggering and dissipation, an ESD protection circuit utilizing a first time constant for triggering and a second time constant for dissipation is described.

[0031] FIG. 1 illustrates one embodiment of an ESD protection circuit. ESD protection circuit 100 shunts the supply (VSUP) and ground (GND) rails or nodes to each other in the event an ESD event is detected on the VSUP rail.

[0032] The primary components of the ESD protection circuit includes shunt activation circuitry and the shunt 160. The shunt activation circuitry includes a capacitor 110 and a selectable load 120. In one embodiment, the capacitor 110 is a transistor adapted to function as a capacitor. Series-coupled transistors 122, 124, and 126 form the selectable load 120. Additional circuitry such as pull-up resistors 114, 116, inverters 130, 150, 170, and transmission gate 140 ensure initial conditions or perform various signal conditioning functions for the primary components. The operation of the ESD protection circuit may be better understood in view of the profiles of the types of events anticipated for the power supply rails.

[0033] FIG. 2 illustrates one embodiment of an ESD event profile 200 occurring on the VSUP rail and any node of that rail such as might occur from contact with a human body. A significant change in node voltage occurs over nanoseconds. The ESD event is a transient event characterized by an initial high slew rate relative to the slew rate of slew rates expected for power-up events. The ESD protection circuit should be triggered to shunt the ESD current near the inception of the ESD event. The shunt should be enabled throughout the duration of the ESD event.

[0034] FIG. 3 illustrates one embodiment of a power-up event for the VSUP rail. The power-up event profile 300 exhibits a smaller maximum slew rate than does the ESD event profile of FIG. 2. Indeed, the slew rates vary by at least a few orders of magnitude. In the illustrated embodiment, profile 300 also exhibits a substantially monotonic change in slew rate from the power-off to the power-up states.

[0035] Referring back to FIG. 1, the operation of the ESD protection circuit is explained in the context of an ESD event occurring at any first node coupled to the VSUP rail. The resistance provided by selectable load 120 for the current path from node 112 to ground can be selected from at least two values. When transistors 122-126 are “on” as determined by the gate voltage at transistor 124, selectable load 120 provides a first resistance, RS1. When any of transistors 122-126 is “off” as determined by the gate voltage of transistor 124, selectable load 120 provides a second resistance, RS2. In the illustrated embodiment, RS2 can be very large due to the electrical properties of the field effect transistors. In particular RS2>>RS1. The only current flowing through the selectable load is leakage current. The time constant τ associated with the activation circuitry is determined predominately by the capacitance in conjunction with the resistance (RS1 and RS2) of the load 120.

[0036] The ESD event causes the capacitor 110 to increase the voltage at node 112. The selectable load is providing a first resistance (RS1) at this time because transistors 122, 124, and 126 are conducting due to pull-up resistors 114, 116 and the voltage supplied by the ESD event itself. As a result the shunt activation circuitry is associated with a first time constant, τ=τ₁ for triggering in response to an ESD event.

[0037] Inverter 130 inverts the node 112 output to provide an inverted activation circuitry signal to transmission gate 140. In the illustrated embodiment, transmission gate 140 comprises a p-type metal oxide semiconductor (PMOS) transistor and an n-type metal oxide semiconductor (NMOS) transistor. The transmission gate performs signal conditioning.

[0038] The PMOS transistor of the transmission gate passes a strong 1 but only a weak 0. The NMOS transistor of the transmission gate passes a strong 0 but only a weak 1. These properties are due to the voltage drops resulting from the transistor threshold voltages.

[0039] The inverted activation circuitry signal is passed to inverter 150. The output of inverter 150 enables the shunt 160 that effectively shorts the VSUP and GND rails to each other. Shunt 160 is embodied as a relatively large transistor. The gate of the transistor is coupled to the output of inverter 150. In one embodiment, the shunt is a field effect transistor. Once the shunt is enabled, the shunt diverts the bulk of the ESD event to the GND rail.

[0040] The time constant that proved useful for detecting the ESD event will result in rapid depletion of charge from node 112 through the selectable load. This in turn can result in premature termination of the shunting effect of shunt 160. In order to keep the shunt enabled, the dissipation of charge from node 112 through selectable load 120 is interrupted using feedback from the shunt.

[0041] The output of inverter 150 is itself inverted by 170 such that the input to the gate of transistor 124 of the selectable load is complementary to the gate voltage of the shunt. Thus the control for the shunt also effectively controls the resistance presented to node 112. The output of inverter 170 will rise to turn off the gate of transistor 124 for the remaining duration of the ESD event. Turning off transistor 124 ensures that only leakage current now passes from node 112 through the selectable load. The selectable load has thus effectively become a very large resistance (RS2) that significantly alters or interrupts the charge dissipation from node 112. The only current flowing is due to nominal leakage through transistors 122-126.

[0042] The resistance now presented by the selectable load results in changing the time constant associated with the activation circuitry to a second value, τ=τ₂ and τ₂>τ₁. In various embodiments,

[0043] $\frac{{\tau }_2}{{\tau }_1}>100.$

[0044] As a result of the much larger time constant, the node 112 voltage is sustained to keep the shunt operational until the ESD event has been dissipated. The manner of achieving the larger resistance is also preferable to alternatives that require significant die area for fabrication of large resistors. The activation circuitry thus utilizes a first time constant for detecting the ESD event and a second time constant for holding the shunt enabled.

[0045] FIG. 4 illustrates one embodiment of a slew rate rejection profile 400 of the ESD protection circuit of FIG. 1. In particular, the voltage at node 152 is shown in response to various VSUP slew rates. The time constants are selected to ensure that shunt triggering occurs outside the slew rates anticipated for power-up events. Due to process, voltage, and temperature variations, prior art ESD protection circuits with a single time constant could have significant variations in triggering threshold and duration of the shunting effect. Allowances would need to be made during the design process to ensure that such a design could distinguish between the ESD event and a power up across a wide range of process, voltage, and temperature variations. In contrast, the present design enables greater resolution in capturing ESD events while rejecting normal operation events such as a power up across a wide range of process, voltage, and temperature variations.

[0046] FIG. 5 illustrates one embodiment of a process for handling an ESD event. In step 510 a selectable shunt is provided between a first node and a second node of a circuit. In step 520, the shunt is enabled with activation circuitry in response to an electrostatic discharge event on the first node. The shunt activation circuitry has a time constant τ=τ₁ for detecting the ESD event. In step 530, the time constant of the activation circuitry is configured to τ=τ₂ subsequent to enabling the shunt, wherein τ₂>τ₁. With respect to FIG. 1, the selectable shunt corresponds to shunt 160. The first and second nodes correspond to the VSUP and GND rails, respectively. The activation circuitry includes capacitor 110 and selectable load 120. The resistance component of the time constant is determined from the resistance of selectable load 120.

[0047] The rail clamps can be located within the integrated circuit in a manner such that a plurality of input/output cells share the same ESD protection circuit. The size of an individual rail clamp may be reduced if more than one clamp can be relied upon to provide ESD protection. In an effort to mitigate the effects of parasitic bus resistance, ESD rail clamps may be distributed locally in the input/output cells themselves. In this manner, several ESD rail clamps participate in the ESD event to provide robust protection. In this way, the effects of power and ground rail resistances may also be reduced in comparison with placing fewer, larger clamps in more centralized locations. In general, the sum total of parasitic power and ground rail resistances around the ESD discharge loop and constraints on maximum bond pad voltages establish limits on how far apart ESD rail clamps may be spaced in order to achieve a given level of ESD protection. In general, one skilled in the art is required to balance the tradeoff among ESD protection, resistance, and chip area.

[0048] FIG. 6 illustrates a cross-section of one embodiment of an integrated circuit package 610. A semiconductor die 630 is disposed within a carrier 620. Bond pads 632, 634 residing on the semiconductor die are used to electrically connect integrated circuitry fabricated on the die to conductive pins 632, 634. The pins enable communication of electrical signals between the integrated circuit and circuitry external to the integrated circuit package.

[0049] In order to protect the core circuitry of the integrated circuit from an ESD event occurring on a supply line, the ESD protection circuit such as illustrated in FIG. 1 is coupled to shunt ESD generated currents between the supply pin (e.g., VSUP 622) and the ground pin (e.g., GND 624) when the ESD event is detected.

[0050] In the preceding detailed description, the invention is described with reference to specific exemplary embodiments thereof. Various modifications and changes may be made thereto without departing from the broader scope of the invention as set forth in the claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.