US 8,629,432 B2Grant
Semiconductor device and manufacturing method thereof
Issue Date:2014-01-14
•17 Claims
•22 Drawing Sheets
Abstract
A semiconductor device including a thin film transistor which includes an oxide semiconductor layer and has high electric characteristics and reliability. Film deposition is performed using an oxide semiconductor target containing an insulator (an insulating oxide, an insulating nitride, silicon oxynitride, aluminum oxynitride, or the like), typically SiO2, so that the semiconductor device in which the Si-element concentration in the thickness direction of the oxide semiconductor layer has a gradient which increases in accordance with an increase in a distance from a gate electrode is realized.
Metadata
Assignee
- Semiconductor Energy Laboratory Co., Ltd.
Inventors
- Junichiro Sakata
- Takashi Shimazu
- Hiroki Ohara
- Toshinari Sasaki
- Shunpei Yamazaki
Application Information
Application Number:US 12/683,681
Filing Date:2010-01-07
Priority Date:2009-01-16
Art Unit:2896
Classifications
IPC:
H01L29/786H01L21/36
Patent Drawings (22 sheets)
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a semiconductor device including a circuit which includes a thin film transistor (hereinafter, referred to as TFT) and a manufacturing method thereof. For example, the present invention relates to an electronic appliance mounted with an electro-optic device typified by a liquid crystal display panel or a light-emitting display device including an organic light-emitting element as a component.
[0003] In this specification, a semiconductor device refers to all types of devices which can function by using semiconductor characteristics. An electro-optical device, a semiconductor circuit, and an electronic device are all included in the category of the semiconductor device.
[0004] 2. Description of the Related Art
[0005] There are a variety of kinds of metal oxides intended for many uses. Indium oxide is a well-known material and is used as a transparent electrode material necessary for a liquid crystal display or the like.
[0006] Some metal oxides have semiconductor characteristics. The metal oxides having semiconductor characteristics are one kind of compound semiconductor. The compound semiconductor is a semiconductor formed by two or more kinds of atoms bonded together. In general, metal oxides are insulators; however, it is known that metal oxides are semiconductors depending on the combination of elements included in the metal oxides.
[0007] For example, among metal oxides, tungsten oxide, tin oxide, indium oxide, zinc oxide, and the like are known as the metal oxides having semiconductor characteristics. The metal oxide as above has been used for a transparent semiconductor layer serving as a channel formation region in a thin film transistor (as disclosed in Patent Documents 1 to 4 and Non-Patent Document 1).
[0008] Examples of metal oxides include not only an oxide of a single metal element but also an oxide of a plurality of metal elements. For example, InGaO3(ZnO)m (m is a natural number) which is a homologous compound is a known material (Non-Patent Documents 2 to 4).
[0009] It has been confirmed that such an In—Ga—Zn based oxide as above is applicable to a channel layer of a thin film transistor (Patent Document 5 and Non-Patent Documents 5 and 6).
[0010] Further, attention has been drawn to a technique for manufacturing a thin film transistor using an oxide semiconductor and applying to an electronic device or an optical device. For example, Patent Document 6 and Patent Document 7 disclose a technique by which a thin film transistor is manufactured using zinc oxide or an In—Ga—Zn—O based oxide semiconductor as an oxide semiconductor film and such a transistor is used as a switching element or the like of an image display device.
REFERENCE
Patent Documents
[0011] [Patent Document 1] Japanese Published Patent Application No. S60-198861
[0012] [Patent Document 2] Japanese Published Patent Application No. H8-264794
[0013] [Patent Document 3] Japanese Translation of PCT International Application No. H11-505377
[0014] [Patent Document 4] Japanese Published Patent Application No. 2000-150900
[0015] [Patent Document 5] Japanese Published Patent Application No. 2004-103957
[0016] [Patent Document 6] Japanese Published Patent Application No. 2007-123861
[0017] [Patent Document 7] Japanese Published Patent Application No. 2007-096055
Non-Patent Document
[0018] [Non-Patent Document 1] M. W. Prins, K. O. Grosse-Holz, G. Muller, J. F. M. Cillessen, J. B. Giesbers, R. P. Weening, and R. M. Wolf, “A ferroelectric transparent thin-film transistor”, Appl. Phys. Lett., 17 Jun. 1996, Vol. 68 p. 3650-3652
[0019] [Non-Patent Document 2] M. Nakamura, N. Kimizuka, and T. Mohri, “The Phase Relations in the In2O3—Ga2ZnO4—ZnO System at 1350° C.”, J. Solid State Chem., 1991, Vol. 93, p. 298-315
[0020] [Non-Patent Document 3] N. Kimizuka, M. Isobe, and M. Nakamura, “Syntheses and Single-Crystal Data of Homologous Compounds, In2O3(ZnO)m (m=3, 4, and 5), InGaO3(ZnO)3, and Ga2O3(ZnO)m (m=7, 8, 9, and 16) in the In2O3—ZnGa2O4—ZnO System”, J. Solid State Chem., 1995, Vol. 116, p. 170-178
[0021] [Non-Patent Document 4] M. Nakamura, N. Kimizuka, T. Mohri, and M. Isobe, “Homologous Series, Synthesis and Crystal Structure of InFeO3(ZnO)m (m: natural number) and its Isostructural Compound”, KOTAI BUTSURI (SOLID STATE PHYSICS), 1993, Vol. 28, No. 5, p. 317-327
[0022] [Non-Patent Document 5] K. Nomura, H. Ohta, K. Ueda, T. Kamiya, M. Hirano, and H. Hosono, “Thin-film transistor fabricated in single-crystalline transparent oxide semiconductor”, SCIENCE, 2003, Vol. 300, p. 1269-1272
[0023] [Non-Patent Document 6] K. Nomura, H. Ohta, A. Takagi, T. Kamiya, M. Hirano, and H. Hosono, “Room-temperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors”, NATURE, 2004, Vol. 432 p. 488-492
[0024] An object of an embodiment of the present invention is to provide a semiconductor device including a thin film transistor which includes an oxide semiconductor layer and has high electric characteristics and reliability.
SUMMARY OF THE INVENTION
[0025] As an oxide semiconductor layer, a material containing at least zinc is used. Further, a zinc oxide is easy to be crystallized, and therefore, in order to realize an amorphous oxide semiconductor layer, film deposition is performed by using an oxide semiconductor target containing an insulator (e.g., an insulating oxide such as silicon oxide, germanium oxide, or aluminum oxide, an insulating nitride such as silicon nitride or aluminum nitride, or silicon oxynitride, aluminum oxynitride, or the like), typically SiO2 at from 0.1 wt % to 10 wt % inclusive, preferably at form 1 wt % to 6 wt % inclusive. SiOx (x>0) which hinders crystallization is contained in the oxide semiconductor layer, which enables improvement of the heat resistance, reduction of characteristic variation, or prevention of characteristic fluctuation with long-term use of a thin film transistor to be achieved.
[0026] Further, SiOx, which hinders crystallization, contained in the oxide semiconductor layer can suppress crystallization of the oxide semiconductor layer in the case where thermal treatment is performed after the deposition of the oxide semiconductor layer in the manufacturing process. Further, by employing an amorphous oxide semiconductor layer having a concentration gradient of SiOx, reduction of off current of a thin film transistor is achieved.
[0027] One embodiment of the present invention disclosed in this specification is a semiconductor device which includes a gate electrode over an insulating surface, an oxide semiconductor layer containing at least zinc and SiOx, and an insulating layer between the gate electrode and the oxide semiconductor layer, wherein the Si-element concentration in the film thickness direction of the oxide semiconductor layer has a gradient increasing step-by-step in accordance with an increase in the distance from the gate electrode.
[0028] The structure of the thin film transistor may be a bottom-gate structure in which an oxide semiconductor layer is disposed above a gate electrode provided over a substrate having an insulating surface and may be a bottom-contact type.
[0029] In the case where the oxide semiconductor layer is provided above the gate electrode, as for the concentration gradient of SiOx in the oxide semiconductor layer 103 containing SiOx, a higher concentration region is located on the side which is distant from the gate electrode and a lower concentration region is located on the side which is close to the gate electrode. The concentration gradient of SiOx in the oxide semiconductor layer 103 containing SiOx changes step-by-step or continuously.
[0030] The concentration gradient which changes step-by-step means that the Si-element concentration increases or decreases step-by-step in the film thickness direction. For example, when a graph in which the horizontal axis indicates the film thickness and the vertical axis indicates the Si-element concentration is formed, a line which connects a plurality of plotted points describes an upward-sloping or downward-sloping step-by-step line.
[0031] The concentration gradient which changes continuously means that the Si-element concentration changes gently in the film thickness direction. For example, when a graph in which the horizontal axis indicates the film thickness and the vertical axis indicates the Si-element concentration is formed, a line which connects a plurality of plotted points describes an upward-sloping or downward-sloping curve or straight line.
[0032] The oxide semiconductor layer is a single layer or a stacked layer of two or more layers. For example, a first oxide semiconductor layer having a fixed Si-element concentration and a second oxide semiconductor layer in which the Si-element concentration has a gradient changing continuously may be stacked. Alternatively, a first oxide semiconductor layer which does not contain a Si element and a second oxide semiconductor layer having a fixed Si-element concentration may be stacked; it can be regarded that this stacked layer shows a concentration gradient which changes step-by-step.
[0033] As one example of the oxide semiconductor layer, an In—Ga—Zn—O based oxide semiconductor can be given. The same or similar function as/to the above can be obtained by adding SiOx to any of the following: an In—Sn—Zn—O based oxide semiconductor, an In—Al—Zn—O based oxide semiconductor, a Sn—Ga—Zn—O based oxide semiconductor, an Al—Ga—Zn—O based oxide semiconductor, a Sn—Al—Zn—O based oxide semiconductor, an In—Zn—O based oxide semiconductor, a Sn—Zn—O based oxide semiconductor, an Al—Zn—O based oxide semiconductor, and a Zn—O based oxide semiconductor.
[0034] An embodiment of the present invention for the purpose of realizing the above structure is a method for manufacturing a semiconductor device including the steps of forming a gate electrode over an insulating surface, forming an insulating layer over the gate electrode, and forming an oxide semiconductor layer over the insulating layer, in which the Si-element concentration in the film thickness direction increases in accordance with an increase in the distance from the gate electrode, by a sputtering method with use of a first oxide semiconductor target and then by a sputtering method with use of a second oxide semiconductor target containing SiO2 at from 0.1 wt % to 10 wt % inclusive.
[0035] The structure of the thin film transistor of the present invention may be a top-gate structure in which an oxide semiconductor layer is disposed below a gate electrode provided over a substrate having an insulating surface. An embodiment of the present invention is a method for manufacturing a semiconductor device including the steps of forming an oxide semiconductor layer over an insulating surface, in which the Si-element concentration in the film thickness direction has a concentration gradient, by a sputtering method with use of a first oxide semiconductor target containing SiO2 at from 0.1 wt % to 10 wt % inclusive and then by a sputtering method with use of a second oxide semiconductor target, forming an insulating layer covering the oxide semiconductor layer, and forming a gate electrode over the insulating layer.
[0036] According to the present invention, a semiconductor device including a thin film transistor which includes an oxide semiconductor layer containing SiOx and has high electric characteristics and reliability.
BRIEF DESCRIPTION OF THE DRAWINGS
[0037] FIGS. 1A to 1C are cross-sectional views and a top view each illustrating an embodiment of the present invention.
[0038] FIGS. 2A to 2C are cross-sectional views and a top view each illustrating an embodiment of the present invention.
[0039] FIG. 3 is a cross-sectional view illustrating an embodiment of the present invention.
[0040] FIG. 4 is a top view illustrating an embodiment of the present invention.
[0041] FIGS. 5A and 5B are a cross-sectional view and a top view illustrating an embodiment of the present invention.
[0042] FIG. 6 is a top view illustrating an embodiment of the present invention.
[0043] FIG. 7 is a model diagram showing a single crystal structure of InGaZnO4.
[0044] FIG. 8 is a diagram showing a Si-substituted model.
[0045] FIG. 9 is a diagram showing a final structure of a single crystal model.
[0046] FIG. 10 is a diagram showing a final structure of a Si-substituted model.
[0047] FIG. 11 is a graph showing a radical distribution function g (r) of each model.
[0048] FIGS. 12A to 12E are cross-sectional views illustrating manufacturing steps of an embodiment of the present invention.
[0049] FIGS. 13A to 13C are cross-sectional views and a top view each illustrating an embodiment of the present invention.
[0050] FIGS. 14A and 14B are a cross-sectional view and a top view illustrating an embodiment of the present invention.
[0051] FIGS. 15A to 15C are cross-sectional views illustrating manufacturing steps of an embodiment of the present invention.
[0052] FIGS. 16A and 16B are a cross-sectional view and a top view illustrating an embodiment of the present invention.
[0053] FIGS. 17A and 17B are a cross-sectional view and a top view illustrating an embodiment of the present invention.
[0054] FIG. 18 is a diagram illustrating a pixel circuit.
[0055] FIGS. 19A to 19C are cross-sectional views each illustrating an embodiment of the present invention.
[0056] FIGS. 20A and 20B are a cross-sectional view and an external view illustrating an embodiment of the present invention.
[0057] FIGS. 21A and 21B are external views each illustrating an embodiment of the present invention.
[0058] FIGS. 22A and 22B are external views each illustrating an embodiment of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
[0059] Embodiments of the present invention will be hereinafter described in detail with reference to accompanying drawings. However, the present invention is not limited to the description below, and it is easily understood by those skilled in the art that modes and details disclosed herein can be modified in various ways without departing from the spirit and the scope of the present invention. Therefore, the present invention is not construed as being limited to description of the embodiments.
[Embodiment 1]
[0060] In Embodiment 1, an example of a thin film transistor including an oxide semiconductor layer containing SiOx will be described with reference to FIGS. 1A and 1B .
[0061] FIG. 1A illustrates a thin film transistor 190 which is one type of bottom-gate structure, and is a cross-sectional view of a structure called a channel-etch type. FIG. 1B illustrates an example of a top view of the thin film transistor whose cross section taken along line A1-A2 corresponds to FIG. 1A .
[0062] The thin film transistor 190 illustrated in FIG. 1A includes a gate electrode layer 101 over a substrate 100, a gate insulating layer 102 over the gate electrode layer 101, a stacked layer of oxide semiconductor layers over the gate insulating layer 102, and a source and drain electrode layers 105a and 105b over the stacked layer of the oxide semiconductor layers. In addition, a protective insulating layer 106 is provided, which covers the stacked layer of the oxide semiconductor layers and the source and drain electrode layers 105a and 105b.
[0063] The gate electrode layer 101 can be formed using a single layer or a stacked layer using any of the following: a metal material such as aluminum, copper, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, or scandium; an alloy material which contains any of these materials as a main component; and a nitride containing any of these materials. It is preferable to use a low-resistance conductive material such as aluminum or copper. However, such a low-resistance conductive material has the disadvantages of low heat resistance, being easily corroded, and the like; thus, it is preferably used in combination with a conductive material having heat resistance. As the conductive material having heat resistance, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, scandium, or the like is used.
[0064] For example, the stacked-layer structure of the gate electrode layer 101 is preferably a two-layer structure where a molybdenum layer is stacked over an aluminum layer, a two-layer structure where a molybdenum layer is stacked over a copper layer, a two-layer structure where a titanium nitride layer or a tantalum nitride layer is stacked over a copper layer, or a two-layer structure where a titanium nitride layer and a molybdenum layer are stacked. Alternatively, a three-layer structure where a tungsten layer or a tungsten nitride layer, an aluminum-silicon alloy layer or an aluminum-titanium alloy layer, and a titanium nitride layer or a titanium layer are stacked is preferable as well.
[0065] The gate insulating layer 102 is formed by a plasma CVD method or a sputtering method. The gate insulating layer 102 can be formed using a single layer or a stacked layer of any of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a silicon nitride oxide layer by a CVD method, a sputtering method, or the like. Alternatively, the gate insulating layer 102 can be formed using a silicon oxide layer by a CVD method using an organosilane gas.
[0066] Of the stacked layer of the oxide semiconductor layers, at least one layer of these is an oxide semiconductor layer containing SiOx; in this embodiment, a first oxide semiconductor layer 193, an oxide semiconductor layer 103 containing SiOx (also referred to as a second oxide semiconductor layer), and a third oxide semiconductor layer are stacked in this order. Note that the third oxide semiconductor layer is a semiconductor layer having higher electric conductivity than the oxide semiconductor layer 103 containing SiOx and functions as a buffer layer, an n+ layer, and/or a source and drain regions. In FIG. 1A , the third oxide semiconductor layer is illustrated as a first buffer layer 104a and a second buffer layer 104b.
[0067] As each oxide semiconductor layer, any of the following can be applied: an In—Ga—Zn—O based non-single-crystal film, an In—Sn—Zn—O based oxide semiconductor, an In—Al—Zn—O based oxide semiconductor, a Sn—Ga—Zn—O based oxide semiconductor, an Al—Ga—Zn—O based oxide semiconductor, a Sn—Al—Zn—O based oxide semiconductor, an In—Zn—O based oxide semiconductor, a Sn—Zn—O based oxide semiconductor, an Al—Zn—O based oxide semiconductor, an In—O based oxide semiconductor, a Sn—O based oxide semiconductor, and a Zn—O based oxide semiconductor.
[0068] In this embodiment, as the first oxide semiconductor layer 193, an In—Ga—Zn—O based non-single-crystal film obtained by a sputtering method using an oxide semiconductor target containing In (indium), Ga (gallium), and Zn (zinc) (In2O3:Ga2O3:ZnO=1:1:1) is used.
[0069] Further, as the oxide semiconductor layer 103 containing SiOx, a Zn—O based non-single-crystal film obtained by a sputtering method using an oxide semiconductor target containing SiO2 at 2 wt % is used.
[0070] In FIG. 1A , the boundary between the first oxide semiconductor layer 193 and the oxide semiconductor layer 103 containing SiOx is illustrated schematically. The boundary between oxide semiconductor layers may become indistinct depending on the materials thereof. By employing an oxide semiconductor layer containing SiOx, at least as one layer of the oxide semiconductor layers, electrical characteristics are made to be different between at least the oxide semiconductor layer on the gate insulating layer side, that is, the lower layer portion of the oxide semiconductor layers and the upper layer portion of the oxide semiconductor layers. Further, the Si-element concentration in the film thickness direction of the oxide semiconductor layers has a gradient increasing step-by-step in accordance with an increase in the distance from the gate electrode layer.
[0071] The third oxide semiconductor layer which is the first buffer layer 104a and the second buffer layer 104b can be obtained by changing the film deposition condition of the In—Ga—Zn—O based non-single-crystal semiconductor film used as the first oxide semiconductor layer. For example, the flow rate ratio of an oxygen gas in the film-deposition condition of an In—Ga—Zn—O based non-single-crystal film used as the third oxide semiconductor layer is set to be lower than that in the film-deposition condition of the In—Ga—Zn—O based non-single-crystal film used as the first oxide semiconductor layer. As the third oxide semiconductor layer, an In—Ga—Zn—O based non-single-crystal film containing nitrogen, that is, an In—Ga—Zn—O—N based non-single-crystal film (also referred to as an IGZON film) may be used. This In—Ga—Zn—O—N based non-single-crystal film can be obtained as follows: an oxynitride film containing indium, gallium, and zinc is formed by using a target containing an oxide containing indium, gallium, and zinc in an atmosphere containing a nitrogen gas; and the oxynitride film is subjected to thermal treatment. Alternatively, as the third oxide semiconductor layer, a Ga—Zn—O based non-single-crystal film containing nitrogen, that is, a Ga—Zn—O—N based non-single-crystal film (also referred to as an GZON film) may be used.
[0072] Further, an impurity element which imparts n-type conductivity may be contained in the third oxide semiconductor layer. As the impurity element, the following can be used: magnesium, aluminum, titanium, iron, tin, calcium, germanium, scandium, yttrium, zirconium, hafnium, boron, thallium, lead, or the like. Magnesium, aluminum, titanium, or the like contained in the buffer layer produces a blocking effect against oxygen or the like, so that the oxygen concentration of the oxide semiconductor layer can be kept within an optimal range by thermal treatment or the like after film deposition.
[0073] The source and drain electrode layers 105a and 105b are formed using any of an element selected from Al, Cr, Ta, Ti, Mo, and W, an alloy containing any of these elements, an alloy film containing a combination of any of these elements, and the like.
[0074] The protective insulating layer 106 can have a single layer structure or a stacked-layer structure using any of a silicon nitride film, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, an aluminum nitride film, an aluminum oxynitride film, a tantalum oxide film, and the like by a sputtering method or the like.
[0075] By employing the stacked-layer structure of the first oxide semiconductor layer 193 and the oxide semiconductor layer 103 containing SiOx, as an active layer of the thin film transistor 190 as shown in FIG. 1A , a main flow of drain current can be led to the first oxide semiconductor layer 193 when the thin film transistor 190 is in the ON state, so that the field-effect mobility can be increased. In addition, when the thin film transistor 190 is in the OFF state, drain current mainly flows through a portion of the oxide semiconductor layer 103 containing SiOx, which is subjected to etching treatment, so that off-current does not flow through the first oxide semiconductor layer 193 which has higher electric conductivity than the oxide semiconductor layer 103 containing SiOx, thereby decreasing off-current.
[0076] Respective materials of the first oxide semiconductor layer 193 and the oxide semiconductor layer 103 containing SiOx are not particularly limited: for example, the first oxide semiconductor layer 193 may be formed by a sputtering method using an oxide semiconductor target containing SiO2 at 2 wt % and the oxide semiconductor layer 103 containing SiOx may be formed by a sputtering method using an oxide semiconductor target containing SiO2 at 5 wt %. In that case also, the Si-element concentration in the film thickness direction has a gradient increasing step-by-step in accordance with an increase in the distance from the gate electrode layer.
[0077] Further, the present invention is not limited to the above-described structure including the first buffer layer 104a and the second buffer layer 104b; a structure in which a buffer layer is not provided may be employed. An example of a cross-sectional view of a thin film transistor 191 in that case is illustrated in FIG. 1C . Note that in FIG. 1C , the structure is the same as FIG. 1A , except in that a buffer layer is not provided, and therefore, the same reference numerals denote the same portions as the corresponding portions in FIG. 1A .
[Embodiment 2]
[0078] In Embodiment 2, an example of a thin film transistor including an oxide semiconductor layer containing an insulator such as an insulating oxide typified by silicon oxide, germanium oxide, or aluminum oxide, an insulating nitride typified by silicon nitride or aluminum nitride, or an insulating oxynitride typified by silicon oxynitride or aluminum oxynitride in minutes amount will be described with reference to FIGS. 2A and 2B .
[0079] FIG. 2A illustrates a thin film transistor 170 which is one type of bottom-gate structure, and is an example of a cross-sectional view of a structure called a channel-etch type. FIG. 2B is an example of a top view of the thin film transistor whose cross section taken along dotted line C1-C2 corresponds to FIG. 2A .
[0080] The thin film transistor 170 illustrated in FIG. 2A includes a gate electrode layer 101 over a substrate 100, a gate insulating layer 102 over the gate electrode layer 101, a stacked layer of oxide semiconductor layers over the gate insulating layer 102, a source and drain electrode layers 105a and 105b over the stacked layer of the oxide semiconductor layers, and a protective insulating layer 106 covering the stacked layer of the oxide semiconductor layers and the source and drain electrode layers 105a and 105b.
[0081] In this embodiment, over the gate insulating layer 102, an oxide semiconductor layer 103 containing SiOx as an insulating oxide (also referred to as a first oxide semiconductor layer) and a second oxide semiconductor layer are stacked in this order. Note that the second oxide semiconductor layer is a semiconductor layer having higher electric conductivity than the oxide semiconductor layer 103 containing an insulating oxide and functions as a buffer layer, an n+ layer, and/or a source and drain regions. In FIG. 2A , the second oxide semiconductor layer is illustrated as a first buffer layer 104a and a second buffer layer 104b.
[0082] In this embodiment, the oxide semiconductor layer 103 containing an insulating oxide is formed with use of an oxide semiconductor target containing In (indium), Ga (gallium), and Zn (zinc), in which SiO2 is contained at from 0.1 wt % to 10 wt % inclusive, preferably at from 1 wt % to 6 wt % inclusive. An insulating oxide contained in an oxide semiconductor makes an oxide semiconductor to be deposited easy to be amorphous. In addition, in the case where the oxide semiconductor film is subjected to thermal treatment, crystallization of the oxide semiconductor film can be suppressed.
[0083] Change in a structure of an oxide semiconductor containing In (indium), Ga (gallium), and Zn (zinc) which is so-called IGZO, by containing SiO2 therein, was calculated by the classical molecular dynamics simulation. In the classical molecular dynamics method, empirical potential characterizing interaction between atoms is defined, whereby force acting on each atom is evaluated, and Newton's equation of motion is numerically solved, whereby motion (time-dependent change) of each atom can be deterministically tracked.
[0084] Hereinafter, calculation models and calculation conditions are described. Note that in this calculation, the Born-Mayer-Huggins potential was used.
[0085] A single crystal structure of InGaZnO4 including 1680 atoms (see FIG. 7 ) and a structure of InGaZnO4 including 1680 atoms in which 20 atoms of each of In, Ga, and Zn are substituted by Si atoms (see FIG. 8 ) were formed. In the Si-substituted model, Si atoms are contained at 3.57 atoms % (2.34 wt %). The density of the single crystal model is 6.36 g/cm3, and the density of the Si-substituted model is 6.08 g/cm3.
[0086] At 1727° C. which is lower than the melting point of the InGaZnO4 single crystal (about 2000° C. according to estimation by the classical molecular dynamics simulation), structure relaxation was performed by the classical molecular dynamics simulation at a fixed pressure (1 atm) for 150 psec (time step width 0.2 fsec×750000 steps). The radial distribution functions g (r) of the two structures were calculated. Note that the radial distribution function g (r) is a function representing the probability density atoms existing at a distance of r from one atom. As the correlation between atoms disappears, g (r) becomes closer to 1.
[0087] FIG. 9 and FIG. 10 show final structures obtained by performing the classical molecular dynamics simulation for 150 psec on the above two calculation models of FIG. 7 and FIG. 8 . In addition, FIG. 11 shows the radial distribution function g (r) in each structure.
[0088] The single crystal model shown in FIG. 9 is stable and keeps the crystal structure in the final structure, whereas the Si-substituted model shown in FIG. 10 is unstable, and it can be observed that the crystal structure is distorted with time and changes into an amorphous structure. As seen in FIG. 11 , by comparing the radial distribution functions g (r) of the structural models, it is found that the single crystal model has peaks even at a long distance and the long-range order. On the other hand, it is found that in the Si-substituted model, the peak disappears at a distance of about 0.6 nm, and the Si-substituted model does not have the long-range order.
[0089] These calculation results indicate that in the case where SiO2 is contained, IGZO with an amorphous structure is more stable than that with a crystalline structure, and IGZO is easily to be amorphous by containing SiO2 in the IGZO. The IGZO thin film containing SiO2 immediately after deposition, which is practically obtained by a sputtering method, is an amorphous semiconductor film. Thus, according to these calculation results, SiO2 being contained can hinder crystallization even if thermal treatment is performed at high temperature, and can keep the amorphous structure.
[0090] Further, in the oxide semiconductor layer 103 containing SiOx, the Si-element concentration in the film thickness direction has a gradient increasing in accordance with an increase in the distance from the gate electrode layer. In the case of the thin film transistor 170 shown in FIG. 2A in which the oxide semiconductor layer is disposed above the gate electrode layer, as for the concentration gradient of SiOx in the oxide semiconductor layer 103 containing SiOx, a higher concentration region is located on the side which is distant from the gate electrode layer and a lower concentration region is located on the side which is close to the gate electrode layer. The concentration gradient of SiOx in the oxide semiconductor layer 103 containing SiOx changes step-by-step or continuously.
[0091] By employing the oxide semiconductor layer containing SiOx and having a concentration gradient, as an oxide semiconductor layer, a main flow of drain current can be led to the boundary vicinity between the oxide semiconductor layer 103 containing SiOx and the gate insulating layer 102 (low Si-element concentration region) when the thin film transistor 170 is in the ON state, so that the field-effect mobility can be increased. In addition, when the thin film transistor 170 is in the OFF state, drain current mainly flows through a portion of the oxide semiconductor layer 103 containing SiOx (high Si-element concentration region), which is subjected to etching treatment, so that off-current does not flow through the low Si-element concentration region which has higher electric conductivity than the high Si-element concentration region, thereby decreasing off-current.
[0092] The oxide semiconductor layer 103 containing SiOx is not limited to an In—Ga—Zn—O based oxide semiconductor, and for example, any of the following can be used: an In—Sn—Zn—O based oxide semiconductor, an In—Al—Zn—O based oxide semiconductor, a Sn—Ga—Zn—O based oxide semiconductor, an Al—Ga—Zn—O based oxide semiconductor, a Sn—Al—Zn—O based oxide semiconductor, an In—Zn—O based oxide semiconductor, a Sn—Zn—O based oxide semiconductor, an Al—Zn—O based oxide semiconductor, an In—O based oxide semiconductor, a Sn—O based oxide semiconductor, and a Zn—O based oxide semiconductor. The same or similar effect as/to the above can be obtained by employing the oxide semiconductor layer containing SiOx and having a concentration gradient, as the oxide semiconductor layer.
[0093] Further, the present invention is not limited to the above-described structure including the first buffer layer 104a and the second buffer layer 104b; a structure in which a buffer layer is not provided may be employed. An example of a cross-sectional view of a thin film transistor 171 in that case is illustrated in FIG. 2C . Note that in FIG. 2C , the structure is the same as FIG. 2A , except in that a buffer layer is not provided, and therefore, the same reference numerals denote the same portions as the corresponding portions in FIG. 2A .
[0094] Hereinafter, an example of manufacturing a display device using the above-described thin film transistor 170 as a switching element of a pixel portion is described.
[0095] First, a gate electrode layer 101 is provided over a substrate 100 having an insulating surface. A glass substrate is used as the substrate 100 having an insulating surface. The gate electrode layer 101 can be formed using a single layer or a stacked layer using any of a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium, and an alloy material which contains any of these materials as a main component. Note that when the gate electrode layer 101 is formed, a capacitor wiring 108 of the pixel portion and a first terminal 121 of a terminal portion are also formed.
[0096] For example, a stacked-layer structure of two layers of the gate electrode layer 101 is preferably a two-layer structure where a molybdenum layer is stacked over an aluminum layer, a two-layer structure where a molybdenum layer is stacked over a copper layer, a two-layer structure where a titanium nitride layer or a tantalum nitride layer is stacked over a copper layer, or a two-layer structure where a titanium nitride layer and a molybdenum layer are stacked. Alternatively, a stacked structure where a copper oxide layer including Ca which is to be a barrier layer is stacked over a copper layer including Ca, or a stacked structure where a copper oxide layer including Mg which is to be a barrier layer is stacked over a copper layer including Mg can be given. As a three-layer structure, a stacked-layer structure where a tungsten layer or a tungsten nitride layer, an alloy of aluminum and silicon or an alloy of aluminum and titanium, and a titanium nitride layer or a titanium layer are stacked is preferable.
[0097] Next, a gate insulating layer 102 covering the gate electrode layer 101 is formed. The gate insulating layer 102 is formed to have a thickness of 50 nm to 400 nm by a sputtering method, a PCVD method, or the like.
[0098] For example, as the gate insulating layer 102, a 100-nm-thick silicon oxide film is formed by a sputtering method. It is needless to say that the gate insulating layer 102 is not limited to such a silicon oxide film. The gate insulating layer 102 may be formed using a single layer or a stacked layer using another insulating film such as a silicon oxynitride film, a silicon nitride film, an aluminum oxide film, an aluminum nitride film, an aluminum oxynitride film, or a tantalum oxide film. In the case of having a stacked structure, for example, a silicon nitride film may be formed by a PCVD method, and a silicon oxide film may be formed by a sputtering film thereover. In the case where a silicon oxynitride film, a silicon nitride film, or the like is used as the gate insulating layer 102, an impurity from the glass substrate, sodium for example, can be blocked from diffusing into and entering an oxide semiconductor to be formed later above the gate insulating layer 102.
[0099] Next, an oxide semiconductor film containing SiOx is formed over the gate insulating layer 102. The oxide semiconductor film is formed with use of an oxide semiconductor target in which SiO2 is contained at from 0.1 wt % to 10 wt % inclusive, preferably at from 1 wt % to 6 wt % inclusive. Note that any other insulating impurity can be contained in the oxide semiconductor target, instead of SiO2, and any of the following can be used: an insulating oxide typified by germanium oxide or aluminum oxide, an insulating nitride typified by silicon nitride or aluminum nitride, an insulating oxynitride typified by silicon oxynitride or aluminum oxynitride, and the like. Such an insulating impurity contained in an oxide semiconductor makes an oxide semiconductor to be deposited easy to be amorphous. In addition, in the case where the oxide semiconductor film is subjected to thermal treatment, crystallization of the oxide semiconductor film can be suppressed.
[0100] In this embodiment, an oxide semiconductor film having a gradient of the Si-element concentration (a first In—Ga—Zn—O based non-single-crystal film) is formed as follows: two of an oxide semiconductor target containing In (indium), gallium (Ga), and Zn (zinc), in which SiO2 is contained at 2 wt % and an oxide semiconductor target containing In (indium), gallium (Ga), and Zn (zinc), in which SiO2 is contained at 5 wt % are disposed in the same chamber and changed by a shutter to be used, so that successive film deposition is performed in the same chamber.
[0101] An oxide semiconductor target containing In (indium), gallium (Ga), and Zn (zinc) can be deposited either of an RF sputtering method or a DC sputtering method. Therefore, two targets of an artificial quartz target and an oxide semiconductor target containing In (indium), gallium (Ga), and Zn (zinc) may be disposed in the same chamber and sputtered at the same time by an RF sputtering method, that is, so-called co-sputtering may be performed to form the oxide semiconductor film having a gradient of the Si-element concentration (the first In—Ga—Zn—O based non-single-crystal film). A silicon target may be used instead of the artificial quartz to perform co-sputtering. Co-sputtering enables an oxide semiconductor film containing SiOx to be formed without using an oxide semiconductor target containing SiO2.
[0102] Next, an oxide semiconductor film (a second In—Ga—Zn—O based non-single-crystal film) having lower resistance than the oxide semiconductor film containing SiOx is formed by a sputtering method. In this embodiment, sputtering is performed using a target of In2O3:Ga2O3:ZnO=1:1:1 under film deposition conditions where the pressure is 0.4 Pa, the power is 500 W, the deposition temperature is room temperature, and an argon gas is introduced at a flow rate of 40 sccm. Despite the use of the target in which In2O3:Ga2O3:ZnO=1:1:1, an In—Ga—Zn—O based non-single-crystal film including crystal grains each with a size of 1 to 10 nm immediately after the deposition may be formed. The presence, density, and diameter of crystal grains can be controlled by adjusting the deposition conditions of reactive sputtering as appropriate, such as the composition ratio of a target, the deposition pressure (0.1 Pa to 2.0 Pa), the power (250 W to 3000 W: 8 inches φ), or the temperature (room temperature to 100° C.). The diameter of each of the crystal grains can be controlled within a range of 1 to 10 nm The thickness of the second In—Ga—Zn—O based non-single-crystal film is set to 5 to 20 nm In the case where crystal grains are contained in the second In—Ga—Zn—O based non-single-crystal film, the size of each crystal grain does not exceed the film thickness. In this embodiment, the thickness of the second In—Ga—Zn—O based non-single-crystal film is 5 nm. The second In—Ga—Zn—O based non-single-crystal film is deposited in a rare gas (such as argon or helium) atmosphere (or an atmosphere containing oxygen at 10% or less and an argon gas at 90% or more).
[0103] Examples of a sputtering method include an RF sputtering method in which a high-frequency power source is used as a sputtering power source, a DC sputtering method, and a pulsed DC sputtering method in which a bias is applied in a pulsed manner.
[0104] In addition, there is a multi-source sputtering apparatus in which a plurality of targets of different materials can be set. With the multi-source sputtering apparatus, films of different materials can be deposited to be stacked in the same chamber, and a film of plural kinds of materials can be deposited by electric discharge at the same time in the same chamber.
[0105] In addition, there are a sputtering apparatus provided with a magnet system inside the chamber and used for a magnetron sputtering, and a sputtering apparatus used for an ECR sputtering in which plasma generated with the use of microwaves is used without using glow discharge.
[0106] Furthermore, as a deposition method by a sputtering method, there are also a reactive sputtering method in which a target substance and a sputtering gas component are chemically reacted with each other during deposition to form a thin compound film thereof, and a bias sputtering method in which a voltage is also applied to a substrate during deposition.
[0107] Next, a photolithography step is performed. A resist mask is formed, and the first In—Ga—Zn—O based non-single-crystal film and the second In—Ga—Zn—O based non-single-crystal film are etched.
[0108] Next, a photolithography step is performed. A resist mask is formed, and an unnecessary portion (part of the gate insulating layer) is removed by etching, so that a contact hole which reaches an electrode layer or a wiring formed of the same material as the gate electrode layer is formed. This contact hole is provided for direct contact with a conductive film formed later. For example, in the driver circuit portion, a contact hole is formed when a thin film transistor whose gate electrode layer is direct contact with the source or drain electrode layer or a terminal that is electrically connected to a gate wiring of a terminal portion is formed. Note that an example of forming the contact hole for direct connection with the conductive film to be formed later by the photolithography step is described in this embodiment, but there is no particular limitation. A contact hole reaching the gate electrode layer may be formed later in the same step as the step in which a contact hole for connection to a pixel electrode is formed, and electrical connection may be performed with use of the same material as the pixel electrode. When the electrical connection is performed with use of the same material as the pixel electrode, the number of masks can be reduced by one.
[0109] Next, a conductive film using a metal material is formed over the second In—Ga—Zn—O based non-single-crystal film by a sputtering method or a vacuum evaporation method.
[0110] As the material of the conductive film, there are an element selected from Al, Cr, Ta, Ti, Mo, and W, an alloy containing any of these elements, an alloy film containing a combination of any of these elements, and the like. Further, in the case of performing thermal treatment at 200° C. to 600° C., heat resistance against such thermal treatment is preferably provided for the conductive film. Since solo use of Al brings disadvantages such as low heat resistance and being easily corroded, aluminum is used in combination with a conductive material having heat resistance. As the conductive material having heat resistance which is used in combination with Al, any of the following materials may be used: an element selected from titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc), an alloy containing any of these above elements, an alloy film containing these elements in combination, and a nitride containing any of these above elements as a component.
[0111] In this embodiment, the conductive film has a single-layer structure of a titanium film. Alternatively, the conductive film may have a two-layer structure where a titanium film may be stacked over an aluminum film. Still alternatively, the conductive film may have a three-layer structure where a Ti film, a film of aluminum containing Nd (Al—Nd) is stacked over the Ti film, and a Ti film is formed over these films. The conductive film may have a single-layer structure of a film of aluminum containing silicon.
[0112] Next, a photolithography step is performed. A resist mask is formed, and unnecessary portions are removed by etching, so that the source and drain electrode layers 105a and 105b, and the first buffer layer 104a and the second buffer layer 104b which function as the source and drain regions are formed in the pixel portion and a source and drain electrode layers and a source and drain regions are formed in the driver circuit portion. An etching method at this time is wet etching or dry etching. For example, in the case where an aluminum film or an aluminum-alloy film is used as the conductive film, wet etching using a mixed solution of phosphoric acid, acetic acid, and nitric acid can be performed. In this embodiment, by wet-etching using an ammonia-hydrogen peroxide solution (hydrogen peroxide:ammonium:water=5:2:2), the conductive film that is a Ti film is etched, so that the source and drain electrode layers are formed, and the second In—Ga—Zn—O based non-single-crystal film is etched, so that the first buffer layer 104a and the second buffer layer 104b are formed. In this etching step, an exposed region of the oxide semiconductor film containing SiOx is also partly etched, so that the oxide semiconductor layer 103 containing SiOx is formed.
[0113] In addition, in this photolithography step, a second terminal 122 formed using the same material as the source and drain electrode layers 105a and 105b is left in the terminal portion. Note that the second terminal 122 is electrically connected to a source wiring (a source wiring including the source or drain electrode layer 105a or 105b).
[0114] Through the above steps, the thin film transistor 170 in which the oxide semiconductor layer 103 containing SiOx serves as a channel formation region can be formed in the pixel portion.
[0115] In addition, in the terminal portion, a connection electrode 120 is directly connected to the first terminal 121 of the terminal portion through a contact hole formed in the gate insulating film. Note that although not illustrated in this embodiment, a source or drain wiring of the thin film transistor of the driver circuit is directly connected to the gate electrode through the same steps as the above-described steps.
[0116] Next, thermal treatment (including photo-annealing) is performed at 200° C. to 600° C., typically, 300° C. to 500° C. In this embodiment, thermal treatment is performed in a nitrogen atmosphere in a furnace at 350° C. for one hour. Through this thermal treatment, atomic rearrangement occurs in the In—Ga—Zn—O based non-single-crystal film. In addition, the oxide semiconductor layer 103 containing SiOx can be prevented from being crystallized in thermal treatment, by SiOx being contained; thus the oxide semiconductor layer 103 can be kept to be amorphous. Further, SiOx contained in the oxide semiconductor layer 103 containing SiOx enables the oxide semiconductor layer 103 containing SiOx to be subjected to thermal treatment at relatively high temperature for a long period. Note that there is no particular limitation on when to perform the thermal treatment, as long as it is performed after the second In—Ga—Zn—O based non-single-crystal film is formed; for example, the thermal treatment may be performed after a pixel electrode is formed.
[0117] Next, the resist mask is removed, and the protective insulating layer 106 covering the thin film transistor 170 is formed.
[0118] Next, a photolithography step is performed. A resist mask is formed, and the protective insulating layer 106 is etched, so that a contact hole reaching the source or drain electrode layer 105a or 105b is formed. In addition, a contact hole reaching the second terminal 122 and a contact hole reaching the connection electrode 120 are also formed by this etching.
[0119] Next, the resist mask is removed, and then a transparent conductive film is formed. The transparent conductive film is formed using indium oxide (In2O3), indium tin oxide (In2O3—SnO2, abbreviated as ITO), or the like by a sputtering method, a vacuum evaporation method, or the like. Etching treatment of such a material is performed with a hydrochloric acid based solution. However, since a residue is easily generated particularly in etching ITO, indium oxide-zinc oxide alloy (In2O3—ZnO) may be used to improve etching processability.
[0120] Next, a photolithography step is performed. A resist mask is formed, and an unnecessary portion is removed by etching, so that a pixel electrode layer 110 is formed. In this photolithography step, a storage capacitor is formed by the capacitor wiring 108 and the pixel electrode layer 110 using the gate insulating layer 102 and the protective insulating layer 106 in the capacitor portion as a dielectric. Furthermore, in this photolithography step, the first terminal and the second terminal are covered with the resist mask so that transparent conductive films 128 and 129 remain in the terminal portion. The transparent conductive films 128 and 129 serve as electrodes or wirings that are used for connection with an FPC. The transparent conductive film 128 formed over the connection electrode 120 that is directly connected to the first terminal 121 serves as a terminal electrode for connection which functions as an input terminal for the gate wiring. The transparent conductive film 129 formed over the second terminal 122 serves as a terminal electrode for connection which functions as an input terminal for the source wiring.
[0121] Described in this embodiment is an example in which the storage capacitor is formed by the capacitor wiring 108 and the pixel electrode layer 110 by using the gate insulating layer 102 and the protective insulating layer 106 as a dielectric is described; however, there is no particular limitation. A structure may also be employed, in which an electrode formed using the same material as the source and drain electrodes is provided above a capacitor wiring and a storage capacitor is formed by the electrode and the capacitor wiring with the gate insulating layer 102 interposed therebetween as a dielectric, and the electrode and the pixel electrode layer 110 are electrically connected.
[0122] Next, the resist mask is removed. FIG. 3 is a cross-sectional view at this stage. Note that, a top view of the thin film transistor 170 in the pixel portion at this stage corresponds to FIG. 4 .
[0123] A cross-sectional view taken along line A1-A2 and line B1-B2 of FIG. 4 corresponds to FIG. 3 . FIG. 3 illustrates a cross-sectional structure of the thin film transistor 170 in the pixel portion, a cross-sectional structure of a capacitor portion in the pixel portion, and a cross-sectional structure of the terminal portion.
[0124] Further, FIGS. 5A and 5B are a cross-sectional view of a source wiring terminal portion and a top view thereof, respectively. FIG. 5A is a cross-sectional view taken along line D1-D2 of FIG. 5B . In FIG. 5A , a transparent conductive film 155 formed over a protective insulating film 106 is a connection terminal electrode which functions as an input terminal. Furthermore, in FIG. 5A , in the terminal portion, an electrode 156 formed using the same material as the gate wiring is located below and overlapped with a second terminal 150, which is electrically connected to the source wiring, with a gate insulating layer 152 interposed therebetween. The electrode 156 is not electrically connected to the second terminal 150. When the electrode 156 is set to, for example, floating state, GND, or 0 V such that the potential of the electrode 156 is different from the potential of the second terminal 150, a capacitor for preventing noise or static electricity can be formed. The second terminal 150 is electrically connected to the transparent conductive film 155 with the protective insulating film 106 interposed therebetween.
[0125] A plurality of gate wirings, source wirings, and capacitor wirings are provided depending on the pixel density. Also in the terminal portion, the first terminal at the same potential as the gate wiring, the second terminal at the same potential as the source wiring, the third terminal at the same potential as the capacitor wiring, and the like are each arranged in plurality. There is no particular limitation on the number of each of the terminals, and the number of the terminals can be determined as appropriate.
[0126] Thus, the pixel portion which includes the thin film transistor 170 including an oxide semiconductor layer containing SiOx and the storage capacitor, and the terminal portion can be manufactured. In addition, a driver circuit can be formed over the same substrate.
[0127] When an active matrix liquid crystal display device is manufactured, an active matrix substrate and a counter substrate provided with a counter electrode are bonded to each other with a liquid crystal layer interposed therebetween. Note that a common electrode is provided over the active matrix substrate to be electrically connected to the counter electrode provided on the counter substrate, and a terminal is provided in a terminal portion to be electrically connected to the common electrode. This terminal is provided for setting the common electrode at a fixed potential such as GND or 0 V.
[0128] Further, in this embodiment, the pixel structure is not limited to that of FIG. 4 . An example of a top view different from FIG. 4 is illustrated in FIG. 6 . FIG. 6 illustrates an example in which a capacitor wiring is not provided but a pixel electrode overlaps with a gate wiring of an adjacent pixel, with a protective insulating film and a gate insulating layer interposed therebetween to form a storage capacitor. In that case, a capacitor wiring and a third terminal which is connected to the capacitor wiring can be omitted. Note that in FIG. 6 , the same portions as portions in FIG. 4 are denoted by the same reference numerals.
[0129] In an active matrix liquid crystal display device, display patterns are formed on a screen by driving pixel electrodes arranged in a matrix. In more detail, when voltage is applied between a selected pixel electrode and a counter electrode that corresponds to the selected pixel electrode, a liquid crystal layer provided between the pixel electrode and the counter electrode is optically modulated, and this optical modulation is recognized as a display pattern.
[0130] In displaying moving images, a liquid crystal display device has a problem that a long response time of liquid crystal molecules themselves causes afterimages or blurring of moving images. In order to improve the moving-image characteristics of the liquid crystal display device, a driving method called black insertion is employed in which color black is displayed on the whole screen every other frame period.
[0131] Moreover, a driving method called double-frame rate driving may be employed in which the vertical synchronizing frequency is 1.5 times or more, preferably twice or more as high as a conventional vertical synchronizing frequency, whereby the moving-image characteristics are improved.
[0132] Further alternatively, in order to improve the moving-image characteristics of a liquid crystal display device, a driving method may be employed in which a plurality of LEDs (light-emitting diodes) or a plurality of EL light sources are used to form a surface light source as a backlight, and each light source of the surface light source is independently driven in a pulsed manner in one frame period. As the surface light source, three or more kinds of LEDs may be used and an LED emitting white light may be used. Since a plurality of LEDs can be controlled independently, the light emission timing of LEDs can be synchronized with the timing at which a liquid crystal layer is optically modulated. According to this driving method, LEDs can be partly turned off; therefore, an effect of reducing power consumption can be obtained particularly in the case of displaying an image having a large part on which black is displayed.
[0133] By combining these driving methods, the display characteristics of a liquid crystal display device, such as moving-image characteristics, can be improved as compared to those of conventional liquid crystal display devices.
[0134] According to this embodiment, a display device having high electrical characteristics and high reliability can be provided at low costs.
[0135] This embodiment can be combined with Embodiment 1 as appropriate.
[Embodiment 3]
[0136] In Embodiment 3, an example in which light exposure using a multi-tone mask is performed so that the number of masks is decreased will be described.
[0137] In addition, described is an example in which indium that is a rare metal the amount of production of which is limited is not used in the composition of an oxide semiconductor layer. In addition, described is an example in which gallium that is one kind of rare metal is also not used as a compositional element of an oxide semiconductor layer.
[0138] A multi-tone (high-tone) mask can achieve three levels of light exposure: an exposed portion, a half-exposed portion, and an unexposed portion. Light has a plurality of intensity levels by passing through the multi-tone mask. One-time light exposure and development process enables a resist mask with regions with a plurality of thicknesses (typically, two levels of thickness) to be formed. Accordingly, by using a multi-tone mask, the number of light-exposure masks can be reduced.
[0139] As typical examples of a multi-tone mask, there are a gray-tone mask, a half-tone mask, and the like.
[0140] A gray-tone mask includes a light-transmitting substrate, and a light-shielding portion and a diffraction grating which are formed over the light-transmitting substrate. The light transmittance of the light-shielding portion is 0%. On the other hand, the light transmittance of the diffraction grating can be controlled by setting an interval between light-transmitting portions in slit forms, dot forms, or mesh forms to an interval less than or equal to the resolution limit of light used for the exposure. Note that the diffraction grating can be either in a regular slit form, a regular dot form, or a regular mesh form, or in an irregular slit form, an irregular dot form, or an irregular mesh form.
[0141] A half-tone mask includes a light-transmitting substrate, and a semi-transmissive portion and a light-shielding portion which are formed over the light-transmitting substrate. The semi-transmissive portion can be formed using MoSiN, MoSi, MoSiO, MoSiON, CrSi, or the like. The light-shielding portion can be formed using a light-shielding material which absorbs light, such as chromium or chromium oxide. When the half-tone mask is irradiated with light for exposure, the light transmittance of the light-shielding portion is 0% and the light transmittance of a region where neither the light-shielding portion nor the semi-transmissive portion is provided is 100%. The light transmittance of the semi-transmissive portion can be controlled in the range of 10% to 70%. The light transmittance of the semi-transmissive portion can be controlled by the material of the semi-transmissive portion.
[0142] FIGS. 12A to 12E correspond to cross-sectional views illustrating steps for manufacturing a thin film transistor 360.
[0143] In FIG. 12A , an insulating film 357 is provided over a substrate 350 and a gate electrode layer 351 is provided over the insulating film 357. In this embodiment, a silicon oxide film (with a thickness of 100 nm) is used as the insulating film 357. Over the gate electrode layer 351, a gate insulating layer 352, an oxide semiconductor film 380, an oxide semiconductor film 381 containing SiOx, and a conductive film 383 are stacked in this order. In this embodiment, an oxide semiconductor containing neither of indium and gallium, typically a Sn—Zn—O based oxide semiconductor, an Al—Zn—O based oxide semiconductor, a Sn—Al—Zn—O based oxide semiconductor, and/or a Zn—O based oxide semiconductor are/is used as the oxide semiconductor film 380 and the oxide semiconductor film 381 containing SiOx. In this embodiment, a Sn—Zn—O based oxide semiconductor formed by a sputtering method is used as the oxide semiconductor film 380, and a Sn—Zn—O based oxide semiconductor is used as the oxide semiconductor film 381 containing SiOx.
[0144] A mask 384 is formed over the gate insulating layer 352, the oxide semiconductor film 380, the oxide semiconductor film 381 containing SiOx, and the conductive film 383.
[0145] In Embodiment 3, an example is described in which light exposure using a multi-tone (multi-tone) mask is performed to form the mask 384.
[0146] The light exposure is performed using the multi-tone mask through which light has a plurality of intensity levels, and then development is performed, whereby the mask 384 having regions with different levels of thickness can be formed as shown in FIG. 12B . The number of light-exposure masks can be reduced by using a multi-tone mask.
[0147] Next, a first etching step is performed using the mask 384 to etch the oxide semiconductor film 380, the oxide semiconductor film 381 containing SiOx, and the conductive film 383 into an island shape. Accordingly, a patterned oxide semiconductor layer 390, a patterned oxide semiconductor layer 385 containing SiOx, and a patterned conductive layer 387 can be formed (see FIG. 12B ).
[0148] Next, ashing is conducted on the mask 384. As a result, the area and thickness of the mask are reduced. At this time, the resist of the mask in a region with a small thickness (a region overlapping with part of the gate electrode layer 351) is removed, and divided masks 388 can be formed (see FIG. 12C ).
[0149] A second etching step is performed using the masks 388 to etch the oxide semiconductor layer 385 containing SiOx and the conductive layer 387, so that a semiconductor layer 353 containing SiOx and a source and drain electrode layers 355a and 355b are formed (see FIG. 12D ). Note that the semiconductor layer 353 containing SiOx is partly etched to become a semiconductor layer having a groove (depression) and also having an end portion which is partly etched and exposed to outside.
[0150] When the first etching step is performed on the oxide semiconductor film 381 containing SiOx and the conductive film 383 by dry-etching, the oxide semiconductor film 381 containing SiOx and the conductive film 383 are etched anisotropically, which makes the end portions of the masks 384 and the end portions of the oxide semiconductor layer 385 containing SiOx and the conductive layer 387 to be aligned with each other so as to become continuous.
[0151] Similarly, when the second etching step is performed on the oxide semiconductor layer 385 containing SiOx and the conductive layer 387 by dry-etching, the oxide semiconductor layer 385 containing SiOx and the conductive layer 387 are etched anisotropically, which makes the end portions of the masks 388, one of the end portion of the depression and the end portion in the etched region of the oxide semiconductor layer 353 containing SiOx, and the end portion of one of the source and drain electrode layers 355a and 355b to be aligned with each other so as to become continuous.
[0152] Shown in Embodiment 3 is the case where the semiconductor layer 353 containing SiOx and the source and drain electrode layers 355a and 355b have the same tapered angle at the respective end portions and are stacked so that the end portions are continuous. However, since the etching rates thereof are different depending on the etching condition and the materials of the oxide semiconductor layer and the conductive layer, the tapered angles may be different and the end portions is not necessarily continuous.
[0153] After that, the masks 388 are removed.
[0154] Next, heating is performed at 200° C. to 600° C. in an atmosphere containing oxygen is performed (see FIG. 12E ).
[0155] Through the above process, the channel etch type thin film transistor 360 in which the semiconductor layer 353 containing SiOx is stacked over the oxide semiconductor layer 390 can be manufactured.
[0156] The use of a resist mask having regions with a plurality of thicknesses (typically, two levels of thickness) formed using a multi-tone mask as in this embodiment enables the number of resist masks to be reduced, which leads to simplification of the manufacturing process and cost reduction.
[0157] Further, indium and gallium are not used in the oxide semiconductor layer as described in Embodiment 3, thereby reducing the cost for a target of an oxide semiconductor, which leads to cost reduction.
[0158] Accordingly, a semiconductor device can be manufactured at low cost with high productivity.
[0159] Described in Embodiment 3 is an example in which a thin film transistor in a driver circuit and a thin film transistor in a pixel portion are both the inverted staggered thin film transistors 360 each having a stacked-layer structure in which the semiconductor layer 353 containing SiOx is stacked over the oxide semiconductor layer 390. That is, this embodiment is an example in which respective structures of thin film transistors in a driver circuit and in a pixel portion in the case where the circuits are formed over the same substrate are the same or substantially the same as each other.
[0160] This embodiment can be combined with the structure described in any other Embodiment, as appropriate.
[0161] For example, although the example of the stacked-layer structure in which a Sn—Zn—O based oxide semiconductor formed by a sputtering method is used as the oxide semiconductor film 380 and a Sn—Zn—O based oxide semiconductor is used as the oxide semiconductor film 381 containing SiOx is described in Embodiment 3, the present invention is not limited thereto; a single-layer structure as described in Embodiment 2 may be employed and for example, a thin film transistor using a Sn—Zn—O based oxide semiconductor containing SiOx may be manufactured.
[Embodiment 4]
[0162] In Embodiment 4, an example of a channel stop type thin film transistor 430 will be described using FIGS. 13A and 13B . FIG. 13B is an example of a top view of a thin film transistor, cross-sectional view along dotted line Z1-Z2 of which corresponds to FIG. 13A . Described is an example in which an oxide semiconductor material containing no indium is used in an oxide semiconductor layer in the thin film transistor 430.
[0163] In FIG. 13A , a gate electrode 401 is provided over a substrate 400. Then, over a gate insulating layer 402 covering the gate electrode 401, a first oxide semiconductor layer 403 and a second oxide semiconductor layer 405 are provided.
[0164] In this embodiment, a Ga—Zn—O based oxide semiconductor formed by a sputtering method is used as the first oxide semiconductor layer 403, and a Sn—Zn—O based oxide semiconductor containing SiOx is used as the second oxide semiconductor layer 405. In this embodiment, an oxide semiconductor containing no indium, typically a Sn—Ga—Zn—O based oxide semiconductor, an Al—Ga—Zn—O based oxide semiconductor, a Sn—Al—Zn—O based oxide semiconductor, a Sn—Zn—O based oxide semiconductor, an Al—Zn—O based oxide semiconductor, and/or a Zn—O based oxide semiconductor are/is used as the first oxide semiconductor layer 403 and the second oxide semiconductor layer 405.
[0165] Next, a channel protective layer 418 is provided on and in contact with the second oxide semiconductor layer 405. The channel protective layer 418 is provided, whereby damage to a channel formation region of the second oxide semiconductor layer 405, which is caused in the manufacturing process (reduction in film thickness due to plasma or etchant in etching, oxidation, etc.), can be prevented. Accordingly, the reliability of the thin film transistor 430 can be improved.
[0166] The channel protective layer 418 can be formed using an inorganic material (such as silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide). As a manufacturing method of the channel protective layer 418, a vapor phase growth method such as a plasma CVD method or a thermal CVD method, or a sputtering method can be used. The shape of the channel protective layer 418 is processed after the film deposition. In this embodiment, a silicon oxide film is deposited by a sputtering method and processed by etching using a mask formed by photolithography, so that the channel protective layer 418 is formed.
[0167] Next, n+ layers 406a and 406b are formed over the channel protective layer 418 and the second oxide semiconductor layer 405. In this embodiment, the n+ layers 406a and 406b serving as a source and drain regions are Ga—Zn—O based non-single-crystal films, which are formed under deposition conditions different from the deposition conditions of the first oxide semiconductor layer 403 and the second oxide semiconductor layer 405, and are oxide semiconductor layers having lower resistance. The n+ layers 406a and 406b may be formed using a Ga—Zn—O based non-single-crystal film containing nitrogen, that is, a Ga—Zn—O—N based non-single-crystal film (also called a GZON film).
[0168] Next, a first wiring 409 and a second wiring 410 are formed over the n+ layer 406a and the n+ layer 406b, respectively. The first wiring 409 and the second wiring 410 are each formed using an element selected from Al, Cr, Ta, Ti, Mo, and W, an alloy containing any of these elements as its component, an alloy film containing a combination of any of these elements, or the like.
[0169] By the provision of the n+ layers 406a and 406b, the first wiring 409 and the second wiring 410 which are metal layers can have a good junction with the second oxide semiconductor layer 405, so that stable operation can be realized in terms of heat in comparison with a Schottky junction. In addition, it is effective that the n+ layer is provided in order that carriers of a channel are supplied (on the source side), that carriers of a channel are absorbed stably (on the drain side), or that a resistive component is not produced in an interface between a wiring and an oxide semiconductor layer. Moreover, resistance is reduced, thereby ensuring high mobility even with a high drain voltage.
[0170] Further, the present invention is not limited to the above-described structure including the n+ layers 406a and 406b; a structure in which an n+ layer is not provided may be employed. An example of a cross-sectional view of a thin film transistor 191 in that case is illustrated in FIG. 13C . Note that in FIG. 13C , the structure is the same as FIG. 13A , except in that an n+ layer is not provided, and therefore, the same reference numerals denote the same portions as the corresponding portions in FIG. 13A .
[0171] Next, it is preferable to perform thermal treatment at 200° C. to 600° C., typically, 300° C. to 500° C. In this embodiment, thermal treatment is performed in a furnace at 350° C. for one hour in an air atmosphere. By this thermal treatment, atomic rearrangement of the first oxide semiconductor layer 403 and the second oxide semiconductor layer 405 is performed. This thermal treatment releases strain energy which inhibits carrier travel, and therefore, the thermal treatment (including photo-annealing) is important. In addition, crystallization of the second oxide semiconductor layer 405 is inhibited by SiOx contained in the second oxide semiconductor layer 405 in the thermal treatment, whereby large part of the second oxide semiconductor layer 405 can be kept to be amorphous. There is no particular limitation on when to perform the thermal treatment as long as it is performed after the formation of the second oxide semiconductor layer 405; for example, it may be performed after the formation of a pixel electrode.
[0172] Further, indium is not used in the oxide semiconductor layer as is in this embodiment, which leads to no use of indium that might be depleted as a material.
[0173] This embodiment can be combined with the structure described in any other Embodiment, as appropriate.
[0174] For example, although the example of the stacked-layer structure in which a Ga—Zn—O based oxide semiconductor formed by a sputtering method is used as the first oxide semiconductor layer 403 and a Sn—Zn—O based oxide semiconductor containing SiOx is used as the second oxide semiconductor layer 405 is described in Embodiment 4, the present invention is not limited thereto; a single-layer structure as described in Embodiment 2 may be employed and for example, a thin film transistor using a Sn—Zn—O based oxide semiconductor containing SiOx may be manufactured.
[Embodiment 5]
[0175] In Embodiment 5, an example in which an inverter circuit is formed using two n-channel thin film transistors 760 and 761 will be described. Described in Embodiment 5 is an example in which gallium is not contained in each oxide semiconductor layer of the thin film transistors 760 and 761.
[0176] A driver circuit for driving a pixel portion is formed using an inverter circuit, a capacitor, a resistor, and the like. When two n-channel TFTs are combined to form an inverter circuit, there are two types of combinations: a combination of an enhancement type transistor and a depletion type transistor (hereinafter, a circuit formed by such a combination is referred to as an “EDMOS circuit”) and a combination of enhancement type TFTs (hereinafter, a circuit formed by such a combination is referred to as an “EEMOS circuit”). Note that when the threshold voltage of the n-channel TFT is positive, the n-channel TFT is defined as an enhancement type transistor, while when the threshold voltage of the n-channel TFT is negative, the n-channel TFT is defined as a depletion type transistor; this definition is applied throughout the specification.
[0177] The pixel portion and the driver circuit are formed over the same substrate. In the pixel portion, on/off of voltage application to a pixel electrode is switched using enhancement type transistors arranged in a matrix.
[0178] FIG. 14A illustrates a cross-sectional structure of the inverter circuit of the driver circuit. In FIG. 14A , a first gate electrode 741 and a second gate electrode 742 are provided over a substrate 740. The first gate electrode 741 and the second gate electrode 742 each can be formed to have a single-layer or stacked-layer structure using any of a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium, and an alloy material which includes any of these materials as a main component.
[0179] Further, a first wiring 749, a second wiring 750, and a third wiring 751 are provided over a gate insulating layer 743 that covers the first gate electrode 741 and the second gate electrode 742. The second wiring 750 is directly connected to the second gate electrode 742 through a contact hole 744 formed in the gate insulating layer 743.
[0180] Further, an n+ layer 755a is formed over the first wiring 749, n+ layers 755b and 756a are formed over the second wiring 750, and an n+ layer 756b is formed over the third wiring 751. In this embodiment, the n+ layers 755a, 755b, 756a, and 756b each of which serves as a source region or a drain region are Ga—Zn—O based non-single-crystal films. The n+ layers 755a, 755b, 756a, and 756b may be formed using a Ga—Zn—O based non-single-crystal film containing nitrogen, that is, a Ga—Zn—O—N based non-single-crystal film (also called a GZON film).
[0181] Further, a first oxide semiconductor layer 748 and a second oxide semiconductor layer 745 containing SiOx are provided in a position which overlaps with the first gate electrode 741 so as to interpose the n+ layer 755a between the first wiring 749 and the first and second oxide semiconductor layers 748 and 745 and so as to interpose the n+ layer 755b between the second wiring 750 and the first and second oxide semiconductor layers 748 and 745. Similarly, a third oxide semiconductor layer 746 and a fourth oxide semiconductor layer 747 containing SiOx are provided in a position which overlaps with the second gate electrode 742 so as to interpose the n+ layer 756a between the second wiring 750 and the third and fourth oxide semiconductor layers 746 and 747 and so as to interpose the n+ layer 756b between the third wiring 751 and the third and fourth oxide semiconductor layers 746 and 747.
[0182] In this embodiment, an In—Zn—O based oxide semiconductor formed by a sputtering method is used as the first oxide semiconductor layer 748 and the third oxide semiconductor layer 746. A Sn—Zn—O based oxide semiconductor containing SiOx is used as the second oxide semiconductor layer 745 and the fourth oxide semiconductor layer 747. In this embodiment, an oxide semiconductor containing no gallium, typically an In—Sn—Zn—O based oxide semiconductor, an In—Al—Zn—O based oxide semiconductor, a Sn—Al—Zn—O based oxide semiconductor, an In—Zn—O based oxide semiconductor, a Sn—Zn—O based oxide semiconductor, an Al—Zn—O based oxide semiconductor, and/or a Zn—O based oxide semiconductor are/is used as the first oxide semiconductor layer 748, the second oxide semiconductor layer 745, the third oxide semiconductor layer 746, and the fourth oxide semiconductor layer 747.
[0183] The thin film transistor 760 includes the first gate electrode 741, the first oxide semiconductor layer 748 which overlaps with the first gate electrode 741 with the gate insulating layer 743 interposed therebetween, and the second oxide semiconductor layer 745 containing SiOx, and the first wiring 749 is a power supply line at a ground potential (a ground power supply line). This power supply line at a ground potential may be a power supply line to which a negative voltage VDL is applied (a negative power supply line).
[0184] In addition, the thin film transistor 761 includes the second gate electrode 742, the third oxide semiconductor layer 746 which overlaps with the second gate electrode 742 with the gate insulating layer 743 interposed therebetween, and the fourth oxide semiconductor layer 747 containing SiOx and the third wiring 751 is a power supply line to which a positive voltage VDD is applied (a positive power supply line).
[0185] As shown in FIG. 14A , the second wiring 750 which is electrically connected to both the first oxide semiconductor layer 748 and the third oxide semiconductor layer 746 is directly connected to the second gate electrode 742 of the thin film transistor 761 through a contact hole 744 formed in the gate insulating layer 743. Direct connection between the second wiring 750 and the second gate electrode 742 can provide good contact and reduce the contact resistance. In comparison with the case where the second gate electrode 742 and the second wiring 750 are connected to each other with an conductive film, e.g., a transparent conductive film, interposed therebetween, a reduction in the number of contact holes and a reduction in an area occupied by the driver circuit in accordance with the reduction in the number of contact holes can be achieved.
[0186] A top view of the inverter circuit of the driver circuit is illustrated in FIG. 14B . A cross section taken along dotted-line Y1-Y2 in FIG. 14B corresponds to FIG. 14A .
[0187] Further, an example of a manufacturing process of an inverter circuit using thin film transistors 762 and 763 each of which does not include an n+ layer is illustrated in FIGS. 15A to 15C .
[0188] A first conductive film is formed over a substrate 740 by a sputtering method and is selectively etched using a first photomask to form a first gate electrode 741 and a second gate electrode 742. Next, a gate insulating layer 743 for covering the first gate electrode 741 and the second gate electrode 742 is formed by a plasma CVD method or a sputtering method. The gate insulating layer 743 can be formed to have a single-layer or a stacked-layer structure using any of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a silicon nitride oxide layer by a CVD method, a sputtering method, or the like. The gate insulating layer 743 can be formed using a silicon oxide layer by a CVD method using an organosilane gas.
[0189] Next, the gate insulating layer 743 is selectively etched using a second photomask to form a contact hole 744 which reaches the second gate electrode 742. A cross-sectional view at this stage corresponds to FIG. 15A .
[0190] Next, a second conductive film is deposited by a sputtering method and is selectively etched using a third photomask to form a first wiring 749, a second wiring 750, and a third wiring 751. The third wiring 751 is directly in contact with the second gate electrode 742 through the contact hole 744.
[0191] Next, a first oxide semiconductor film and a second oxide semiconductor film containing SiOx are deposited to be stacked by a sputtering method. It is preferable that, before the deposition of the first oxide semiconductor film by a sputtering method, dust attached to a surface of the gate insulating layer 743 and a bottom surface of the contact hole 744 is removed by reverse sputtering in which an argon gas is introduced and plasma is generated. Reverse sputtering refers to a method in which, without application of a voltage to a target side, an RF power source is used for application of a voltage to a substrate side in an argon atmosphere to change the quality of a surface. Note that instead of an argon atmosphere, nitrogen, helium, or the like may be used. An argon atmosphere to which oxygen, hydrogen, N2O, or the like is added may be used as well. Further, an argon atmosphere to which Cl2, CF4, or the like is added may be used as well.
[0192] Next, the first oxide semiconductor film and the second oxide semiconductor film containing SiOx are selectively etched using a fourth photomask. By this etching, a stack of a first oxide semiconductor layer 748 and a second oxide semiconductor layer 745 containing SiOx is formed over the first gate electrode 741, and a stack of a third oxide semiconductor layer 746 and a fourth oxide semiconductor layer 747 containing SiOx is formed over the second gate electrode 742.
[0193] Next, a protective layer 752 is formed and is selectively etched using a fifth photomask to form a contact hole. After that, a third conductive film is formed. Finally, the third conductive film is selectively etched using a sixth photomask to form a connection wiring 753 which is electrically connected to the second wiring 750. A cross-sectional view at this stage corresponds to FIG. 15C .
[0194] The protective layer 752 can be formed using an inorganic material (such as silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide). The protective layer 752 can be formed by a vapor phase growth method such as a plasma CVD method or a thermal CVD method, or a sputtering method.
[0195] Next, it is preferable to perform thermal treatment at 200° C. to 600° C., typically, 300° C. to 500° C. In this embodiment, thermal treatment is performed in a furnace at 350° C. for one hour in an air atmosphere. By this thermal treatment, atomic rearrangement of the first oxide semiconductor layer 748, the second oxide semiconductor layer 745, the third oxide semiconductor layer 746, and the fourth oxide semiconductor layer 747 is performed. This thermal treatment releases strain energy which inhibits carrier travel, and therefore, the thermal treatment (including photo-annealing) is important. There is no particular limitation on when to perform the thermal treatment as long as it is performed after the formation of the second oxide semiconductor layer 745; for example, it may be performed after the formation of a pixel electrode.
[0196] Further, gallium is not used in the oxide semiconductor layer as is in this embodiment, so that a target containing gallium that is a material which brings high manufacturing cost is not necessarily used.
[0197] This embodiment can be combined with the structure described in any other Embodiment, as appropriate.
[0198] For example, although the example of the stacked-layer structure in which an In—Zn—O based oxide semiconductor formed by a sputtering method is used as each of the first oxide semiconductor layer 748 and the third oxide semiconductor layer 746 and a Sn—Zn—O based oxide semiconductor containing SiOx is used as each of the second oxide semiconductor layer 745 and the fourth oxide semiconductor layer 747 is described in Embodiment 5, the present invention is not limited thereto; a single-layer structure as described in Embodiment 2 may be employed and for example, a thin film transistor using a Sn—Zn—O based oxide semiconductor containing SiOx, may be manufactured.
[Embodiment 6]
[0199] In Embodiment 6, an example of a top-gate type thin film transistor 330 will be described using FIGS. 16A and 16B . FIG. 16B is an example of a top view of a thin film transistor, cross-sectional view along dotted line P1-P2 of which corresponds to FIG. 16A .
[0200] In FIG. 16A , a first wiring 309 and a second wiring 310 are formed over a substrate 300. The first wiring 309 and the second wiring 310 serve as a source and drain electrodes.
[0201] Next, a first oxide semiconductor layer 304 containing SiOx and a second oxide semiconductor layer 305 are formed over the first wiring 309 and the second wiring 310. In this embodiment, a Sn—Zn—O based oxide semiconductor containing SiOx is used as the first oxide semiconductor layer 304, and an In—Ga—Zn—O based non-single-crystal film is used as the second oxide semiconductor layer 305.
[0202] In the first oxide semiconductor layer 304, an oxide semiconductor layer having a concentration gradient of a Si element in the film thickness direction, increasing in accordance with an increase in the distance from a gate electrode formed later may be included.
[0203] Next, a gate insulating layer 303 which covers the second oxide semiconductor layer 305, the first wiring 309, and the second wiring 310 is formed.
[0204] Next, it is preferable to perform thermal treatment at 200° C. to 600° C., typically, 300° C. to 500° C. In this embodiment, thermal treatment is performed in a furnace at 350° C. for one hour in an air atmosphere. By this thermal treatment, atomic rearrangement of the first oxide semiconductor layer 304 and the second oxide semiconductor layer 305 is performed. This thermal treatment releases strain energy which inhibits carrier travel, and therefore, the thermal treatment (including photo-annealing) is important.
[0205] Next, a gate electrode 301 is provided in a position which overlaps with the region where the first oxide semiconductor layer 304 is in contact with the substrate 300, over the gate insulating layer 303.
[0206] Through the above process, the top-gate type thin film transistor 330 can be manufactured.
[0207] This embodiment can be combined with the structure described in any other Embodiment, as appropriate.
[0208] For example, although the example of the stacked-layer structure in which a Sn—Zn—O based oxide semiconductor containing SiOx formed by a sputtering method is used as the first oxide semiconductor layer 304 and an In—Ga—Zn—O based oxide semiconductor is used as the second oxide semiconductor layer 305 is described in Embodiment 6, the present invention is not limited thereto; a single-layer structure may be employed and for example, a thin film transistor using a Sn—Zn—O based oxide semiconductor containing SiOx may be manufactured.
[Embodiment 7]
[0209] In Embodiment 7, an example of a top-gate type thin film transistor 630 will be described using FIGS. 17A and 17B . FIG. 17B is an example of a top view of a thin film transistor, cross-sectional view along dotted line R1-R2 of which corresponds to FIG. 17A .
[0210] In FIG. 17A , a first oxide semiconductor layer 604 containing SiOx and a second oxide semiconductor layer 605 are formed over a substrate 600. In this embodiment, a Sn—Zn—O based oxide semiconductor film containing SiOx is used as the first oxide semiconductor layer 604, and an In—Ga—Zn—O based non-single-crystal film is used as the second oxide semiconductor layer 605.
[0211] In the first oxide semiconductor layer 604, an oxide semiconductor layer having a concentration gradient of a Si element in the film thickness direction, increasing in accordance with an increase in the distance from a gate electrode formed later may be included.
[0212] Next, n+ layers 606a and 606b are formed over the second oxide semiconductor layer 605. In this embodiment, the n+ layers 606a and 606b which serve as a source and drain regions are Ga—Zn—O based non-single-crystal films. The n+ layers 606a and 606b may be formed using a Ga—Zn—O based non-single-crystal film containing nitrogen, that is, a Ga—Zn—O—N based non-single-crystal film (also called a GZON film).
[0213] Next, a first wiring 609 is formed over the n+ layer 606a and a second wiring 610 is formed over the n+ layer 606b. The first wiring 609 and the second wiring 610 serve as a source and drain electrodes.
[0214] Next, a gate insulating layer 603 is formed over the first wiring 609 and the second wiring 610.
[0215] Next, a gate electrode 601 is provided in a position which overlaps with the region where the second oxide semiconductor layer 605 is in contact with the gate insulating layer 603, over the gate insulating layer 603.
[0216] Next, it is preferable to perform thermal treatment at 200° C. to 600° C., typically, 300° C. to 500° C. In this embodiment, thermal treatment is performed in a furnace at 350° C. for one hour in an air atmosphere. By this thermal treatment, atomic rearrangement of the first oxide semiconductor layer 604 and the second oxide semiconductor layer 605 is performed. This thermal treatment releases strain energy which inhibits carrier travel, and therefore, the thermal treatment (including photo-annealing) is important.
[0217] Through the above process, the top-gate type thin film transistor 630 can be manufactured.
[0218] Further, the present invention is not limited to the above-described structure including the n+ layers 606a and 606b; a structure in which an n+ layer is not provided may be employed.
[0219] This embodiment can be combined with the structure described in any other Embodiment, as appropriate.
[0220] For example, although the example of the stacked-layer structure in which a Sn—Zn—O based oxide semiconductor containing SiOx formed by a sputtering method is used as the first oxide semiconductor layer 604 and an In—Ga—Zn—O based oxide semiconductor is used as the second oxide semiconductor layer 605 is described in Embodiment 7, the present invention is not limited thereto; a single-layer structure may be employed and for example, a thin film transistor using a Sn—Zn—O based oxide semiconductor containing SiOx may be manufactured.
[Embodiment 8]
[0221] In Embodiment 8, an example of a light-emitting display device will be described as a semiconductor device. As a display element included in a display device, a light-emitting element using electro luminescence is described here. Light-emitting elements using electroluminescence are classified according to whether a light-emitting material is an organic compound or an inorganic compound; the former is referred to as an organic EL element, and the latter as an inorganic EL element.
[0222] In an organic EL element, voltage is applied to the light-emitting element, so that electrons are injected from one electrode into a layer including a light-emitting organic compound, and holes are injected from the other electrode into the layer including a light-emitting organic compound, whereby current flows. Then, by recombination of these carriers (electrons and holes), the light-emitting organic compound gets in an excited state, and light is emitted when the excited state returns to a ground state. From such a mechanism, such a light-emitting element is called a current excitation type light-emitting element.
[0223] Inorganic EL elements are classified in a dispersive inorganic EL element and a thin-film inorganic EL element. A dispersive inorganic EL element includes a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and light emission mechanism thereof is donor-acceptor recombination light emission in which a donor level and an acceptor level are utilized. In a thin-film inorganic EL element, a light-emitting layer is sandwiched between dielectric layers, and the dielectric layers are sandwiched between electrodes. Light emission mechanism thereof is local light emission in which inner-shell electron transition of a metal ion is utilized. Described here is the case in which an organic EL element is used as a light-emitting element.
[0224] FIG. 18 is a diagram showing an example of a pixel configuration as an example of a semiconductor device, which can be driven by a digital time grayscale method.
[0225] The configuration and operation of the pixel to which a digital time grayscale method can be applied are described. Described here is an example in which two n-channel transistors using an oxide semiconductor layer (typically, an In—Ga—Zn—O based non-single-crystal film containing SiOx) in a channel formation region are provided in each pixel.
[0226] A pixel 6400 includes a switching transistor 6401, a driving transistor 6402, a light-emitting element 6404, and a capacitor 6403. A gate of the switching transistor 6401 is connected to a scan line 6406, a first electrode (one of a source electrode and a drain electrode) of the switching transistor 6401 is connected to a signal line 6405, and a second electrode (the other of the source electrode and the drain electrode) of the switching transistor 6401 is connected to a gate of the driving transistor 6402. The gate of the driving transistor 6402 is connected to a power supply line 6407 through the capacitor 6403, a first electrode of the driving transistor 6402 is connected to the power supply line 6407, and a second electrode of the driving transistor 6402 is connected to a first electrode (pixel electrode) of the light-emitting element 6404. A second electrode of the light-emitting element 6404 corresponds to a common electrode 6408. The common electrode 6408 is electrically connected to a common potential line, the common electrode 6408 and the common potential line are formed over the same substrate, and a portion in which the common electrode 6408 is electrically connected to the common potential line may be used as a common connection portion.
[0227] The second electrode of the light-emitting element 6404 (the common electrode 6408) is set to a low power supply potential. The low power supply potential is a potential satisfying the low power supply potential <a high power supply potential with the high power supply potential set to the power supply line 6407 as a reference. A potential difference between the high power supply potential and the low power supply potential is applied to the light-emitting element 6404, so that current flows into the light-emitting element 6404. In order to make the light-emitting element 6404 emit light, each potential is set so that the potential difference between the high power supply potential and the low power supply potential is equal to or greater than the forward threshold voltage of the light-emitting element 6404.
[0228] Gate capacitance of the driving transistor 6402 may be used as a substitute for the capacitor 6403, so that the capacitor 6403 can be omitted. The gate capacitance of the driving transistor 6402 may be formed between the channel region and the gate electrode of the driving transistor 6402.
[0229] In the case of a voltage-input voltage-driving method, a video signal is input to the gate of the driving transistor 6402 so that the driving transistor 6402 is in either of two states of being sufficiently turned on and turned off. That is, the driving transistor 6402 operates in a linear region. Since the driving transistor 6402 operates in a linear region, a voltage higher than the voltage of the power supply line 6407 is applied to the gate of the driving transistor 6402. A voltage greater than or equal to (power supply line voltage+Vth of the driving transistor 6402) is applied to the signal line 6405.
[0230] In the case of performing analog grayscale driving instead of digital time grayscale driving, the same pixel configuration as FIG. 18 can be used by changing signal input.
[0231] In the case of performing the analog grayscale driving, a voltage greater than or equal to (forward voltage of the light-emitting element 6404+Vth of the driving transistor 6402) is applied to the gate of the driving transistor 6402. The forward voltage of the light-emitting element 6404 refers to a voltage with which a desired luminance is obtained, and includes at least a forward threshold voltage. The video signal at which the driving transistor 6402 operates in a saturation region is input, so that current can flow into the light-emitting element 6404. In order that the driving transistor 6402 can operate in the saturation region, the potential of the power supply line 6407 is set to be higher than the gate potential of the driving transistor 6402. By using an analog signal as the video signal, current in accordance with the video signal flows into the light-emitting element 6404, so that the analog grayscale driving can be performed.
[0232] Note that the pixel configuration shown in FIG. 18 is not limited to the above-described configuration. For example, a switch, a resistor, a capacitor, a transistor, a logic circuit, or the like may be added to the pixel shown in FIG. 18 .
[0233] Next, structures of light-emitting elements are described using FIGS. 19A to 19C . A cross-sectional structure of a pixel in the case where an n-channel driving TFT is used is described. TFTs 7001, 7011, and 7021 serving as driver TFTs used for respective semiconductor devices illustrated in FIGS. 19A , 19B, and 19C, can be manufactured in a manner similar to the second thin film transistor 170 described in Embodiment 2. The TFTs 7001, 7011, and 7021 are thin film transistors each including an oxide semiconductor film containing SiOx.
[0234] In order to extract light emission of the light-emitting element, at least one of an anode and a cathode may be transparent. A thin film transistor and a light-emitting element are formed over a substrate. A light-emitting element can have: a top emission structure in which light emission is extracted through the surface on the opposite side to the substrate; a bottom emission structure in which light emission is extracted through the surface on the substrate side; or a dual emission structure in which light emission is extracted through the surface on the substrate side and the surface on the opposite side to the substrate. The pixel configuration can be applied to a light-emitting element having any of these emission structures.
[0235] A light-emitting element having a top emission structure is described using FIG. 19A .
[0236] FIG. 19A is a cross-sectional view of a pixel in the case where the driving TFT 7001 is an n-channel TFT and light is emitted from a light-emitting element 7002 and passes through an anode 7005 side. In the TFT 7001, an In—Sn—Zn—O based oxide semiconductor containing silicon oxide is used as a semiconductor layer. The impurity such as silicon oxide contained can prevent crystallization of the oxide semiconductor and/or generation of a microcrystal grain even when thermal treatment at 300° C. to 600° C. is performed. In FIG. 19A , a cathode 7003 of the light-emitting element 7002 is electrically connected to the driving TFT 7001, and a light-emitting layer 7004 and the anode 7005 are stacked in this order over the cathode 7003. The cathode 7003 can be formed using a variety of materials as long as they are conductive films which have low work functions and reflect light. For example, Ca, Al, MgAg, AlLi, or the like is preferably used. The light-emitting layer 7004 may be formed using either a single layer or a stacked layer of a plurality of layers. If the light-emitting layer 7004 is formed using a plurality of layers, an electron-injecting layer, an electron-transporting layer, a light-emitting layer, a hole-transporting layer, and a hole-injecting layer are stacked in this order over the cathode 7003. It is not necessary to provide all of these layers. The anode 7005 is formed using a light-transmitting conductive material such as indium oxide including tungsten oxide, indium zinc oxide including tungsten oxide, indium oxide including titanium oxide, indium tin oxide including titanium oxide, indium tin oxide (hereinafter, referred to as ITO), indium zinc oxide, or indium tin oxide to which silicon oxide is added.
[0237] A region where the light-emitting layer 7004 is sandwiched between the cathode 7003 and the anode 7005 corresponds to the light-emitting element 7002. In the case of the pixel illustrated in FIG. 19A , light is emitted from the light-emitting element 7002 and passes through the anode 7005 side as indicated by an arrow.
[0238] Next, a light-emitting element having a bottom emission structure is described using FIG. 19B . FIG. 19B is a cross-sectional view of a pixel in the case where a driving TFT 7011 is an n-channel TFT and light emitted from a light-emitting element 7012 passes through a cathode 7013 side. In the TFT 7011, an In—Al—Zn—O based oxide semiconductor containing silicon oxide is used as a semiconductor layer. The impurity such as silicon oxide contained can prevent crystallization of the oxide semiconductor and/or generation of a microcrystal grain even when thermal treatment at 300° C. to 600° C. is performed. In FIG. 19B , the cathode 7013 of the light-emitting element 7012 is formed over a light-transmitting conductive film 7017 that is electrically connected to the driving TFT 7011, and a light-emitting layer 7014 and an anode 7015 are stacked in this order over the cathode 7013. A blocking film 7016 for reflecting or blocking light may be formed so as to cover the anode 7015 when the anode 7015 has a light-transmitting property. As the cathode 7013, a variety of materials can be used as is in the case of FIG. 19A as long as they are conductive materials having low work functions. The cathode 7013 has a thickness as small as light can be transmitted therethrough (preferably, about 5 to 30 nm). For example, an aluminum film with a thickness of 20 nm can be used as the cathode 7013. Further, as is in FIG. 19A , the light-emitting layer 7014 may be formed using a single layer or a stacked layer including a plurality of layers. Although the anode 7015 does not need to transmit light, the anode 7015 can be formed using a light-transmitting conductive material as is in FIG. 19A . As for the blocking film 7016, a metal or the like that reflects light can be used; however, it is not limited to a metal film. For example, a resin or the like to which black pigments are added can be used.
[0239] A region where the light-emitting layer 7014 is sandwiched between the cathode 7013 and the anode 7015 corresponds to the light-emitting element 7012. In the case of the pixel illustrated in FIG. 19B , light is emitted from the light-emitting element 7012 and ejected to the cathode 7013 side as indicated by an arrow.
[0240] Next, a light-emitting element having a dual emission structure is described using FIG. 19C . In FIG. 19C , a cathode 7023 of a light-emitting element 7022 is formed over a light-transmitting conductive film 7027 which is electrically connected to the driving TFT 7021, and a light-emitting layer 7024 and an anode 7025 are stacked in this order over the cathode 7023. In the TFT 7021, a Sn—Al—Zn—O based oxide semiconductor containing silicon oxide is used as a semiconductor layer. The impurity such as silicon oxide contained can prevent crystallization of the oxide semiconductor and/or generation of a microcrystal grain even when thermal treatment at 300° C. to 600° C. is performed. As in the case of FIG. 19A , the cathode 7023 can be formed using a variety of conductive materials as long as they have low work functions. The cathode 7023 has a thickness as small as light can be transmitted therethrough. For example, an aluminum film with a thickness of 20 nm can be used as the cathode 7023. Further, as is in FIG. 19A , the light-emitting layer 7024 may be formed using a single layer or a stacked layer including a plurality of layers. As is in FIG. 19A , the anode 7025 can be formed using a light-transmitting conductive material.
[0241] A region where the cathode 7023, the light-emitting layer 7024, and the anode 7025 overlap with each other corresponds to the light-emitting element 7022. In the case of the pixel illustrated in FIG. 19C , light is emitted from the light-emitting element 7022 and ejected to both the anode 7025 side and the cathode 7023 side as indicated by arrows.
[0242] Although an organic EL element is described as a light-emitting element in Embodiment 8, it is also possible to provide an inorganic EL element as a light-emitting element.
[0243] An example in which a thin film transistor for controlling the driving of a light-emitting element (a driving TFT) is electrically connected to a light-emitting element is described in Embodiment 8; a current control TFT may be provided between the driving TFT and the light-emitting element.
[0244] Through the above step, a highly reliable light-emitting display device (display panel) as a semiconductor device can be manufactured.
[0245] This embodiment can be combined with the structure described in any other Embodiment, as appropriate.
[Embodiment 9]
[0246] In Embodiment 9, an example of electronic paper will be described as a semiconductor device.
[0247] FIG. 20A is a cross-sectional view illustrating an active-matrix electronic paper. A thin film transistor 581 used in a display portion of the semiconductor device can be manufactured in a manner similar to the thin film transistor 170 described in Embodiment 2 and is a thin film transistor having highly electrical characteristics, including an oxide semiconductor film as a semiconductor layer. In this embodiment, a thin film transistor having highly electrical characteristics, in which a Zn—O based oxide semiconductor containing silicon oxide is included as a semiconductor layer is used.
[0248] The electronic paper in FIG. 20A is an example of a display device using a twisting ball display system. According to a twisting ball display system, the direction of spherical particles each of which is colored separately in black and white, which are arranged between a first electrode layer and a second electrode layer which are electrode layers used for a display element is controlled by a potential difference generated between the first electrode layer and the second electrode layer to display an image.
[0249] The thin film transistor 581 interposed between a substrate 580 and a substrate 596 is a bottom-gate thin film transistor, and a source or drain electrode layer thereof is in contact with a first electrode layer 587 through an opening formed in insulating layers 583, 584, and 585, whereby the thin film transistor 581 is electrically connected to the first electrode layer 587. Between the first electrode layer 587 and a second electrode layer 588, spherical particles 589 are provided. Each spherical particle 589 includes a black region 590a and a white region 590b, and a cavity 594 filled with liquid around the black region 590a and the white region 590b. The space between the spherical particles 589 is filled with a filler 595 such as a resin (see FIG. 20A ).
[0250] In Embodiment 9, the first electrode layer 587 corresponds to a pixel electrode and the second electrode layer 588 corresponds to a common electrode. The second electrode layer 588 is electrically connected to a common potential line, the common potential line and the thin film transistor 581 are provided over the same substrate. The second electrode layer 588 and the common potential line are electrically connected through conductive particles arranged between a pair of substrates, in the common connection portion.
[0251] Instead of the twisting ball, an electrophoretic element can also be used. A microcapsule having a diameter of about 10 μm to 200 μm, in which transparent liquid and positively charged white microparticles and negatively charged black microparticles are encapsulated, is used. In the microcapsule that is provided between the first electrode layer and the second electrode layer, when an electric field is applied by the first electrode layer and the second electrode layer, the white microparticles and the black microparticles migrate to opposite sides to each other, so that color white or black can be displayed. A display element using this principle is an electrophoretic display element and is called electronic paper. The electrophoretic display element has higher reflectivity than a liquid crystal display element; thus, an auxiliary light is not required, power consumption is small, and a display portion can be recognized even in a dusky place. In addition, even when power is not supplied to the display portion, an image which has been displayed once can be maintained; thus, a displayed image can be stored even if a semiconductor device equipped with a display function (which may simply be referred to as a display device or a semiconductor device provided with a display device) is distanced from an electric wave source.
[0252] By manufacturing the thin film transistor according to the process described in Embodiment 2, electronic paper can be manufactured with reduced manufacturing cost, as a semiconductor device. An electronic paper can be used for electronic apparatuses of a variety of fields as long as they can display data. For example, an electronic paper can be applied to an e-book reader (electronic book), a poster, an advertisement in a vehicle such as a train, or displays of various cards such as a credit card. An example of the electronic apparatus is illustrated in FIG. 20B .
[0253] FIG. 20B illustrates an example of an e-book reader 2700. For example, the e-book reader 2700 includes two housings: a housing 2701 and a housing 2703. The housing 2701 and the housing 2703 are combined with a hinge 2711 so that the e-book reader 2700 can be opened and closed with the hinge 2711 as an axis. With such a structure, the e-book reader 2700 can operate like a paper book.
[0254] A display portion 2705 and a display portion 2707 are incorporated in the housing 2701 and the housing 2703, respectively. The display portion 2705 and the display portion 2707 may display one image or different images. In the case where the display portion 2705 and the display portion 2707 display different images, for example, a display portion on the right side (the display portion 2705 in FIG. 20B ) can display text whereas a display portion on the left side (the display portion 2707 in FIG. 20B ) can display graphics.
[0255] In the example illustrated in FIG. 20B , the housing 2701 is provided with an operation portion and the like. For example, the housing 2701 is provided with a power switch 2721, operation keys 2723, a speaker 2725, and the like. With the operation keys 2723, pages can be turned. Note that a keyboard, a pointing device, and the like may be provided on the same plane as the display portion of the housing. Further, an external connection terminal (an earphone terminal, a USB terminal, a terminal that can be connected to various cables such as an AC adapter and a USB cable, or the like), a recording medium insertion portion, and the like may be provided on the back surface or the side surface of the housing. Moreover, the e-book reader 2700 may be equipped with a function of an electronic dictionary.
[0256] The e-book reader 2700 may have a structure capable of wirelessly transmitting and receiving data. Through wireless communication, book data or the like can be purchased and downloaded from an e-book server.
[0257] This embodiment can be combined with the structure described in any other Embodiment, as appropriate.
[Embodiment 10]
[0258] A semiconductor device including a thin film transistor using an oxide semiconductor layer can be applied to a variety of electronic apparatuses (including amusement machines). Examples of electronic appliances include television sets (also referred to as televisions or television receivers), monitors of computers or the like, cameras such as digital cameras or digital video cameras, digital photo frames, cellular phones (also referred to as mobile phones or mobile phone sets), portable game consoles, portable information terminals, audio reproducing devices, and large-sized game machines such as pachinko machines.
[0259] FIG. 21A illustrates an example of a television set 9601. In the television set 9601, a display portion 9603 is incorporated in a housing. The display portion 9603 can display images. Illustrated in FIG. 21A is the structure in which the rear side of the housing is supported by fixing to a wall 9600.
[0260] The television set 9601 can be operated with an operation switch provided with the housing or a separate remote controller 9610. Channels and volume can be controlled with an operation key 9609 provided with the remote controller 9610 so that an image displayed on the display portion 9603 can be controlled. Furthermore, the remote controller 9610 may be provided with a display portion 9607 for displaying data output from the remote controller 9610.
[0261] Note that the television set 9601 is provided with a receiver, a modem, and the like. With the receiver, general television broadcasting can be received. Moreover, when the display device is connected to a communication network with or without wires via the modem, one-way (from sender to receiver) or two-way (between sender and receiver or between receivers) data communication can be performed.
[0262] FIG. 21B is a portable amusement machine including two housings, a housing 9881 and a housing 9891. The housings 9881 and 9891 are connected with a connection portion 9893 so as to be opened and closed. A display portion 9882 and a display portion 9883 are incorporated in the housing 9881 and the housing 9891, respectively. In addition, the portable amusement machine illustrated in FIG. 21B includes a speaker portion 9884, a recording medium insertion portion 9886, an LED lamp 9890, an input unit (operation keys 9885, a connection terminal 9887, a sensor 9888 (a sensor equipped with a function of measuring force, displacement, position, speed, acceleration, angular velocity, rotational frequency, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, electric power, radiation, flow rate, humidity, gradient, oscillation, odor, or infrared rays), or a microphone 9889), and the like. The structure of the portable amusement machine is not limited to the above as long as a semiconductor device is provided; any other structure provided with any other accessory equipment as appropriate can be employed as well. The portable amusement machine illustrated in FIG. 21B is equipped with a function of reading a program or data stored in a recording medium to display on the display portion and/or a function of sharing data with another portable amusement machine by wireless communication. The portable amusement machine illustrated in FIG. 21B can be equipped with various functions without being limited to the above.
[0263] FIG. 22A illustrates an example of a mobile phone 1000. The mobile phone 1000 is provided with a display portion 1002 incorporated in a housing 1001, operation buttons 1003, an external connection port 1004, a speaker 1005, a microphone 1006, and the like.
[0264] Data can be input to the mobile phone 1000 illustrated in FIG. 22A by touching the display portion 1002 with a finger or the like. Furthermore, operations such as making calls and texting messaging can be performed by touching the display portion 1002 with a finger or the like.
[0265] There are mainly three screen modes of the display portion 1002. The first is a display mode mainly for displaying an image. The second is an input mode mainly for inputting data such as text. The third is a display-and-input mode in which two modes of the display mode and the input mode are mixed.
[0266] For example, in the case of making a call or texting messaging, the text input mode mainly for inputting text is selected for the display portion 1002 so that text displayed on the screen can be input. In that case, it is preferable to display a keyboard or number buttons on almost all the area of the screen of the display portion 1002.
[0267] Further, a detector including a sensor for detecting inclination, such as a gyroscope or an acceleration sensor, may be provided inside the mobile phone 1000, so that display on the screen of the display portion 1002 can be automatically switched by determining the direction of the mobile phone 1000 (whether the mobile phone 1000 is placed horizontally or vertically for a landscape mode or a portrait mode).
[0268] The screen mode is switched by touching the display portion 1002 or operating the operation buttons 1003 of the housing 1001. The screen modes can also be switched depending on the kind of images displayed on the display portion 1002. For example, when a signal for an image displayed on the display portion is data of moving images, the screen mode is switched to the display mode, whereas when the signal is text data, the screen mode is switched to the input mode.
[0269] Moreover, the following control may be performed: in the input mode, when input by touching the display portion 1002 is not performed within a specified period while a signal detected by the optical sensor in the display portion 1002 is detected, the screen mode is switched from the input mode to the display mode.
[0270] The display portion 1002 can also be functioned as an image sensor. For example, an image of a palm print, a fingerprint, or the like is taken by touching the display portion 1002 with the palm or the finger, whereby personal authentication can be performed. Furthermore, by providing a backlight or a sensing light source emitting a near-infrared light for the display portion, an image of a finger vein, a palm vein, or the like can also be taken.
[0271] FIG. 22B also illustrates an example of a mobile phone. The mobile phone illustrated in FIG. 22B is provided with a display device 9410 having a display portion 9412 and operation buttons 9413 in a housing 9411 and a communication device 9400 having scan buttons 9402, an external input terminal 9403, a microphone 9404, a speaker 9405, and a light-emitting portion 9406 which emits light when receiving a call in a housing 9401. The display device 9410 equipped with a display function can be detached from or attached to the communication device 9400 equipped with a telephone function in two directions indicated by arrows. Therefore, the display device 9410 and the communication device 9400 can be attached to each other along either of respective short axes or long axes. In the case where only the display function is needed, the display device 9410 can be detached from the communication device 9400 and used alone. Images or input data can be transmitted or received by wireless or wire communication between the communication device 9400 and the display device 9410, each of which has a rechargeable battery.
[0272] This embodiment can be combined with the structure described in any other Embodiment, as appropriate.
[0273] This application is based on Japanese Patent Application serial no. 2009-008134 filed with Japan Patent Office on Jan. 16, 2009, the entire contents of which are hereby incorporated by reference.
Claims
Certificate of Correction present
The claims shown below may not include correction changes. Use the corrected PDF for authoritative text.
What is claimed is:
1. A semiconductor device comprising:
a gate electrode over an insulating surface;
an insulating layer over the gate electrode;
a first oxide semiconductor layer over the insulating layer;
a second oxide semiconductor layer over the first oxide semiconductor layer, the second oxide semiconductor layer containing zinc and silicon, and
a source electrode and a drain electrode over the second oxide semiconductor layer;
wherein the second oxide semiconductor layer includes a depression between the source electrode and the drain electrode, and
wherein a concentration of silicon in the second oxide semiconductor layer is larger than a concentration of silicon in the first oxide semiconductor layer.
2. The semiconductor device according to claim 1, wherein the second oxide semiconductor layer is amorphous.
3. A semiconductor device comprising:
a gate electrode over an insulating surface;
an insulating layer over the gate electrode;
a first oxide semiconductor layer over the insulating layer;
a second oxide semiconductor layer over the first oxide semiconductor layer, the second oxide semiconductor layer containing zinc and SiOx, and
a source electrode and a drain electrode over the second oxide semiconductor layer;
wherein the second oxide semiconductor layer includes a depression between the source electrode and the drain electrode, and
wherein a concentration of silicon in the second oxide semiconductor layer is larger than a concentration of silicon in the first oxide semiconductor layer.
4. The semiconductor device according to claim 3, wherein at least one of the first oxide semiconductor layer and the second oxide semiconductor layer contains indium.
5. The semiconductor device according to claim 3, wherein at least one of the first oxide semiconductor layer and the second oxide semiconductor layer contains gallium.
6. The semiconductor device according to claim 3, wherein the first oxide semiconductor layer or the second oxide semiconductor layer is formed by a sputtering method using an oxide semiconductor target containing SiO2 at from 0.1 wt % to 10 wt % inclusive.
7. The semiconductor device according to claim 3, wherein the second oxide semiconductor layer is amorphous.
8. A semiconductor device comprising:
a first oxide semiconductor layer over an insulating surface, the first oxide semiconductor layer containing zinc and silicon;
a second oxide semiconductor layer over the first oxide semiconductor layer;
an insulating layer over the second oxide semiconductor layer; and
a gate electrode over the insulating layer,
wherein a concentration of silicon in the first oxide semiconductor layer is larger than a concentration of silicon in the second oxide semiconductor layer.
9. The semiconductor device according to claim 8, wherein the first oxide semiconductor layer is amorphous.
10. A semiconductor device comprising:
a first oxide semiconductor layer over an insulating surface, the first oxide semiconductor layer containing zinc and SiOx;
a second oxide semiconductor layer over the first oxide semiconductor layer;
an insulating layer over the second oxide semiconductor layer; and
a gate electrode over the insulating layer,
wherein a concentration of silicon in the first oxide semiconductor layer is larger than a concentration of silicon in the second oxide semiconductor layer.
11. The semiconductor device according to claim 10, wherein at least one of the first oxide semiconductor layer and the second oxide semiconductor layer contains indium.
12. The semiconductor device according to claim 10, wherein at least one of the first oxide semiconductor layer and the second oxide semiconductor layer contains gallium.
13. The semiconductor device according to claim 10, wherein the first oxide semiconductor layer or the second oxide semiconductor layer is formed by a sputtering method using an oxide semiconductor target containing SiO2 at from 0.1 wt % to 10 wt % inclusive.
14. The semiconductor device according to claim 10, wherein the first oxide semiconductor layer is amorphous.
15. A semiconductor device comprising:
a first oxide semiconductor layer on and in contact with an insulating surface, the first oxide semiconductor layer containing indium, gallium, zinc and silicon;
a second oxide semiconductor layer over the first oxide semiconductor layer, the second oxide semiconductor layer containing indium, gallium and zinc; and
a gate electrode adjacent to the first oxide semiconductor layer and the second oxide semiconductor layer,
wherein a concentration of silicon in the first oxide semiconductor layer is larger than a concentration of silicon in the second oxide semiconductor layer.
16. The semiconductor device according to claim 15, wherein the gate electrode is formed over the second oxide semiconductor layer.
17. The semiconductor device according to claim 15, wherein the first oxide semiconductor layer is amorphous.
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