Top gate thin film transistor and display apparatus including the same

[0001] 1. Field of the Invention

[0002] The present invention relates to a top gate thin film transistor (top gate type thin film transistor) that uses an oxide semiconductor for a semiconductor layer, and a display apparatus including the top gate thin film transistor.

[0003] 2. Description of the Related Art

[0004] Thin film transistors (TFTs) that use amorphous silicon or low-temperature polysilicon for a semiconductor layer are widely used in a drive circuit in display apparatuses such as active matrix liquid crystal display devices and organic electroluminescence (EL) display devices. However, the manufacture of those TFTs requires a high temperature process, and hence it is difficult to employ a flexible substrate such as a plastic substrate or a film substrate which is low in heat resistance.

[0005] Meanwhile, in recent years, the development of TFTs that use, for a semiconductor layer, an oxide semiconductor having ZnO as a main component has recently become active. This oxide semiconductor can be made into a film at low temperature, and hence it is possible to form a TFT on a plastic substrate, a film substrate, or the like. However, the oxide semiconductor having ZnO as the main component has high sensitivity with respect to an atmosphere, and hence, in order to enable actual use of the TFT, it is necessary to isolate the oxide semiconductor layer from the atmosphere by a protective layer.

[0006] A plasma-enhanced chemical vapor deposition (PECVD) method is generally used as a method of forming the protective layer, which is high in film formation speed and is excellent in productivity. However, it is known that an insulating layer made of silicon nitride or the like, which is formed by a PECVD method and serves as a protective layer, has a large hydrogen amount in the layer, and hence when hydrogen is diffused from the protective layer into a channel region formed in the oxide semiconductor, the resistance of the oxide semiconductor is reduced (see SID'08 Digest, p. 633 (2008)).

[0007] As a method of preventing hydrogen from diffusing into the channel region, there is disclosed a method of forming a protective layer containing hydrogen while using a gate insulating layer and a gate electrode layer as a mask in a top gate polycrystalline oxide TFT having ZnO as the main component (see Japanese Patent Application Laid-Open No. 2007-220817). In this case, the hydrogen concentration of the semiconductor layer in an unmasked region increases, and therefore the resistance of the unmasked region of the semiconductor layer reduces. In this manner, source and drain electrode layers are formed in a self-alignment manner, and thus a TFT having a coplanar structure may be obtained.

[0008] In the structure disclosed in Japanese Patent Application Laid-Open No. 2007-220817, in order to prevent hydrogen from diffusing into the channel region of the semiconductor layer when the protective layer containing hydrogen is formed, the gate insulating layer or the gate electrode layer to be the mask is required to have a function of sufficiently suppressing the hydrogen diffusion.

[0009] When silicon oxide or the like is used for the gate insulating layer, in order to suppress reduction in resistance of the semiconductor layer, the gate insulating layer is preferred to be formed thick. However, the increase in thickness of the gate insulating layer may cause an increase in drive voltage of the TFT, or lowering of an on-current or deterioration of an S value.

[0010] Therefore, it is more desired to provide a function of suppressing hydrogen diffusion to the gate electrode layer. However, the inventors of the prevent invention have been made clear that, when Mo is used for the gate electrode layer, hydrogen diffusion cannot be suppressed even if the film thickness is 200 nm. Further, even when a polycrystalline oxide semiconductor such as indium tin oxide (ITO) and ZnO is used for the gate electrode layer, hydrogen is diffused through grain boundaries in the polycrystalline oxide semiconductor, and hence the reduction in resistance of the channel region of the semiconductor layer cannot be suppressed. From the facts above, a gate electrode layer capable of suppressing hydrogen diffusion has been desired.

[0011] It is therefore an object of the present invention to provide a top gate oxide semiconductor TFT, which is capable of suppressing reduction in resistance of a channel region of an oxide semiconductor layer due to hydrogen diffusion, and to provide a display apparatus including the top gate oxide semiconductor TFT.

[0012] In order to solve the above-mentioned problems, according to the present invention, there is provided a top gate thin film transistor including on a substrate: a source electrode layer; a drain electrode layer; an oxide semiconductor layer; a gate insulating layer; a gate electrode layer including an amorphous oxide semiconductor containing at least one kind of element selected from among In, Ga, Zn, and Sn; and a protective layer containing hydrogen, in which: the gate insulating layer is formed on a channel region of the oxide semiconductor layer; the gate electrode layer is formed on the gate insulating layer; and the protective layer is formed on the gate electrode layer.

[0013] According to the present invention, even in a case where deposition of the protective layer containing hydrogen or hydrogen plasma processing is carried out, it is possible to suppress the reduction in resistance of the channel region made of an oxide semiconductor. Further, by employing the gate electrode layer of the present invention, a leakage current density of the gate insulating layer may be reduced.

[0014] Further features of the present invention will become apparent from the following description of exemplary embodiments with reference to the attached drawings.

[0024] Hereinafter, a top gate thin film transistor (top gate type thin film transistor) (TFT) according to an exemplary embodiment of the present invention is described with reference to the accompanying drawings.

[0025] FIG. 1 is a cross-sectional view illustrating a structure of an oxide semiconductor TFT having a top gate coplanar structure, which is an example of the exemplary embodiment of the present invention. The oxide semiconductor TFT includes a substrate 10, an oxide semiconductor layer 11 including a channel region 11a and source and drain regions 11b, a gate insulating layer 12, a gate electrode layer 13, a protective layer 14, and source and drain wiring layers 15.

[0026] A glass substrate is preferred to be used as the substrate 10. Alternatively, there may be employed a plastic film of polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyimide, polycarbonate, and the like, a thin plate, a stainless substrate coated with an insulating layer, and the like.

[0027] First, on the substrate 10, the oxide semiconductor layer 11 is formed by methods such as a sputtering method, a pulse laser deposition (PLD) method, and an electron beam deposition method. After that, the oxide semiconductor layer 11 is patterned by a photolithography method and an etching method. As the oxide semiconductor layer 11, an amorphous oxide semiconductor containing at least one kind of element selected from among In, Ga, Zn, and Sn is preferred to be used.

[0028] Next, on the oxide semiconductor layer 11 (on the channel region 11a of the oxide semiconductor layer), the gate insulating layer 12 is formed by methods such as a sputtering method, a pulse laser deposition (PLD) method, an electron beam deposition method, and a plasma-enhanced CVD method. The gate insulating layer 12 is provided in direct contact to the oxide semiconductor layer 11, and hence the gate insulating layer 12 is required to have a function of suppressing reduction in resistance of the channel region 11a of the oxide semiconductor layer when the gate insulating layer 12 is formed. Specifically, as the gate insulating layer 12, an insulating layer containing oxygen, such as a silicon oxide layer and a silicon oxynitride layer, is preferred to be used. Those insulating layers raise no problems even when the compositions of the insulating layers do not strictly follow stoichiometry. For example, an amorphous structure may be employed.

[0029] Subsequently, on the gate insulating layer 12, the gate electrode layer 13 is formed by methods such as a sputtering method, a PLD method, and an electron beam deposition method. After that, the gate insulating layer and the gate electrode layer 13 are patterned by a photolithography method and an etching method. As the gate electrode layer 13, an amorphous oxide semiconductor layer containing at least one kind of element selected from among In, Ga, Zn, and Sn is preferred to be used. The gate electrode layer 13 may be formed of a laminate of a metal electrode material made of a metal such as Ti, Pt, Au, Ni, Al, and Mo and alloys of those metal elements, or a laminate film of the metal electrode materials, and an electrode material such as an oxide conductor including ITO. In this case, any one of the electrode materials may be the upper layer.

[0030] Next, on the oxide semiconductor layer 11 (on regions which become the source and drain regions 11b of the oxide semiconductor layer) and on the gate electrode layer 13, the protective layer 14 is formed. The protective layer 14 is required to have a function of reducing resistance of regions of the oxide semiconductor layer 11 in which the gate electrode layer 13 is not formed on its upper side (the regions which become the source and drain regions 11b of the oxide semiconductor layer), and the gate electrode layer 13 made of an oxide semiconductor. The resistance of the oxide semiconductor may be reduced by adding hydrogen, and hence as the protective layer 14, an insulating layer containing hydrogen is preferred to be used. Specifically, it is preferred to use a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or a silicon carbide film containing hydrogen, or a laminate thereof. Those insulating layers raise no problems even when the compositions of the insulating layers do not follow stoichiometry. A plasma-enhanced CVD method that uses a raw material gas containing hydrogen is desired as a method of forming the protective layer 14, in light of the plasma's effect of accelerating hydrogen diffusion into an oxide semiconductor. At this time, hydrogen in the raw material diffuses into the regions of the oxide semiconductor layer 11 in which the gate electrode layer 13 is not formed on its upper side (the regions which become the source and drain regions 11b of the oxide semiconductor layer) and into the gate electrode layer 13. With this diffusion, the resistance of the regions of the oxide semiconductor layer 11 in which the gate electrode layer 13 is not formed on its upper side is reduced, and at the same time, the resistance of the gate electrode layer 13 is reduced. Further, at this time, in the regions of the oxide semiconductor layer 11 in which the gate electrode layer 13 is not formed on its upper side, with the use of the gate insulating layer 12 and the gate electrode layer 13 as a mask, the source and drain regions 11b of the oxide semiconductor layer are formed in a self-alignment manner. That is, a source electrode layer and a drain electrode layer are formed. In this case, the channel region 11a of the oxide semiconductor layer and the source and drain regions 11b of the oxide semiconductor layer are formed of the same oxide semiconductor layer 11. Accordingly, a TFT that has small parasitic capacitance can be manufactured. Note that, the source and drain regions 11b of the oxide semiconductor layer may be separately formed by different layers, to thereby form the source and drain electrode layers. The structure of the TFT in this case is preferred to be a bottom contact structure illustrated in FIG. 2, a top contact structure illustrated in FIG. 3, or the like. As the source and drain electrode layers in this case, it is preferred to use a metal electrode material made of a metal such as Ti, Pt, Au, Ni, Al and Mo, and alloys of those metal elements, a laminate film of the metal electrode materials, or an oxide conductor such as ITO.

[0031] Subsequently, contact holes are formed in the protective layer 14 by a photolithography method and an etching method. After that, the source and drain wiring layers 15 are formed for electric connection to the outside by methods such as a sputtering method, a pulse laser deposition (PLD) method, an electron beam deposition method, and a CVD method. As the source and drain wiring layers 15, any material that has good electric conductivity can be employed, and it is preferred to use, for example, a metal electrode material made of a metal such as Ti, Pt, Au, Ni, Al and Mo, and an alloy of those metal elements, a laminate film of the metal electrode materials, or an oxide conductor such as ITO. Note that, the source and drain regions 11b of the oxide semiconductor layer can be used as the source and drain wiring layers 15 as it is.

[0032] Here, FIG. 4 illustrates the film thickness dependence of the resistivity obtained when a silicon nitride layer, which is the insulating layer containing hydrogen, is formed on the gate electrode layer made of an In—Ga—Zn—O-based amorphous oxide semiconductor (amorphous IGZO). The silicon nitride layer is formed by a PECVD method. Before the silicon nitride layer is formed, the amorphous oxide semiconductor has a resistivity of a value larger than 10⁵ Ωcm, which is a measurement limit, but by forming the silicon nitride layer, the resistance is sufficiently reduced as illustrated in FIG. 4. From FIG. 4, it is understood that when the film thickness of the gate electrode layer made of an amorphous oxide semiconductor exceeds 30 nm, the resistivity thereof increases. This shows that there is a resistivity distribution in a film thickness direction, and hence it may be said that as a portion in the amorphous oxide semiconductor film is spaced apart from the interface with the insulating layer containing hydrogen, the resistivity thereof increases. That is, the amorphous oxide semiconductor has a function of suppressing the reduction in resistance due to hydrogen diffusion.

[0033] Meanwhile, a bottom gate oxide semiconductor TFT is manufactured, in which a laminate film including a silicon oxide layer and an Mo layer being sequentially formed is formed on the amorphous oxide semiconductor. At this time, the silicon oxide layer and the Mo layer have a film thickness of 300 nm and 200 nm, respectively. The silicon oxide layer and the Mo layer are formed by a PECVD method and a sputtering method, respectively. FIG. 5 illustrates Id-Vg characteristics of cases before and after the silicon nitride layer, which is the insulating layer containing hydrogen, is formed on this TFT. It is understood from FIG. 5 that even if the silicon oxide layer having a film thickness of 300 nm and the Mo layer having the film thickness of 200 nm are present, after the silicon nitride layer is formed, the TFT cannot be turned OFF. That is, it is understood that those films cannot suppress reduction in resistance of the channel region of the oxide semiconductor layer due to the hydrogen diffusion from the silicon nitride layer. This reason is not clear, but because the Mo layer is a polycrystalline film, there is a possibility that an enhanced diffusion in grain boundaries causes this result. On the other hand, there are no grain boundaries in an amorphous oxide semiconductor. From those results and because the gate insulating layer is desired to be thin in view of the TFT characteristics, it can be said that the gate electrode layer 13 is desired to have a function of suppressing hydrogen diffusion.

[0034] Further, in a structure illustrated in FIG. 6, on the substrate 10, a storage capacitor including a lower electrode layer 24, an insulating layer 25, and an upper electrode layer 26 is formed. FIG. 7 illustrates a comparison of a leakage current density between the lower electrode layer 24 and the upper electrode layer 26, between a case where an amorphous oxide semiconductor subjected to resistance reduction is used as the upper electrode layer 26 and a case where a metal is used as the upper electrode layer 26. In this case, a Ti/Au/Ti layer and a silicon oxide layer are used as the lower electrode layer 24 and the insulating layer 25, respectively. As illustrated in FIG. 6, it is understood that when an amorphous oxide semiconductor layer is used on a side of the upper electrode layer 26 of the storage capacitor provided in contact to the insulating layer, the leakage current density between the lower electrode layer 24 and the upper electrode layer 26 is smaller. From the description above, an effect may be expected that, even when an amorphous oxide semiconductor layer subjected to resistance reduction as described above is used as the gate electrode layer in the top gate TFT, the leakage current density of the gate insulating layer is reduced.

[0035] The oxide semiconductor TFT having the top gate coplanar structure is thus completed. In the present invention, multiple transistors structured as above can be arranged two-dimensionally on the substrate (arranged in crosswise and lengthwise directions as if forming a plane).

[0036] Hereinafter, examples of the present invention are described in detail, but the present invention is in no way limited by the examples.

[0037] FIG. 1 illustrates an oxide semiconductor TFT having a top gate coplanar structure according to this example.

[0038] First, on the glass substrate 10, an amorphous IGZO film having a film thickness of 30 nm was formed as the oxide semiconductor layer 11 by a sputtering method. In order to form the oxide semiconductor layer 11, a DC sputtering apparatus was used and the substrate temperature was set to room temperature (25° C.). A target of a polycrystalline sintered body having an InGaZnO₄ composition was used with the input DC power set to 300 W. During the film formation, the atmosphere was set to a total pressure of 0.5 Pa and the gas flow rate at that time was set to Ar:O₂=98:2. After that, the oxide semiconductor layer 11 was patterned by a photolithography method and an etching method.

[0039] Next, on the oxide semiconductor layer 11 (on the channel region 11a of the oxide semiconductor layer), a silicon oxide film having a thickness of 100 nm was formed as the gate insulating layer 12 by a sputtering method. The silicon oxide film was formed at room temperature using an RF sputtering apparatus. A 4-inch diameter SiO₂ target was used with the input RF power set to 500 W. During the film formation, the atmosphere was set to a total pressure of 0.5 Pa and the gas flow rate at that time was set to Ar:O₂=90:10.

[0040] Subsequently, on the gate insulating layer 12, an amorphous IGZO film having a film thickness of 200 nm was formed as the gate electrode layer 13 by a sputtering method. In order to form the gate electrode layer 13, the DC sputtering apparatus was used and the substrate temperature was set to room temperature (25° C.). A target of a polycrystalline sintered body having an InGaZnO₄ composition was used with the input DC power set to 150 W. During the film formation, the atmosphere was set to a total pressure of 0.5 Pa and the gas flow rate at that time was set to Ar:O₂=80:20. After that, the gate insulating layer 12 and the gate electrode layer 13 were patterned by a photolithography method and an etching method.

[0041] Next, on the oxide semiconductor layer 11 (on regions which become the source and drain regions 11b of the oxide semiconductor layer) and on the gate electrode layer 13, a silicon nitride film containing hydrogen having a film thickness of 300 nm was formed as the protective layer 14 by a plasma-enhanced CVD method. The substrate temperature was set to 150° C. in this plasma-enhanced CVD method for forming the silicon nitride film. SiH₄, NH₃, and N₂ were used as a process gas. The gas flow rate was set to SiH₄:NH₃:N₂=1:2.5:25. The input RF power density and the pressure were set to 0.9 W/cm² and 150 Pa, respectively. Further, simultaneously with the formation of the protective layer 14, the resistance of the regions of the oxide semiconductor layer 11, in which the gate electrode layer 13 is not formed on its upper side, was reduced, to thereby become the source and drain regions 11b of the oxide semiconductor layer. Further, the resistance of the gate electrode layer 13 was reduced.

[0042] Finally, contact holes were formed in the protective layer 14 by a photolithography method and an etching method. Then, an Mo film having a film thickness of 100 nm was formed as the source and drain wiring layers 15. After that, the source and drain wiring layers 15 were patterned by a photolithography method and an etching method.

[0043] Through the above-mentioned steps, the oxide semiconductor TFT of this example was completed.

[0044] In this example, an amorphous oxide semiconductor having a film thickness of 200 nm was formed as the gate electrode layer 13 of the top gate TFT, and on the gate electrode layer 13, a silicon nitride film containing hydrogen having a film thickness of 300 nm was formed as the protective layer 14. In this manner, as described with reference to FIGS. 4 and 7, it was possible to suppress reduction in resistance of the channel region 11a of the oxide semiconductor layer due to hydrogen diffusion, and was also possible to reduce the leakage current density of the gate insulating layer 12.

[0045] FIG. 2 illustrates an oxide semiconductor TFT having a top gate bottom contact structure according to this example.

[0046] First, on the glass substrate 10, an Mo film having a film thickness of 200 nm was formed as source and drain electrode layers 11c. After that, the source and drain electrode layers 11c were patterned by a photolithography method and an etching method.

[0047] Next, in the same manner as in Example 1, the oxide semiconductor layer 11 (channel region of the oxide semiconductor layer) and the gate insulating layer 12 were sequentially formed.

[0048] Subsequently, on the gate insulating layer 12, an amorphous IGZO film having a film thickness of 200 nm was formed as the gate electrode layer 13 by a sputtering method. The gate electrode layer 13 was formed at room temperature (25° C.) using a DC sputtering apparatus. A target of a polycrystalline sintered body having an InGaZnO₄ composition was used with the input DC power set to 150 W. During the film formation, the atmosphere was set to a total pressure of 0.5 Pa and the gas flow rate at that time was set to Ar:O₂=80:20. After that, the gate electrode layer 13 was patterned by a photolithography method and an etching method.

[0049] Next, in the same manner as in Example 1, the protective layer 14 was formed. With the formation of the protective layer 14, the resistance of the gate electrode layer 13 was reduced.

[0050] Finally, contact holes were formed in the protective layer 14 by a photolithography method and an etching method. Then, an Mo film having a film thickness of 100 nm was formed as the source and drain wiring layers 15. After that, the source and drain wiring layers 15 were patterned by a photolithography method and an etching method.

[0051] Through the above-mentioned steps, the oxide semiconductor TFT of this example was completed.

[0052] In this example, an amorphous oxide semiconductor having a film thickness of 200 nm was formed as the gate electrode layer 13 of the top gate TFT, and on the gate electrode layer 13, a silicon nitride film containing hydrogen having a film thickness of 300 nm was formed as the protective layer 14. In this manner, as described with reference to FIGS. 4 and 7, similarly to Example 1, it was possible to suppress reduction in resistance of the oxide semiconductor layer 11 (channel region of the oxide semiconductor layer) due to hydrogen diffusion, and was also possible to reduce the leakage current density of the gate insulating layer 12.

[0053] FIG. 8 illustrates an oxide semiconductor TFT having a double gate coplanar structure according to this example.

[0054] First, on the glass substrate 10, an Mo film having a film thickness of 200 nm was formed as a bottom gate electrode layer 20. After that, the bottom gate electrode layer 20 was patterned by a photolithography method and an etching method.

[0055] Next, on the glass substrate 10 and on the bottom gate electrode layer 20, a silicon oxide film having a film thickness of 200 nm was formed as a lower gate insulating layer 21 by a plasma-enhanced CVD method. The substrate temperature was set to 340° C. in this plasma-enhanced CVD method for forming the silicon oxide film. SiH₄ and N₂O were used as a process gas. The gas flow rate was set to SiH₄:N₂O=1:25. The input RF power density and the pressure were set to 0.9 W/cm² and 173 Pa, respectively.

[0056] Next, in the same manner as in Example 1, the oxide semiconductor layer 11 was formed.

[0057] Subsequently, on the oxide semiconductor layer 11 (on the channel region 11a of the oxide semiconductor layer), a silicon oxide film having a film thickness of 100 nm was formed as an upper gate insulating layer 22 by a sputtering method. The upper gate insulating layer 22 was formed at room temperature (25° C.) using an RF sputtering apparatus. A target of SiO₂ was used with the input RF power set to 500 W. During the film formation, the atmosphere was set to a total pressure of 0.5 Pa and the gas flow rate at that time was set to Ar:O₂=90:10.

[0058] Next, contact holes (not shown in FIG. 8) were formed in the lower gate insulating layer 21 and the upper gate insulating layer 22 by a photolithography method and an etching method.

[0059] Subsequently, on the upper gate insulating layer 22, an amorphous IGZO film having a film thickness of 200 nm was formed as a top gate electrode layer 23 by a sputtering method. In order to form the top gate electrode layer 23, the DC sputtering apparatus was used and the substrate temperature was set to room temperature (25° C.). A target of a polycrystalline sintered body having an InGaZnO₄ composition was used with the input DC power set to 150 W. During the film formation, the atmosphere was set to a total pressure of 0.5 Pa and the gas flow rate at that time was set to Ar:O₂=80:20. The bottom gate electrode layer 20 and the top gate electrode layer 23 are electrically connected to each other via the above-mentioned contact holes. After that, the upper gate insulating layer 22 and the top gate electrode layer 23 were patterned by a photolithography method and an etching method, by employing backside exposure which uses the bottom gate electrode layer 20 as a mask. By employing backside exposure which uses the bottom gate electrode layer 20 as a mask, the top gate electrode layer 23 was patterned in an almost self-alignment manner with respect to the bottom gate electrode layer 20.

[0060] Next, in the same manner as in Example 1, the protective layer 14 was formed. Simultaneously with the formation of the protective layer 14, the resistance of the regions of the oxide semiconductor layer 11, in which the top gate electrode layer 23 is not formed on the upper side, was reduced, to thereby become the source and drain regions 11b of the oxide semiconductor layer. In addition, the resistance of the top gate electrode layer 23 was reduced. The source and drain regions 11b of the oxide semiconductor layer were formed in an almost self-alignment manner with respect to the bottom gate electrode layer 20, and in a self-alignment manner with respect to the top gate electrode layer 23.

[0061] Finally, contact holes were formed in the protective layer 14 by a photolithography method and an etching method. Then, an Mo film having a film thickness of 100 nm was formed as the source and drain wiring layers 15. After that, the source and drain wiring layers 15 were patterned by a photolithography method and an etching method.

[0062] Through the above-mentioned steps, the oxide semiconductor TFT of this example was completed.

[0063] In this example, an amorphous oxide semiconductor having a film thickness of 200 nm was formed as the upper gate electrode layer 23 of the double gate TFT, and on the upper gate electrode layer 23, a silicon nitride film containing hydrogen having a film thickness of 300 nm was formed as the protective layer 14. In this manner, as described with reference to FIGS. 4 and 7, similarly to Examples 1 and 2, it was possible to suppress reduction in resistance of the channel region 11a of the oxide semiconductor layer due to hydrogen diffusion, and was also possible to reduce the leakage current density of the gate insulating layer 12.

[0064] FIG. 9 illustrates a display apparatus according to this example, which is a display apparatus including an oxide semiconductor TFT having a top gate coplanar structure and a display device. The oxide semiconductor TFT was manufactured in the same manner as in Example 1. Note that, the oxide semiconductor TFT illustrated in any one of FIGS. 1 to 3 and FIG. 8 may be used.

[0065] First, on an oxide semiconductor TFT 120 of the present invention, a silicon nitride film was formed as an insulating layer 121 by a plasma-enhanced CVD method. After that, a contact hole was formed in the insulating layer 121 by a photolithography method and an etching method. Next, on the insulating layer 121, an ITO film was formed as an electrode layer 123 by a sputtering method, which is connected to a source wiring layer 122 through intermediation of the insulating layer 121. After that, on the electrode layer 123, a hole transport layer 124 and a light-emitting layer 125 were formed by a deposition method. α-NPD and Al_q3 are used for the hole transport layer 124 and the light-emitting layer 125, respectively. Finally, an MgAg film was formed on the light-emitting layer 125 as the electrode layer 126 by a deposition method.

[0066] Through the above-mentioned steps, the display apparatus of this example was completed, which includes the oxide semiconductor TFT of the present invention and an organic electro-luminescence element as the display device, and in which the source electrode layer or the drain electrode layer of the TFT is electrically connected to the display device.

[0067] While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions.

[0068] This application claims the benefit of Japanese Patent Application No. 2010-174234, filed Aug. 3, 2010, which is hereby incorporated by reference herein in its entirety.