Bonding of substrates including metal-dielectric patterns with metal raised above dielectric and structures so formed

[0001] This application is a divisional of U.S. patent application Ser. No. 11/532,599, which received a Notice of Allowance on Apr. 3, 2012, and is hereby incorporated by reference in its entirety.

[0002] This invention was made with government support under contract numbers: N66001-00-C-8003 and N66001-04-C-8032 of the Defense Advanced Research Projects Agency (DARPA). The government has certain rights to this invention.

[0003] 1. Technical Field

[0004] The invention generally relates to the integrated circuit fabrication and, more specifically, to bonding of substrates having metal-dielectric patterns.

[0005] 2. Background Art

[0006] In the integrated circuit fabrication industry, substrate bonding is used to join various parts of an integrated circuit (IC) together. Thermal-compression bonding is one type of bonding that is advantageous because it allows the use of metals at the bonding interface rather than just dielectrics. The metallic surface serves as a good bonding medium, and also provides additional functionality such as electrical signal propagation and thermal spreading. Unfortunately, thermal compression bonding presents many challenges in order to achieve a good quality bond.

[0007] One challenge is optimizing process parameters. Process parameters may include, for example, surface preparation before bonding such as cleans and wetting treatments, process conditions during bonding such as temperature, pressure, force, time, etc., and post-bonding treatments such as thermal cycles.

[0008] Another challenge is addressing patterned metal-dielectric mating surfaces that typically include topography, which prevents a reliable bond. In particular, metal-dielectric patterning is conventionally formed using damascene processing. Damascene processing involves fabricating interconnect metal lines by forming and filling trenches in a dielectric, and attempting to planarize the surface by chemical-mechanical polishing (CMP). Bonding of patterned surfaces takes place after the CMP step. CMP, however, leaves the metal surface non-uniform, e.g., the metal is typically concave and non-planar relative to the dielectric. As a result, the topographical differences between bonding metallic surfaces presents a challenge. Conventionally, the heating process during the bonding, which causes the reflow of the metallic pattern, has been considered sufficient to cause bonding. Unfortunately, the non-uniformity and the difference in the distances between bonding metallic surfaces does not always allow for adequate bonding via reflow, resulting in low yields.

[0009] Bonding of substrates including metal-dielectric patterns on a surface with the metal raised above the dielectric is disclosed. One method includes providing a first substrate having a metal-dielectric pattern on a surface thereof; providing a second substrate having a metal-dielectric pattern on a surface thereof; performing a process resulting in the metal being raised above the dielectric in at least one of the substrates; cleaning the metal; and bonding the first substrate to the second substrate. A related structure is also disclosed. The bonding of raised metal provides a strong bonding medium, and good electrical and thermal connections enabling creation of three dimensional integrated structures with enhanced functionality.

[0010] A first aspect of the invention includes a method comprising: providing a first substrate having a metal-dielectric pattern on a surface thereof; providing a second substrate having a metal-dielectric pattern on a surface thereof; performing a process resulting in the metal being raised above the dielectric in at least one of the substrates; cleaning the metal; and bonding the first substrate to the second substrate.

[0011] A second aspect of the invention includes a structure comprising: a substrate including a dielectric having a metal therein, the metal extending above a surface of the dielectric and including an upper surface having at least a portion thereof in a substantially convex form.

[0012] A third aspect of the invention includes a method comprising: providing a first substrate having a metal-dielectric pattern on a surface thereof; providing a second substrate having a metal-dielectric pattern on a surface thereof; recessing the dielectric in at least one of the substrates by performing chemical mechanical polishing of the dielectric, and performing an etch; cleaning the metal; bonding the first substrate to the second substrate; and annealing the first substrate and the second substrate.

[0013] A fourth aspect of the invention includes a method comprising: providing a first substrate including a dielectric having a metal-dielectric pattern on a surface thereof with metal recessed; providing a second substrate having a metal-dielectric pattern on a surface thereof with dielectric recessed below metal by performing chemical mechanical polishing of the dielectric, and performing an etch; providing the lock-n-key ability, then cleaning the metal surface; bonding the first substrate to the second substrate; and annealing the bonded stack.

[0014] A fifth aspect of the invention includes a structure having: a first substrate having a metal-dielectric pattern on a surface thereof, the metal-dielectric pattern including: a metal having a concave upper surface; and a dielectric having a substantially uniform upper surface, wherein the metal on the first substrate is raised above the dielectric on the first substrate; and a second substrate bonded with the first substrate, the second substrate including: a dielectric; and a metal positioned substantially below the dielectric below the dielectric of the second substrate, wherein the first substrate and the second substrate are bonded at the metal from the first substrate and the metal from the second substrate.

[0015] A sixth aspect of the invention includes a structure having: a first substrate having a metal-dielectric pattern on a surface thereof, the metal-dielectric pattern including: a metal having a convex-dome shape; and a dielectric having a substantially uniform upper surface, wherein the metal on the first substrate is raised above the dielectric on the first substrate; and a second substrate bonded with the first substrate, the second substrate including: a dielectric; and a metal positioned substantially below the dielectric below the dielectric of the second substrate, wherein the first substrate and the second substrate are bonded at the metal from the first substrate and the metal from the second substrate.

[0016] The illustrative aspects of the present invention are designed to solve the problems herein described and/or other problems not discussed.

[0031] It is noted that the drawings of the invention are not to scale. The drawings are intended to depict only typical aspects of the invention, and therefore should not be considered as limiting the scope of the invention. In the drawings, like numbering represents like elements between the drawings.

[0032] Turning to the drawings, FIGS. 1-9 show one embodiment of a method of bonding according to the invention. FIG. 1 shows a substrate 100 having a metal-dielectric pattern 102 on a surface 104 thereof. As will be described herein, two substrates 100 having metal-dielectric patterns 102 will ultimately be provided and bonded together. Metal-dielectric pattern 102 includes a metal 110 such as a wire or contact positioned within a dielectric 112. It is understood that the layout of metal 110 within the different substrates may vary according to the functioning of the integrated circuit (IC) formed thereby. Metal 110 may include any now known or later developed metallic material 114, e.g., copper, tungsten, aluminum, etc., or combination thereof. In addition, metal 110 may include an oxide layer 116 thereover, e.g., where it has been exposed to the environment. Dielectric 112 may include any now known or later developed insulator material usable in bonded substrates 100, e.g., silicon dioxide (SiO₂), silicon nitride (Si₃N₄) or low-k dielectrics.

[0033] Substrate 100 may be formed using any now known or later developed techniques such as damascene processing, chemical mechanical polishing (CMP), etc. As shown in FIG. 1, metal 110 has a concave upper surface 118 caused by CMP, which may exist in oxide layer 116 and/or metallic material 114. Each substrate 100 may be exposed to CMP. Other layers 120 such as other interconnect layers, a silicon substrate, etc., may be provided under metal-dielectric pattern 102.

[0034] Next, a process is performed resulting in metal 110 being raised above dielectric 112 in at least one of substrates 100 that will be bonded together. FIGS. 2-3 show one embodiment of this process in which dielectric 112 is recessed. This embodiment may include one or more processes. FIG. 2 shows one process in which dielectric 112 is chemical mechanical polished (CMP) 130 to recess dielectric 112. FIG. 4A shows a graph illustrating a height of metal 110 compared to dielectric 112 according to one illustrative structure exposed to the CMP of FIG. 2 alone. FIG. 3 shows another process in which dielectric 112 is exposed to a wet etch 134 to recess dielectric 112. In one embodiment, where dielectric 112 includes silicon dioxide (SiO₂), wet etch 134 may include a diluted hydrofluoric acid (HF) etch; however, other etch process are also considered within the scope of the invention. FIG. 4B shows a graph illustrating a height of metal 110 compared to dielectric 112 according to one illustrative structure exposed to wet etch 134 of FIG. 3 alone. In another embodiment, substrate 100 is exposed to both CMP 130 of FIG. 2 and wet etch 134 of FIG. 3. FIG. 4C shows a graph illustrating a height of metal 110 compared to dielectric 112 according to one illustrative structure exposed to CMP 130 of FIG. 2 and wet etch 134 of FIG. 3. FIGS. 4A-4C show that metal 110 is raised above dielectric 112, and may include an upper surface 135 having at least a portion 136 thereof in a substantially convex form, e.g., rounded off. (Upper surface 135 is labeled in FIGS. 2 and 3 also, but the substantially convex form is not as recognizable due to limitations of the drawings.) In some instances, upper surface 135 may have a substantially domed shape 138, as shown best in FIG. 4C. In either case, any concave upper surface 118 (FIG. 1) is removed in this process, which fosters better metal-to-metal bonding.

[0035] FIG. 5 shows cleaning 140 of metal 110, e.g., etching of any oxide layer 116 (FIGS. 1-3) off of metal 110. The etching may include any now known or later developed etching technique for removing any dielectric used (e.g., silicon dioxide, silicon nitride) from a metal, e.g., a reactive ion etch, a wet etch, etc.

[0036] FIG. 6 shows an optional process of performing a metal surface neutralization process. In one embodiment, this process may include forming a layer 142 of benzotriazole (BTA) on metal 110. BTA layer 142 prevents further oxidation.

[0037] FIGS. 7-8 show bonding a first substrate 100A to a second substrate 100B. As shown in FIG. 7, each of substrates 100A, 100B have been exposed to the above described process. However, it is understood that it may be possible to carry out the bonding with only one of substrates 100A, 100B exposed to the process to raise metal 110 above dielectric 112, described herein. Bonding may include any now known or later developed thermal compression techniques. BTA layer 142 (FIG. 6) dissolves at high temperature. FIG. 8 shows a completed bonded structure 160 including first substrate 100A coupled to second substrate 100B by metal 110 of each respective substrate. In this case, bonding includes bonding only metal 110 of first substrate 100A and second substrate 100B because dielectric 112 is substantially recessed. As a result, a gap 162 is present between dielectric 112 of each respective substrate.

[0038] FIG. 9 shows a bonded structure 168 after an optional annealing 166. As shown in FIG. 8, typically, a low temperature (<400° C.) quick (<1 hr) thermo-compression bonding (FIG. 7) results in a clearly visible interface (or seam) 164 between metal 110 of each respective substrate 100A, 100B. An optimized post-bond annealing 166 provides the time and temperature needed for the interfacial grain growth enabling seam free interface (FIG. 9). In addition, annealing 166 allows for lower thermo-compression bond temperatures (FIG. 7) and higher process load/through-put through the bonding process (FIG. 7-8) because substrates 100A, 100B can be processed in a batch (parallel processing) through annealing 166. Annealing 166 may therefore improve the yield of the bonding process and can be utilized to improve manufacturability of bonded structures 160, 168.

[0039] Turning to FIGS. 10-11, in an alternative embodiment, substrates 100A, 100B may be processed, as described above, in an optimized manner such that, when bonded, metal 110 (with or without BTA layer 142 (FIG. 6)) and dielectric 112 bond together, i.e., gap 162 (FIGS. 8-9) is eliminated. That is, the bonding includes bonding metal 110 of first substrate 100A and second substrate 100B, and dielectric 112 of first substrate 100A and second substrate 100B. In this case, metal 110 is raised only high enough such that when bonded, dielectrics 112 bond also. Bonded structure 170 (FIG. 11) exhibits enhanced bonding strength across the whole substrates 100A, 100B compared to that of FIGS. 7-9, and prevents potential contamination in gap 162 (FIGS. 8-9). FIG. 11 shows bonded structure 170 after an optional anneal, i.e., without an interface 164 (FIG. 8). It is understood, however, that the annealing may not be necessary.

[0040] Referring to FIGS. 12-13, in an alternative embodiment, the process resulting in metal 110 being raised above dielectric 112 in at least one of substrates 100 may be provided by raising metal 110, rather than recessing dielectric 112. In this case, processing begins with substantially the same structure as shown in FIG. 1, and as shown in FIG. 12, metal 110 is cleaned (similar to cleaning 140 FIG. 5), e.g., by an etching of any oxide layer 116 (FIG. 1) off of metal 110. The etching may include any now known or later developed etching technique for removing oxide layer 116 (FIG. 1) from a metal, e.g., a reactive ion etch, a wet etch, etc.

[0041] FIG. 13 shows forming a metal cap 182 over metal 110. Metal 182 may be any metal or metal alloy compatible with metallic material 114. As known to those with skill in plating, if metallic material 114 includes copper (Cu), metal cap 182 may include any thermal compression bondable metal such as copper or a copper alloy such as tin-copper (SnCu), titanium (Ti), etc. Metal cap 182 may be formed using any now known or later developed techniques, e.g., chemical vapor deposition, atomic layer deposition, etc.

[0042] FIG. 14-16A show bonding of substrates 100A, 100B formed using the process of FIGS. 12-13. The bonding is substantially similar to that described relative to FIGS. 7-9. FIG. 15 shows a bonded structure 184 after thermo-compression bonding, with an interface 186 therein. FIG. 16A shows a bonded structure 188 after an optional anneal 190. While FIGS. 15-16 show a gap 192, it is understood that this embodiment may also employ the optimization of FIGS. 10-11 to arrive at a bonded structure 194, as shown in FIG. 17A, without a gap 192 (FIG. 16). Note, FIG. 17A also includes the optional anneal 190 (FIG. 16A) to remove interface 186 (FIG. 15). As shown FIG. 16B-17B, if metal 110 (FIG. 15) used easily diffuses into copper (Cu), then no interface may exist between the different metals, and they may meld into a unitary copper alloy.

[0043] FIGS. 18-22 show another alternative embodiment in which a metal 210 is roughened to have a roughened surface 298 prior to bonding. In some cases, where metal 210 is sufficiently high, a substantially domed shape 138 (FIG. 4C) upper surface 135 (FIG. 2) is advantageous compared to concave upper surface 118 (FIG. 1) which has raised edges. However, if metal 210 is not sufficiently raised, roughening of metal 210 to have a roughened surface 298 may aid in strengthening bonding. FIG. 18 shows roughening of metal 210 to include roughened surface 298, e.g., by etching such as RIE or a wet etch. FIG. 18 may be after the process to raise metal 210 according to any of the above-describe embodiments to raise metal 210. FIG. 18 shows metal 210 including an oxide layer 216, and FIG. 19 shows metal 210 after cleaning, e.g., etching to remove oxide layer 216 (FIG. 18) as described above relative to FIGS. 5 and 12. It is understood, however, that metal 210 may be roughened in the absence of oxide layer 216. FIG. 19 shows optional performing of a metal surface neutralization process. As described above relative to FIG. 6, this process may include forming a layer 242 of benzotriazole (BTA) on metal 210, which prevents further oxidation.

[0044] FIGS. 21-22 show bonding of substrates 200A, 200B formed according to the embodiments of FIGS. 18-20, resulting in a bonded structure 300 (FIG. 22). It is understood that while bonded structure 300 includes a gap 302 and an interface 304, it may be formed as described above relative to FIGS. 10-11 without gap 302, and/or, as described above relative to FIG. 9 without interface 304. If an optional anneal is performed, then interface 304 may be removed.

[0045] FIGS. 23-24 show another alternative embodiment in which substrates 300A, 300B may be bonded in an interlocking fashion. In this case, two substrates 300A, 300B each having substantially similar structure to that shown in FIG. 1 may be provided. Here, as shown in FIG. 23, one substrate 300A is processed according to one of the embodiments above to raise metal 110 above dielectric 112. A BTA layer 142 may or may not be provided on metal 110. In addition, a substrate 300B having a structure substantially similar to FIG. 1 may be provided. As shown in FIG. 24, substrate 300B is processed to raise dielectric 112 above metal 110, which may or may not include oxide layer 116. Dielectric 112 may be raised by deposition of more dielectric in any manner, e.g., masking metal 110 and deposition, or by recessing of metal 110 in any manner, e.g., masking dielectric 112 and etching metal 110. In one embodiment, metal 110 of substrate 300B may be wider than metal 110 of substrate 300A to accommodate mating, i.e., the opening in dielectric 112 is larger in substrate 300B. In one alternative embodiment, where necessary, dielectric 112 and/or metal 110 of substrate 300B may form an angled opening 103 to assist in mating with metal of substrate 300A. However, this may not be necessary in all instances. Substrates 300A, 300B may then be bonded according to any one of the above described embodiments such that metals 110 thereof interlock between dielectrics 112 thereof.

[0046] Returning to FIGS. 3 and 4C, in another embodiment, the invention may include a structure including substrate 100 including dielectric 112 having metal 110 therein. As described above, metal 110 extends above surface 104 of dielectric 112 and include an upper surface 135 having at least a portion 136 thereof in a substantially convex form. As shown in FIG. 4C, upper surface 135 (FIG. 3) may be substantially dome shaped 138.

[0047] The method as described above may be used in the fabrication of integrated circuit chips. In addition, the method may be employed in bonding of mechanical components, e.g., micro-electrical mechanical systems (MEMS), or optical components, such as a micro-optical bench. In the case of IC chips, the resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). Regardless of the method, the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.

[0048] The foregoing description of various aspects of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and obviously, many modifications and variations are possible. Such modifications and variations that may be apparent to a person skilled in the art are intended to be included within the scope of the invention as defined by the accompanying claims.