Semiconductor device and method for fabricating the same

[0001] 1. Field of Invention

[0002] This invention relates to a semiconductor device and a method for fabricating the semiconductor device.

[0003] 2. Description of Related Art

[0004] The semiconductor devices in an integrated circuit usually include metal-oxide-semiconductor (MOS) transistors and polysilicon resistors, wherein the gates of the MOS transistors and the polysilicon resistors are usually at the same level.

[0005] A method for fabricating such an integrated circuit includes the following steps. After contact openings are formed over the source/drain (S/D) regions, a metal salicide (self-aligned silicide) layer is formed on the S/D regions in the contact openings, and then the contact openings are filled by a metal material to form S/D contacts. M0 metal contacts are then formed to contact the gates of the MOS transistors, the S/D contacts and the polysilicon resistors.

[0006] Because a metal salicide layer is not formed on the polysilicon resistors, the M0 metal contacts over the polysilicon resistors directly contact the polysilicon resistors. Thus, the contact sheet resistance between a polysilicon resistor and the corresponding M0 metal contact is large.

[0007] Accordingly, this invention provides a method for fabricating a semiconductor device, which can reduce the contact sheet resistance between a polysilicon resistor and the corresponding metal contact.

[0008] This invention also provides a semiconductor device that is fabricated using the method of this invention.

[0009] The method for fabricating a semiconductor device of this invention is described below. A substrate having thereon a polysilicon resistor is provided. A dielectric layer is formed over the substrate covering the polysilicon resistor. The dielectric layer is etched to form a contact opening over the polysilicon resistor, with overetching into the polysilicon resistor. A metal silicide layer is formed on the polysilicon resistor in the contact opening. A metal material is filled in the contact opening. A portion of the dielectric layer, the metal material, and a portion of the polysilicon resistor are removed to expose the metal silicide layer. A metal contact is then formed over the metal silicide layer.

[0010] The above process can be integrated with a contact process of a MOS transistor. In the integrated process, the substrate provided further has thereon a gate and S/D regions beside the gate, the dielectric layer formed over the substrate further covers the gate and the S/D regions, additional contact openings are formed over the S/D regions by etching the dielectric layer, the metal silicide layer is also formed on the S/D regions in the additional contact openings, the metal material is also filled in the additional contact openings, portions of the metal material remain in the additional contact openings over the S/D regions to serve as S/D metal contacts, and additional metal contacts are formed over the gate and the S/D metal contacts.

[0011] The semiconductor device of this invention includes a polysilicon resistor, a first metal contact on the polysilicon resistor, and a first metal silicide layer disposed and electrically connected between the polysilicon resistor and the first metal contact.

[0012] With the integration of a contact process of a MOS transistor, the semiconductor device can further include a gate, S/D regions beside the gate, S/D metal contacts on the S/D regions, a second metal silicide layer disposed between the S/D regions and the S/D metal contacts and formed simultaneously with the first metal silicide layer, and second metal contacts disposed on the S/D metal contacts and the gate of the MOS transistor and formed simultaneously with the first metal contact.

[0013] For a metal silicide layer is formed or disposed between the polysilicon resistor and the corresponding metal contact, the contact sheet resistance between the poly-Si resistor and the corresponding metal contact can be reduced.

[0014] In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, a preferred embodiment accompanied with figures is described in detail below.

[0016] It is noted that the following embodiment is intended to further explain this invention but not to limit its scope. For example, though the substrate illustrated in the embodiment is a bulk substrate, it may alternatively be a semiconductor-on-insulator (SOI) substrate.

[0017] FIGS. 1A-1D illustrate, in a cross-sectional view, a method for fabricating a semiconductor device according to an embodiment of this invention.

[0018] Referring to FIG. 1A, a semiconductor substrate 100 is provided, having thereon a polysilicon resistor 102, and a gate 104 of a MOS transistor. The substrate 100 may include lightly doped single-crystal or epitaxial silicon. The polysilicon resistor 102 is usually formed on a device isolation layer 106, which may be a shallow trench isolation (STI) layer. The gate 104 may include metal or doped polysilicon, possibly disposed on a gate oxide layer or a high-K gate dielectric layer on the substrate 100. When the gate 104 is a metal gate, it may include a work-function metal layer and a low-resistance metal layer (not shown), and may have a liner layer and a spacer, etc., on the sidewall thereof (not shown). The S/D regions 108 of the MOS transistor are formed in the substrate 100 at both sides of the gate 104, possibly including silicon, or a semiconductor compound containing silicon.

[0019] Thereafter, a dielectric layer 110 is formed over the substrate 100 covering the polysilicon resistor 102, the gate 104 and the S/D regions 108. The dielectric layer 110 may include at least one dielectric film selected from a silicon oxide film, a silicon nitride (SiN) film, a SiC film, a SiCN film, a low-k material film and so on, and may be formed with PECVD or a spin-on glass (SOG) method, etc. A plurality of contact openings 112a and 112b are then formed in the dielectric layer 110 by anisotropic etching, wherein the contact openings 112a are formed over the polysilicon resistor 102 and the contact openings 112b formed over the S/D regions 108, and overetching into the polysilicon resistor 102 occurs in the corresponding contact openings 112a due to the higher top surface of the polysilicon resistor 102. The number of the contact openings 112a is not limited to two. In addition, each of the contact openings 112a may have a slot shape in the top view.

[0020] Moreover, though overetching into the polysilicon resistor 102 occurs in the corresponding contact openings 112a due to the higher top surface of the polysilicon resistor 102 in the above embodiment, in another embodiment, such overetching may be prevented by forming a contact etching stop layer (CESL, not shown) covering the gate 104, the polysilicon resistor 102 and so on before the dielectric layer 110 is formed. In the forming process of the contact openings in such an embodiment, after the etching through the dielectric layer 110 is stopped by the CESL, the exposed portions of the CESL are removed possibly by wet etching.

[0021] Referring to FIG. 1B, a metal silicide layer 114a/b is formed on the polysilicon resistor 102 and the S/D regions 108 in the contact openings 112a and 112b. The metal silicide layer 114a/b may include nickel silicide (NiSi), cobalt silicide (CoSi) or titanium silicide (TiSi), and may be formed with a self-aligned silicide (salicide) process. The salicide process typically includes depositing a metal, reacting the metal with the silicon in the polysilicon resistor 102 and the S/D regions 108, and removing the unreacted metal. Thereafter, a layer of a metal material 116 is formed filling up the contact openings 112a and 112b, possibly through sputtering. The metal material 116 may include tungsten, copper or any metal material with suitable resistance and gap-fill capability. In addition, a barrier layer (not shown), such as a TiN layer, can be formed between the metal material 116 and the dielectric layer 110, if required.

[0022] Referring to FIGS. 1B-1C, a portion of the metal material 116, a portion of the dielectric layer 110, a portion of the polysilicon resistor 102 and a portion of the gate 104 are removed to expose the metal silicide layer 114a on the polysilicon resistor 102 wherein portions of the metal material 116 remain in the contact openings 112b over the S/D regions 108 to serve as S/D metal contacts 116a. The removal process may include a planarization process, such as a chemical mechanical polishing (CMP) process. After the planarization process, the top surface of the remaining dielectric layer 110a, the top surface of the remaining gate 104, the top surfaces of the S/D metal contacts 116a and the top surface of the remaining polysilicon resistor 102a are substantially coplanar with each other.

[0023] Referring to FIG. 1D, another dielectric layer 120 is formed over the resulting structure, and then a plurality of metal contacts 122 are formed respectively over the metal silicide layer 114a on the polysilicon resistor 102, over the gate 104, and over the S/D metal contacts 116a. The metal contacts 122 may include tungsten, copper or any metal material with suitable resistance and gap-fill capability, and may be formed by etching the dielectric layer 120 to form corresponding contact holes, depositing a metal material filling up the contact holes and then removing the metal material outside of the contact holes. In addition, a barrier layer (not shown), such as a TiN layer, can be formed between the metal contacts 122 and the dielectric layer 120, if required.

[0024] Moreover, though the dielectric layer 120 shown in FIG. 1D is directly formed over the previously resulting structure in the above embodiment, this invention is not limited thereto. For example, a relatively thin cap layer can be formed on the resulting structure prior to the dielectric layer 120. In the forming process of contact openings in such embodiment, after the etching through the dielectric layer 120 reaches the cap layer, the exposed portions of the cap layer can be removed by wet etching.

[0025] FIG. 1D also illustrates a semiconductor device according to this embodiment. The semiconductor device includes a polysilicon resistor 102a, a first metal contact 122 on the polysilicon resistor 102a, and a first metal silicide layer 114a disposed and electrically connected between the polysilicon resistor 102a and the first metal contact 122, and further includes a gate 104, S/D regions 108 in the substrate 100 at both sides of the gate 104, S/D metal contacts 116a on the S/D regions 108, a second metal silicide layer 114b disposed between the S/D regions 108 and the S/D metal contacts 116a and formed simultaneously with the first metal silicide layer 114a, and other second metal contacts 122 disposed on the S/D metal contacts 116a and the gate 104 and formed simultaneously with the first metal contact 122.

[0026] The polysilicon resistor 102 is usually disposed on a device isolation layer 106. The top surface of the gate 104, the top surfaces of the S/D metal contacts 116a and the top surface of the polysilicon resistor 102a may be substantially coplanar with each other. The material of each of the above parts of the semiconductor device can be the same as the corresponding material mentioned above.

[0027] Because a metal silicide layer is formed or disposed between the polysilicon resistor and the corresponding metal contact in the above embodiment, the contact sheet resistance between the polysilicon resistor and the corresponding metal contact can be reduced.

[0028] This invention has been disclosed above in the preferred embodiments, but is not limited to those. It is known to persons skilled in the art that some modifications and innovations may be made without departing from the spirit and scope of this invention. Hence, the scope of this invention should be defined by the following claims.