US 8,536,713 B2Grant
System in package with heat sink
Issue Date:2013-09-17
•31 Claims
•11 Drawing Sheets
Abstract
Some embodiments of the invention provide a programmable system in package (“PSiP”). The PSiP includes a single IC housing, a substrate and several IC's that are arranged within the single IC housing. At least one of the IC's is a configurable IC. In some embodiments, the configurable IC is a reconfigurable IC that can reconfigure more than once during run time. In some of these embodiments, the reconfigurable IC can be reconfigured at a first clock rate that is faster (i.e., larger) than the clock rates of one or more of the other IC's in the PSiP. The first clock rate is faster than the clock rate of all of the other IC's in the PSiP in some embodiments.
Metadata
Assignee
- Tabula, Inc.
Inventor
- Steven Teig
Application Information
Application Number:US 13/078,327
Filing Date:2011-04-01
Priority Date:2004-11-04
Art Unit:2815
Classifications
IPC:
H01L23/48
Patent Drawings (11 sheets)
Description
Claim of Benefit to Prior Applications
[0001] This Application is a continuation application of U.S. patent application Ser. No. 11/861,204, filed Sep. 25, 2007, now issued as U.S. Pat. No. 7,936,074. U.S. patent application Ser. No. 11/861,204 is a continuation application of U.S. patent application Ser. No. 11/081,842, filed Mar. 15, 2005, now issued as U.S. Pat. No. 7,301,242 U.S. patent application Ser. No. 11/081,842 claims benefit to U.S. Provisional Patent Application 60/625,263, filed Nov. 4, 2004, entitled “Method and Apparatus for a Programmable System in Package.” U.S. Pat. Nos. 7,936,074, 7,301,242, and U.S. Provisional Patent Application 60/625,263 are incorporated herein by reference.
Field of the Invention
[0002] The present invention is directed towards programmable system in package.
Background of the Invention
[0003] The use of configurable integrated circuits (“IC's”) has dramatically increased in recent years. One example of a configurable IC is a field programmable gate array (“FPGA”). An FPGA is a field programmable IC that has an internal array of logic circuits (also called logic blocks) that are connected together through numerous interconnect circuits (also called interconnects) and that are surrounded by input/output blocks. Like some other configurable IC's, the logic circuits and the interconnect circuits of an FPGA are configurable (i.e., they can be configured to perform different functions and operations by receiving different configuration data). One benefit of configurable IC's is that they can be uniformly mass produced and then subsequently configured to perform different operations.
[0004] Recently, some have suggested implementing an FPGA within a system on chip (“SoC”). A SoC is an IC that includes all of the necessary hardware and electronic circuitry for a complete system. The SoC is typically a small piece of semiconducting material (e.g., silicon) on which several macroblocks are embedded. Some of these macroblocks can include a memory, a microprocessor, digital signal processor, etc. A characteristic of the SoC is that it requires all the macroblocks to be manufactured with one type of fabrication technology. This can be problematic since each macroblock may have a different optimal fabrication technology (e.g., a memory macroblock might be optimally manufactured at 90 nm, while an analog macroblock might be optimally manufactured at 180 nm). As such, in some instances, some of the macroblocks of a SoC might be manufactured sub-optimally. Another drawback of a SoC is that the design process is often extensive, cumbersome and expensive.
[0005] Therefore, there is a need in the art for a better method of fabricating a configurable IC that has configurable IC operations and non-configurable IC operations within the IC.
Summary of the Invention
[0006] Some embodiments of the invention provide a programmable system in package (“PSiP”). The PSiP includes a single IC housing, a substrate and several IC's that are arranged within the single IC housing. At least one of the IC's is a configurable IC. In some embodiments, the configurable IC is a reconfigurable IC that can reconfigure more than once during run time. In some of these embodiments, the reconfigurable IC can be reconfigured at a first clock rate that is faster (i.e., larger) than the clock rates of one or more of the other IC's in the PSiP. The first clock rate is faster than the clock rate of all of the other IC's in the PSiP in some embodiments.
[0007] Some embodiments provide a method for manufacturing a programmable system in package. The method divides a system into sets of operations. For each set of operations, the method identifies an integrated circuit (“IC”) for performing the set of operations. The method packages a set of identified IC's into a single IC package. The set of identified IC's includes at least one configurable IC. In some embodiments, the configurable IC is a reconfigurable IC that can reconfigure more than once during run time.
[0008] Other embodiments of the invention provide a method for selecting a set of IC's for a PSiP. The method defines a budget for implementing the PSiP. The method identifies sets of operations that the PSiP has to implement. For each particular set of operations, the method identifies an IC to implement the particular set of operations. When the method identifies a set of IC's for implementing the PSiP's sets of operations, the method determines whether the cost of the identified set of IC's is less than the budget. If so, the method selects the identified set of IC's. Otherwise, the method searches for another set of IC's to implement the PSiP's operations. In the set of IC's that the method eventually selects, there is at least one IC that is a configurable IC. In some embodiments, the configurable IC is a reconfigurable IC that can reconfigure more than once during run time.
[0009] In some of the embodiments described above, the set of IC's may include digital and analog IC's. Furthermore, in some embodiments, the set of IC's may include IC's that are manufactured with different fabrication technologies. Moreover, different embodiments might package the set of IC's differently in a single package. Some embodiments might stack the set of IC's on top of each other into a single package. Some embodiments might place the set of IC's side by side into a single package. Some embodiments might stack some IC's while placing other IC's side by side in a single package.
Brief Description of the Drawings
[0010] The novel features of the invention are set forth in the appended claims. However, for purpose of explanation, several embodiments of the invention are set forth in the following figures.
[0011] FIG. 1 illustrates a PSiP with IC's that are stacked in a pyramid structure and includes a ball grid array.
[0012] FIG. 2 illustrates a PSiP with IC's that are stacked in a non-pyramid structure and includes a pin grid array.
[0013] FIG. 3 illustrates a PSiP with IC's that are placed side by side.
[0014] FIG. 4 illustrates a PSiP with IC's that are stacked and placed side by side.
[0015] FIG. 5 illustrates a reconfigurable IC that can perform the operations of a non configurable IC.
[0016] FIG. 6 illustrates a PSiP with a reconfigurable IC stacked on top of non configurable IC's.
[0017] FIG. 7 illustrates a PSiP with IC's that have different manufacturing processes.
[0018] FIG. 8 illustrates a PSiP with a heat sink in the PSiP.
[0019] FIG. 9 illustrates a PSiP with a heat sink embedded in the first IC of the PSiP.
[0020] FIG. 10 illustrates a process of manufacturing a PSiP.
[0021] FIG. 11 illustrates a method of identifying IC's for a PSiP.
[0022] FIG. 12 illustrates an example of a system for a PSiP divided into a set of operations.
Detailed Description of the Invention
[0023] In the following description, numerous details are set forth for purpose of explanation. However, one of ordinary skill in the art will realize that the invention may be practiced without the use of these specific details. In other instances well-known structures and devices are shown in block diagram form in order not to obscure the description of the invention with unnecessary detail.
[0024] Some embodiments of the invention provide a programmable system in package (“PSiP”). The PSiP includes a single IC housing, a substrate and several IC's that are arranged within the single IC housing. At least one of the IC's is a configurable IC. In some embodiments, the configurable IC is a reconfigurable IC that can reconfigure more than once during “run time”.
[0025] As used in this document, run time means a period during which the PSiP continuously receives power (i.e., after the PSiP starts receiving power and before the PSiP stops receiving power). Also, in this document, the term “IC” refers to a semiconductor wafer on which a number of circuit elements (e.g., transistors, resistors, etc.) have been defined.
[0026] In some of these embodiments, the reconfigurable IC can be reconfigured at a first clock rate that is faster (i.e., larger) than the clock rates of one or more of the other IC's in the PSiP. The first clock rate is faster than the clock rate of all of the other IC's in the PSiP in some embodiments.
[0027] In some of the embodiments, the set of IC's may include digital and analog IC's. Furthermore, in some embodiments, the set of IC's may include IC's that are manufactured with different fabrication technologies. Moreover, different embodiments might package the set of IC's differently in a single package. Some embodiments might stack the set of IC's on top of each other into a single package. Some embodiments might place the set of IC's side by side into a single package. Some embodiments might stack some IC's while placing other IC's side by side in a single package.
I. Structure of PSiP with Configurable Ic
[0028] A. Stacked IC's
[0029] FIG. 1 illustrates an example of a PSiP that includes several IC's that are stacked. As shown in this figure, the PSiP 100 includes a substrate 105, a ball grid array (“BGA”) 110, a set of vias 115, a first IC 120, a second IC 125, a third IC 130, a fourth IC 135, a first adhesive 140, a second adhesive 145, a third adhesive 150, a fourth adhesive 155, a first set of wire-bonding 160, a second set of wire-bonding 165, a third set of wire-bonding 170, a fourth set of wire-bonding 175, and a housing 180. In some embodiments, at least one of the IC's 120-135 is a configurable IC, or a reconfigurable IC, as further described below.
[0030] As shown in FIG. 1 , the substrate 105 serves as a base for creating the PSiP. In some embodiments, the substrate 105 is a non-conducting or insulating material that prevents outside electrical phenomena (e.g., current, voltage) from interfering with the internal IC's (e.g., first, second, third, fourth IC's) of the PSiP 100.
[0031] As further shown in FIG. 1 , the first IC 120 is located on top of the substrate 105. A first adhesive 140 bonds the first IC 120 to the substrate 105. The second IC 125 is located on top of the first IC 120. The second adhesive 145 bonds the second IC 125 to the first IC 120. The third IC 130 is located on top of the second IC 125. The third adhesive 150 bonds the second IC 125 to the third IC 130. The fourth IC 135 is located on top of the third IC 130. The fourth adhesive 155 bonds the third IC 130 to the fourth IC 135. As shown in this figure, the ICs 120-135 are stacked in a pyramid structure. That is, the ICs 120-135 are stacked bottom to top, from the largest IC to the smallest IC. However, other embodiments might stack the ICs 120-135 differently, such as shown in FIG. 2 .
[0032] As further shown in FIG. 1 , the first IC 120 is communicatively attached to the substrate 105 through the first set of wire-bonding 160. Similarly, each of the IC's 125-135 is communicatively attached to the substrate 105 through a respective set of wire-bonding 165, 170, or 175. These sets of wire-bonding 160-175 allow the first, second, third and fourth IC's 120-135 to communicate with each other without having to go outside of the PSiP 100. In some embodiments, the IC's 120-135 might be directly wire-bonded to each other in order to facilitate communication between these IC's. Instead of, or in conjunction with the sets of wire-bonding 160-175, some embodiments might use other mechanisms to communicatively couple the IC's 120-135 to each other. Furthermore, FIG. 1 illustrates the sets of wire-bonding 160-175 attached to the top surface of the IC's 120-135. However, in other embodiments, the sets of wire-bonding 160-175 may be attached to another surface area (e.g. side surface area) of the IC's 120-135 of the PSiP 100, such as shown in FIG. 2 .
[0033] As further shown in FIG. 1 , the substrate 105 includes the BGA 110 and the set of vias 115. The BGA 110 is a set of solder balls that allows the PSiP 100 to be attached to a printed circuit board (“PCB”). Each via connects a solder ball in the BGA 110 on the bottom of the substrate 105, to a conductor on the top of the substrate 105.
[0034] The conductors on the top of the substrate 105 are electrically coupled to the IC's 120-135 through the sets of wire bonding 160-175. Accordingly, the IC's 120-135 can send and receive signals to and from circuits outside of the PSiP 100 through the sets of wire bonding 160-175, the conductors on the top of the substrate 105, the set of vias 115, and the BGA 110.
[0035] Some embodiments place the BGA 110 in a concentric two-dimensional array at the bottom of the substrate. Other embodiments might place the BGA 110 in other arrangements (e.g., in a peripheral arrangement around the perimeter of the PSiP 100). In other embodiments, a PSiP 200 includes a pin grid array (“PGA”) 205, as shown in FIG. 2 . The PGA 205 performs the same function as the BGA 115 shown in FIG. 1 . As such, in combination with the set of vias 115, the PGA 205 provides an intermediate that allows the IC's 120-135 inside the PSiP 200 to communicate with other IC's outside the PSiP 200.
[0036] As further shown in FIG. 1 , the housing 180 encapsulates the substrate 105, the BGA 110, the set of vias 115, the IC's 120-135, the adhesives 140-155, the sets of wire-bonding 160-175 to form the PSiP 100.
[0037] In the figures mentioned above and below, the PSiPs are shown attached to a PCB facing up. However, one of ordinary skill in the art will realize that other PSiP structures can be used. For example, some embodiments might use a flip chip structure. In such instances, the PSiPs are flipped over and attached to the PCB facing down.
[0038] B. Side by Side IC's
[0039] FIG. 3 illustrates an example of a PSiP 300 that includes several IC's that are placed side by side to each other. As shown in this figure, the first, second, third and fourth IC's 120-135 are located on top of the substrate 105. In some embodiments, at least one of the IC's 120-135 is a configurable IC or a reconfigurable IC, as further described below.
[0040] In the PSiP 300, each IC is placed side by side to each other. A first adhesive 140 is placed between the first IC 120 and the substrate 105 to bond them together. Similarly, a second, third and fourth adhesive 145-155 are respectively placed between the second, third and fourth IC 125-135 and the substrate 105. A first, second, third and fourth set of wire-bonding 160-175 are attached respectively to the first, second, third and fourth IC's 120-135. These sets of wire-bonding 160-175 allow the IC's 120-135 (1) to communicate with each other without having to go outside of the PSiP, and (2) to communicate with IC's that are located outside of the PSiP 300.
[0041] The PSiP 300 includes a BGA 110 and a set of vias 115. As previously mentioned, the BGA 110 and the set of vias 115 allow the IC's 120-135 to communicate with IC's outside of the PSiP 300. In contrast to the PSiP 100 with stacked IC's, which provides a PSiP that is narrow, the PSiP 300 that includes side by side IC's provides a PSiP that is thin.
[0042] iii. Combination of Stacked and Side by Side IC's
[0043] FIG. 4 illustrates an example of a PSiP 400 that includes a combination of stacked and side by side IC's. In such an embodiment, some IC's of the PSiP 400 are stacked on top of each other, while other IC's of the PSiP 400 are placed side by side to each other. As shown in this figure, a first, second and third IC 120-130 is placed on top of a substrate 105. A first, second and third adhesive 140-150 respectively bond the first, second and third IC 120-130 to the substrate 105. A fourth IC 135 is placed on top of the third IC 130. A fourth adhesive 155 bonds the fourth IC 135 to the third IC 130. In some embodiments, at least one of the IC's 120-135 is a configurable IC. Furthermore, the PSiP 400 includes a first, second, third and fourth set of wire-bonding 160-175 that are attached respectively to the first, second, third and fourth IC's 120-135. As previously described, these sets of wire-bonding 160-175 allow the IC's 120-135 to communicate with each other. In other embodiments, the PSiP 400 further includes a BGA 110 and a set of vias 115 to allow the IC's 120-135 to communicate with IC's outside of the PSiP 400.
II. PSiP with Reconfigurable IC's
[0044] In some embodiments, the configurable IC of the PSiP's described above is a reconfigurable IC that reconfigures more than once during runtime. In some embodiments, this reconfigurable IC might be a sub-cycle reconfigurable IC. FIG. 5 conceptually illustrates an example of a sub-cycle reconfigurable IC. Specifically, in its top left hand corner, this figure illustrates a non-configurable IC 505 that operates at a clock speed of X MHz. As further illustrated in this figure, the operations performed by this non-configurable IC 505 can be partitioned into four sets of operations that are each performed at a clock speed of X MHz.
[0045] FIG. 5 then illustrates that these four sets of operations can be performed by one sub-cycle reconfigurable IC 530 that operates at 4× MHz. In some embodiments, four cycles of the 4× MHz clock correspond to four sub-cycles within a cycle of the X MHz clock. Accordingly, this figure illustrates the reconfigurable IC 530 reconfiguring four times during four cycles of the 4× MHz clock (i.e., during four sub-cycles of the X MHz clock). During each of these reconfigurations (i.e., during each sub-cycle), the reconfigurable IC 530 performs one of the identified four sets of operations. In other words, the faster operational speed of the reconfigurable IC 530 allows this IC to reconfigure four times during each cycle of the X MHz clock, in order to perform the four sets of operations sequentially at a 4× MHz rate instead of performing the four sets of operations in parallel at an X MHz rate.
[0046] In some embodiments, a reconfigurable IC 530 reconfigures at a clock speed that is comparatively faster than the clock speed of some or all other IC's within a PSiP. FIG. 6 illustrates an example of such a PSiP. Specifically, this figure illustrates a PSiP 600 that includes a first, second, third and fourth IC 605-620. The first, second and third IC's 605-615 are non configurable IC's. As shown in this figure, each of the first, second and third IC's 605-615 operates at a clock speed of Z MHz or less. The fourth IC 620 is a reconfigurable IC which operates at a clock speed of 4Z MHz.
[0047] As shown in FIG. 6 , the clock speed of the reconfigurable IC 620 is comparatively faster than the clock speed of the first, second and third IC's 605-615. In other embodiments, the clock speed of the reconfigurable IC 620 is comparatively faster than the clock speed of either the first, second or third IC 605-615.
III. Mixed Fabrication Technology
[0048] As mentioned above, the IC's within a PSiP can perform many operations. Examples of operations include a processor operation, an analog operation, a memory operation, etc. In some embodiments, these IC's are manufactured using different fabrication technologies. For instance, an IC that performs memory operations might be manufactured using 90 nm fabrication technology, while an IC that performs a processor operation might be manufactured using 130 nm fabrication technology, and an IC that performs analog operations might be manufactured using 180 nm.
[0049] FIG. 7 conceptually illustrates a PSiP 700 that includes IC's with different fabrication technologies. The PSiP 700 includes a first, second, third and fourth IC 120-135 that are placed on top of the substrate 105. At least one of the IC's 120-135 is a configurable IC. In this figure, the IC's 120-135 have different dimensions (e.g., width, height) to illustrate pictorially and conceptually that some of the IC's 120-135 are manufactured with different fabrication technologies. Irrespective of the conceptual illustration in FIG. 7 , one of ordinary skill will realize that using different manufacturing fabrication technologies might not result in IC's with different dimensions.
IV. PSiP with Heat Sink
[0050] In some embodiments, a PSiP includes a heat sink. FIG. 8 illustrates an example of such a PSiP. As shown in this figure, the PSiP 800 includes a first IC 805 and a configurable IC 810. The configurable IC 810 is a reconfigurable IC in some embodiments. As shown in FIG. 8 , the PSiP 800 also includes a heat sink 815 between the first IC 805 and the configurable IC 810. The heat sink 815 helps dissipate heat from the configurable IC 810 in the PSiP 800.
[0051] FIG. 9 illustrates another embodiment of a PSiP that includes a heat sink. As shown in this figure, the PSiP 900 includes a first IC 905 and a configurable IC 910. The configurable IC 910 is a reconfigurable IC in some embodiments. As shown in FIG. 9 , the first IC 905 includes (1) a center area 915 on which no circuits are defined, and (2) a periphery area 920 on which circuit elements (e.g., transistors, resistors, wires, etc.) are defined. The center area 915 serves as a heat sink on which configurable IC 910 is positioned. In other words, the center area 915 helps dissipate heat from the configurable IC 910 in the PSiP 900.
[0052] Having described various PSiP that include a configurable or reconfigurable IC, a method of manufacturing a PSiP and selecting the IC's for the PSiP will now be described in detail.
V. Manufacturing PSiP
[0053] FIG. 10 conceptually illustrates a process 1000 for manufacturing a PSiP. As shown in this figure, the system requirements of the PSiP are initially identified (at 1005). That is, this operation identifies what performance objectives the PSiP has to achieve. After identifying (at 1005) the system requirements of the PSiP, sets of operations that are necessary for achieving the identified system requirements are identified at 1010. For each set of operation identified at 1010, a determination is made (at 1010) whether to implement the set of operations by using an existing IC or a new IC that will be specifically designed or configured to implement the set of operations. In some embodiments, at least one of the IC's identified at 1010 is a configurable IC. In some of these embodiments, this configurable IC is a reconfigurable IC that reconfigures more than once during run time. The operation at 1010 will be further described below by reference to FIG. 11 .
[0054] After identifying new or existing IC's, a PSiP structure is identified (at 1015) for housing all the identified IC's. As described above, a PSiP can be structured in numerous ways. In some embodiments, a PSiP can include IC's that are stacked. In other embodiments, a PSiP can include IC's that are placed side by side. In yet other embodiments, a PSiP can include IC's that are placed side by side and stacked.
[0055] After defining (at 1015) the structure of the PSiP, a pre-fabrication analysis is performed (at 1020) to determine whether the designed PSiP is likely to satisfy the system requirements. If the designed PSiP fails this analysis, the process (1) returns back to 1010 to redefine the sets of operations and/or to modify the IC selection/design choices, and then (2) transitions to 1015 to define a PSiP structure for housing the IC's identified at 1010.
[0056] When the PSiP design passes the pre-fabrication analysis at 1020, the PSiP is manufactured (at 1025) based on the IC's identified in the last iteration of 1010 and the PSiP structure identified in the last iteration of 1015. In some embodiments, the manufacturing process entails purchasing and/or configuring only existing IC's to produce the desired PSiP. In other embodiments, the manufacturing process entails manufacturing at least one new IC to produce the PSiP.
[0057] After manufacturing the PSiP, the manufactured PSiP is tested (at 1030) to determine whether the manufactured PSiP meets the system requirements that were identified (at 1005). If not, the process returns to 1010, which was described above. When the manufactured PSiP passes the post-fabrication analysis at 1030, then the process 1000 ends.
VI. Identifying Reconfigurable Ic's for PSiP
[0058] FIG. 11 conceptually illustrates a process 1100 for selecting and identifying IC's to be used in a PSiP. Some embodiments perform the process 1100 to implement the design operation 1010 in FIG. 10 . As shown FIG. 11 , an available budget for producing the PSiP is initially identified at 1105. In some embodiments, this budget is predicted on producing a certain number of PSiP's. Also, in some embodiments, the identified budget accounts for all funds necessary (1) for designing, configuring and manufacturing new IC or IC's if such IC's are required by the PSiP, and (2) for acquiring and/or configuring an existing IC. In other embodiments, this amount also includes the cost of the PSiP packaging, assembling, and/or testing.
[0059] Once the available budget has been defined (at 1105), sets of operations are identified (at 1110) by dividing the system requirements of the PSiP into several operational blocks, where each operational block represents a set of operations that the PSiP has to perform. FIG. 12 conceptually illustrates an example of dividing the system requirements for a PSiP into several operational blocks. In this example, the operational blocks include a processor operation block 1205, a memory operation block 1210, a digital signal processor operation block 1220, an analog operation block 1225, an analog/digital converter operation block 1230, a digital/analog converter operation block 1235, and a reconfigurable IC operation block 1240. As mentioned above, each operational block includes a set of operations that the PSiP has to perform. For instance, the processor operation block 1205 may include a set of processing operations that the PSiP has to perform.
[0060] Once the sets of operations have been identified (at 1110) by dividing the system requirement of the PSiP into several operational blocks, one or more sets of operations (i.e., selects at least one or more operational blocks) are selected at 1115. After selecting one or more sets of operations at 1115, an IC that can perform the selected set or sets of operations is identified at 1120. The identified IC might be an existing IC that can perform or can be configured to perform the set or sets of operations selected at 1115. Alternatively, the identified IC might be an IC that has to be designed to perform, or has to be designed to be configured to perform, the selected set of operations. In at least one iteration through 1120, the selected IC is a configurable IC. In some cases, the configurable IC is a reconfigurable IC that can reconfigured more than once at run time.
[0061] Different identified IC's perform the selected set or sets of operations differently. For instance, a non-configurable IC that is identified at 1120 might perform in parallel the operations in the set or sets of operations selected at 1115. Alternatively, the IC identified at 1120 might be a configurable IC that can be configured to perform in parallel the operations in the set or sets of operations selected at 1115. On the other hand, the IC identified at 1120 might be a reconfigurable IC that sequentially performs one or more sub-sets of the operations in the set(s) of operations selected at 1115 during different reconfiguration sub-cycles.
[0062] Once the IC is identified at 1120, a determination is made (at 1125) as to whether the actual or estimated cost of the identified IC is less than the available budget. When the selected IC is a previously designed IC, the cost of the IC is the cost associated with purchasing, manufacturing, and/or configuring the previously designed IC. When the selected IC is an IC that has yet to be designed, the cost of the IC is the cost associated with designing, testing, manufacturing, and/or configuring the IC. Furthermore, in some embodiments, the cost of the IC accounts for costs associated with packaging and assembling the IC within the PSiP. In such embodiments, the process 1100 might perform the package-defining operation 1015 of the process 1000 of FIG. 10 , or might simply account for the probable cost of such a packaging.
[0063] If the cost of the identified IC is not less than the available budget, the process 1100 proceeds back to 1120 to identify another IC for the selected set of operations. However, if the cost of the identified IC is less than the available budget, the process 1100 subtracts (at 1130) the cost of the identified IC from the available budget.
[0064] Once the cost of the identified IC has been subtracted from the available budget, a determination is made (at 1135) whether there is an additional set of operations that has not yet been associated with an IC. If so, the process 1100 (1) returns back to 1115 to select other set or sets of operations that have not yet been selected, and then (2) proceeds to 1120 to identify another IC for the newly selected set or sets of operations.
[0065] When it is determined (at 1135) that there is no additional set of operations, a determination is made (at 1140) whether the identified set of IC's is a good enough set of IC's for implementing the PSiP. For instance, when the identified set of IC's includes a reconfigurable IC, a determination might be made (at 1140) that the reconfigurable IC can perform additional operations in order to reduce the overall cost of the PSiP. Such additional operations would be operations that were previously identified for another IC. When a determination is made (at 1140) that the set of IC's is a good enough set, the process 1100 ends.
[0066] A PSiP, i.e., a SiP with a configurable or reconfigurable IC, has many advantages. A PSiP provides a simple solution for combining the often desirable configurable functionality of a configurable or reconfigurable IC with the functionalities commonly provided by other IC's. PSiP's are easier to design than the currently proposed SoC solutions that combine configurable functionality of configurable IC's with other IC functionalities.
[0067] Also, the IC's of a PSiP can be manufactured by different fabrication technologies. Hence, optimal fabrication processes can be used to manufacture the IC's of the PSiP. This is to be contrasted with the prior SoC solutions that require the use of one fabrication process for all the operational blocks on the SoC, which results in some of the operational blocks being manufactured by fabrication processes that are far from their optimal fabrication technology.
[0068] While the invention has been described with reference to numerous specific details, one of ordinary skill in the art will recognize that the invention can be embodied in other specific forms without departing from the spirit of the invention. For instance, some embodiments might first identify all the IC's for the PSiP and then determine whether the cost of all the IC's is less than the available budget. Furthermore, in some instances, some embodiments might identify an IC based on IC's that were previously identified. Additionally, some embodiments determine whether a set of IC's is optimized based on cost. As such, in some instances, a set of IC's is not optimized if the cost of the set of IC's can be further minimized. Thus, one of ordinary skill in the art would understand that the invention is not to be limited by the foregoing illustrative details, but rather is to be defined by the appended claims.
Claims
What is claimed is:
1. A system in package (“SiP”) comprising:
a substrate; and
first and second integrated circuits (“ICs”),
wherein the first IC is positioned on the substrate, the first IC comprising (i) a first portion where no circuit elements are defined and (ii) a second portion where circuit elements are defined, wherein the second IC is positioned over the first portion of the first IC, wherein the heat from the second IC is dissipated by the first portion of the first IC, wherein the second IC operates at a first clock rate that is faster than a second clock rate of the first IC.
2. The SiP of claim 1, wherein the first portion is a center portion of the first IC, wherein the second portion is a periphery portion of the first IC.
3. The SiP of claim 1 further comprising a cap coupled to the substrate to create a housing that encapsulates the first IC and the second IC.
4. The SiP of claim 1, wherein the second IC is in direct contact with the first IC.
5. The SiP of claim 1, wherein the second IC implements an IC design defined by a user clock rate that is slower than the first clock rate of the second IC.
6. The SiP of claim 5, wherein the user clock rate is a rate of a user clock, wherein the second IC reconfigures multiple times within a clock cycle of the user clock.
7. The SiP of claim 1, wherein the second IC is a sub-cycle reconfigurable IC.
8. The SiP of claim 1, wherein the second IC reconfigures to perform different sets of operations during different clock cycles.
9. The SiP of claim 8, wherein the different clock cycles are sub-cycles of another clock operating in the SiP.
10. The SiP of claim 1, wherein one of the first and second ICs is a digital IC while the other of the first and second ICs is an analog IC.
11. The SiP of claim 1, wherein the first IC is manufactured with a first fabrication process and the second IC is manufactured with a second fabrication process that is different from the first fabrication process.
12. The SiP of claim 1 further comprising:
a first set of wire bonding coupled to the first IC; and
a second set of wire-bonding coupled to the second IC, wherein the first and second sets of wire-bonding allow the first IC to communicate with the second IC.
13. The SiP of claim 12, wherein the first and second sets of wire-bonding are coupled to the substrate.
14. The SiP of claim 12 further comprising:
a third IC positioned on the substrate, the third IC positioned side-by-side to the first and second ICs; and
a bonding material coupling the third IC to the substrate.
15. The SiP of claim 1, wherein the first portion of the first IC comprises a heat sink.
16. A system in package (“SiP”) comprising:
a substrate;
a first integrated circuit (“IC”); and
a second IC,
wherein the first IC is positioned on the substrate, the first IC comprising (i) a first portion where no circuit elements are defined, the first portion for dissipating heat from the second IC positioned adjacent to the first portion and (ii) a second portion where circuit elements are defined, and
the second IC comprising a plurality of reconfigurable circuits, each reconfigurable circuit for reconfigurably performing different sets of operations, wherein the heat from the second IC is dissipated by the first portion of the first IC.
17. The SiP of claim 16, wherein the second IC implements an IC design that is defined according to a first clock rate, wherein the second IC operates at a second clock rate that is faster than the first clock rate.
18. The SiP of claim 17, wherein the first clock rate is a rate of a first clock, wherein the second IC reconfigures multiple times within a clock cycle of the first clock.
19. The SiP of claim 16, wherein the second IC operates at a first clock rate that is faster than a second clock rate of the first IC.
20. The SiP of claim 19, wherein the first clock rate is a clock rate at which the second IC reconfigures to perform the different sets of operations.
21. The SiP of claim 19, wherein the second IC is a sub-cycle reconfigurable IC.
22. The SiP of claim 19, wherein the second IC reconfigures to perform different sets of operations during different clock cycles.
23. The SiP of claim 22, wherein the different clock cycles are sub-cycles of another clock operating in the SiP.
24. The SiP of claim 16, wherein one of the first and second ICs is a digital IC while the other of the first and second ICs is an analog IC.
25. The SiP of claim 16, wherein the first IC is manufactured with a first fabrication process and the second IC is manufactured with a second fabrication process that is different than the first fabrication process.
26. The SiP of claim 16 further comprising:
a first set of wire-bonding coupled to the first IC; and
a second set of wire-bonding coupled to the second IC, wherein the first and second sets of wire-bonding allow the first IC to communicate with the second IC.
27. The SiP of claim 26, wherein the first and second sets of wire-bonding are coupled to the substrate.
28. A system in package (“SiP”) comprising:
a substrate;
a plurality of integrated circuits (“IC”) comprising:
(i) a first IC that is positioned on top of the substrate;
(ii) a second IC comprising a plurality of reconfigurable circuits for reconfigurably performing different sets of operations; and
a heat sink coupled to the second IC, wherein the heat sink is for dissipating heat from the second IC.
29. The SiP of claim 28, wherein the heat sink is positioned on top of the center of the first IC.
30. The SiP of claim 29, wherein the second IC is positioned on top of the heat sink.
31. The SiP of claim 28, wherein the heat sink is positioned between the first and second ICs of the SiP.
Patent Citations (101)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US5426378(A) | 1995-06-01 | Ong | Applicant |
| US5434453(A) | 1995-07-01 | Yamamoto et al. | Applicant |
| US5495398(A) | 1996-02-01 | Takiar et al. | Examiner |
| US5512765(A) | 1996-04-01 | Gaverick | Applicant |
| US5521835(A) | 1996-05-01 | Trimberger | Applicant |
| US5530292(A) | 1996-06-01 | Waki et al. | Applicant |
| US5596743(A) | 1997-01-01 | Bhat et al. | Applicant |
| US5600263(A) | 1997-02-01 | Trimberger et al. | Applicant |
| US5610442(A) | 1997-03-01 | Schneider et al. | Applicant |
| US5610829(A) | 1997-03-01 | Trimberger | Applicant |
| US5629637(A) | 1997-05-01 | Trimberger et al. | Applicant |
| US5646545(A) | 1997-07-01 | Trimberger et al. | Applicant |
| US5701441(A) | 1997-12-01 | Trimberger | Applicant |
| US5721498(A) | 1998-02-01 | Mason et al. | Applicant |
| US5761483(A) | 1998-06-01 | Trimberger | Applicant |
| US5815372(A) | 1998-09-01 | Gallas | Applicant |
| US5825662(A) | 1998-10-01 | Trimberger | Applicant |
| US5869896(A) | 1999-02-01 | Baker et al. | Applicant |
| US5920712(A) | 1999-07-01 | Kuijsten | Applicant |
| US5944813(A) | 1999-08-01 | Trimberger | Applicant |
| US5952725(A) | 1999-09-01 | Ball | Applicant |
| US5973340(A) | 1999-10-01 | Mohsen | Applicant |
| US6015722(A) | 2000-01-01 | Banks et al. | Applicant |
| US6018559(A) | 2000-01-01 | Azegami et al. | Applicant |
| US6084429(A) | 2000-07-01 | Trimberger | Applicant |
| US6100594(A) | 2000-08-01 | Fukui et al. | Applicant |
| US6137164(A) | 2000-10-01 | Yew et al. | Applicant |
| US6437446(B1) | 2002-08-01 | Uchida | Examiner |
| US6480954(B2) | 2002-11-01 | Trimberger et al. | Applicant |
| US6515505(B1) | 2003-02-01 | Rees | Applicant |
| US6601227(B1) | 2003-07-01 | Trimberger | Applicant |
| US6633182(B2) | 2003-10-01 | Pileggi et al. | Applicant |
| US6650142(B1) | 2003-11-01 | Agrawal et al. | Applicant |
| US6686223(B2) | 2004-02-01 | Uchida | Applicant |
| US6709890(B2) | 2004-03-01 | Ida et al. | Applicant |
| US6737755(B1) | 2004-05-01 | McLellan et al. | Applicant |
| US6744126(B1) | 2004-06-01 | Chiang | Applicant |
| US6781226(B2) | 2004-08-01 | Huppenthal et al. | Applicant |
| US6829756(B1) | 2004-12-01 | Trimberger | Applicant |
| US6906407(B2) | 2005-06-01 | Byers et al. | Applicant |
| US6964029(B2) | 2005-11-01 | Poznanovic et al. | Applicant |
| US6969898(B1) | 2005-11-01 | Exposito et al. | Applicant |
| US6989285(B2) | 2006-01-01 | Ball | Applicant |
| US6991947(B1) | 2006-01-01 | Gheewala | Applicant |
| US7009303(B2) | 2006-03-01 | Kuroda et al. | Applicant |
| US7030651(B2) | 2006-04-01 | Madurawe | Applicant |
| US7062744(B2) | 2006-06-01 | Osann, Jr. | Applicant |
| US7082591(B2) | 2006-07-01 | Carlson | Applicant |
| US7091598(B2) | 2006-08-01 | Fujita et al. | Applicant |
| US7126214(B2) | 2006-10-01 | Huppenthal et al. | Applicant |
| US7138827(B1) | 2006-11-01 | Trimberger | Applicant |
| US7143329(B1) | 2006-11-01 | Trimberger et al. | Applicant |
| US7200235(B1) | 2007-04-01 | Trimberger | Applicant |
| US7212448(B1) | 2007-05-01 | Trimberger | Applicant |
| US7219421(B2) | 2007-05-01 | Vrtis et al. | Applicant |
| US7262506(B2) | 2007-08-01 | Mess et al. | Examiner |
| US7268426(B2) | 2007-09-01 | Warner et al. | Examiner |
| US7286976(B2) | 2007-10-01 | Diehl et al. | Applicant |
| US7301242(B2) | 2007-11-01 | Teig | Applicant |
| US7310757(B2) | 2007-12-01 | Ngo et al. | Applicant |
| US7328384(B1) | 2008-02-01 | Kulkarni et al. | Applicant |
| US7424655(B1) | 2008-09-01 | Trimberger | Applicant |
| US7530044(B2) | 2009-05-01 | Teig | Applicant |
| US7936074(B2) | 2011-05-01 | Teig | Applicant |
| US2002/0010853(A1) | 2002-01-01 | Trimberger et al. | Applicant |
| US2002/0066956(A1) | 2002-06-01 | Taguchi | Applicant |
| US2002/0157071(A1) | 2002-10-01 | Schiefele et al. | Applicant |
| US2004/0061147(A1) | 2004-04-01 | Fujita et al. | Applicant |
| US2004/0088666(A1) | 2004-05-01 | Poznanovic et al. | Applicant |
| US2004/0105207(A1) | 2004-06-01 | Spaderna et al. | Applicant |
| US2004/0130036(A1) | 2004-07-01 | Owaki et al. | Applicant |
| US2004/0169285(A1) | 2004-09-01 | Verma et al. | Applicant |
| US2004/0221451(A1) | 2004-11-01 | Chia et al. | Applicant |
| US2004/0238934(A1) | 2004-12-01 | Warner et al. | Examiner |
| US2004/0243383(A1) | 2004-12-01 | Garino et al. | Applicant |
| US2004/0262774(A1) | 2004-12-01 | Kang et al. | Applicant |
| US2005/0017336(A1) | 2005-01-01 | Kung et al. | Applicant |
| US2005/0046003(A1) | 2005-03-01 | Tsai | Examiner |
| US2005/0051903(A1) | 2005-03-01 | Ellsberry et al. | Applicant |
| US2005/0066294(A1) | 2005-03-01 | Templeton et al. | Applicant |
| US2005/0181539(A1) | 2005-08-01 | Ohie | Applicant |
| US2005/0189634(A1) | 2005-09-01 | Wakiyama et al. | Applicant |
| US2005/0193353(A1) | 2005-09-01 | Malekkhosravi et al. | Applicant |
| US2005/0257178(A1) | 2005-11-01 | Daems et al. | Applicant |
| US2005/0269687(A1) | 2005-12-01 | Forcier | Applicant |
| US2005/0275074(A1) | 2005-12-01 | Weng et al. | Applicant |
| US2006/0071701(A1) | 2006-04-01 | Nickolls | Applicant |
| US2006/0118927(A1) | 2006-06-01 | Verma et al. | Applicant |
| US2006/0195729(A1) | 2006-08-01 | Huppenthal et al. | Applicant |
| US2007/0045806(A1) | 2007-03-01 | Hsuan | Applicant |
| US2007/0108598(A1) | 2007-05-01 | Zhong et al. | Applicant |
| US2007/0143577(A1) | 2007-06-01 | Smith | Applicant |
| US2008/0122484(A1) | 2008-05-01 | Zhu et al. | Applicant |
| US2008/0179729(A1) | 2008-07-01 | Shim, II et al. | Applicant |
| US2008/0215854(A1) | 2008-09-01 | Asaad et al. | Applicant |
| US2008/0220563(A1) | 2008-09-01 | Karnezos | Applicant |
| US2008/0293167(A1) | 2008-11-01 | Wada et al. | Applicant |
| US2011/0049577(A1) | 2011-03-01 | Or-Bach et al. | Applicant |
| JP4-162767 | 1992-06-01 | Applicant | |
| JP5-343606 | 1993-12-01 | Applicant | |
| KR2002039010 | 2002-05-01 | Applicant |
Non-Patent Literature (17)
- U.S. Appl. No. 11/269,506, filed Nov. 7, 2005, Schmit, Herman et al.Applicant
- U.S. Appl. No. 11/269,868, filed Nov. 7, 2005, Horel, Timothy.Applicant
- U.S. Appl. No. 11/271,165, filed Nov. 11, 2005, Horel, Timothy, et al.Applicant
- U.S. Appl. No. 12/198,878, filed Aug. 26, 2008, Teig, Steven,Applicant
- Portions of Prosecution History of U.S. Appl. No. 11/081,820, Mar. 2, 2009, Teig, Steven.Applicant
- Portions of Prosecution History of U.S. Appl. No. 11/081,842, Sep. 26, 2007, Teig, Steven.Applicant
- Portions of Prosecution History of U.S. Appl. No. 11/861,204, Mar. 30, 2011, Teig, Steven.Applicant
- Portions of Prosecution History of U.S. Appl. No. 11/271,165, Aug. 30, 2010, Horel, Timothy, et al.Applicant
- Portions of Prosecution History of U.S. Appl. No. 11/269,868, filed Jul. 29, 2010, Horel, Timothy.Applicant
- Portions of Prosecution History of U.S. Appl. No. 11/269,506, filed Dec. 6, 2010, Schmit, Herman, et al.Applicant
- Portions of Prosecution History of U.S. Appl. No. 12/198,878, filed Feb. 2, 2012, Teig, Steven.Applicant
- Patel, C., et al., “An Architectural Exploration of Via Patterned Gate Arrays,” Proceedings of the 2003 International Symposium on Physical Design, Apr. 6-9, 2003, pp. 184-189, Monterey, California, USA.Applicant
- Patel, C., et al., “An Architectural Exploration of Via Patterned Gate Arrays,” Carnegie Mellon University Center for Silicon System Implementation, NPL.Applicant
- Taylor, R., et al., “Enabling Energy Efficiency in Via-Patterned Gate Array Devices”, Proceedings of the 41st annual conference on Design automation, Jun. 7-11, 2004, San Diego, California, USA.Applicant
- Tong, K.T., et al., “Regular Logic Fabrics for a Via Patterned Gate Array (VPGA),” Proceedings of the IEEE 2003 Custom Integrated Circuits Conference 2003, Sep. 21-24, 2003.Applicant
- Trimberger, S., “Effects of FPGA Architecture on FPGA Routing,” 32nd ACM/IEEE Design Automation Conference, Jun. 1995, ACM.Applicant
- Patel, C., et al., “An Architectural Exploration of Via Patterned Gate Arrays,” Carnegie Mellon University Center for Silicon System Implementation, Month Unknown, 2003, 23 pages.Applicant