Method for manufacturing a semiconductor device capable of preventing the decrease of the width of an active region

[0001] The present application claims priority to Korean patent application number 10-2007-0135599 filed on Dec. 21, 2007, which is incorporated herein by reference in its entirety.

[0002] The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device, which can prevent the decrease of the width of an active region.

[0003] With the development of semiconductor manufacturing technologies, semiconductor devices are becoming more highly integrated and accordingly, the size of cell transistors are gradually decreasing. As the size of cell transistors decrease, the size of an isolation structure for electrically isolating devices also decreases.

[0004] As a result, techniques for effectively forming a small sized isolation structure have been examined in order to raise the integration level of a semiconductor device. That is to say, as the area of the semiconductor device occupied by the isolation structure decreases, techniques for forming an isolation structure capable of maximizing an insulation effect between elements have become increasingly important.

[0005] Hereinafter, a method for forming the isolation structure of a semiconductor device according to the conventional art will be schematically described with reference to FIGS. 1A and 1B.

[0006] Referring to FIG. 1A, a hard mask composed of a pad oxide layer 111 and a pad nitride layer 112 is formed on a semiconductor substrate 100 such that the isolation regions of the semiconductor substrate 100 are exposed.

[0007] By etching the exposed portions of the semiconductor substrate 100 using the hard mask as an etch mask, trenches 113 are defined in the isolation regions of the semiconductor substrate 100. A sidewall oxide 114, a linear nitride layer 115, and a linear oxide layer 116 are sequentially formed on the surfaces of the trenches 113.

[0008] Referring to FIG. 1B, an insulation layer 115 for isolation is filled in the trenches 113 which are formed with the linear oxide layer 116. The isolation structure 123 of the semiconductor device is formed by CMPing (chemically and mechanically polishing) the insulation layer for isolation. The isolation structure 123 is formed higher than the active regions 110 of the semiconductor substrate 100.

[0009] However, the isolation structure 123 formed according to the conventional art is likely to be gradually lost in a subsequent cleaning process. As a result, the isolation structure 123 has a height, which is lower than that of the active regions 110 of the semiconductor substrate 100.

[0010] FIG. 2 is a view illustrating a state in which an isolation structure is lost by implementing a cleaning process.

[0011] Referring to FIG. 2, as the isolation structure 123 has a height that is lower than that of the active regions 110 of the semiconductor substrate, a phenomenon, i.e., a moat phenomenon, occurs in which portions of the isolation structure 123 are depressed around the active regions 110. The moat phenomenon causes the oxidation of the sidewalls of the active regions 110 during an oxidation process for forming a gate oxide layer and thereby decreases the width of the active regions 110.

[0012] FIG. 3 is a view illustrating a state in which the width of the active region of a semiconductor substrate has decreased.

[0013] Referring to FIG. 3, the phenomenon, in which the width of the active regions 110 decreases by a gate oxidation process, serves as a factor that increases the resistance of the semiconductor device.

[0014] Meanwhile, after the isolation structure 123 is formed, an SEG (silicon epitaxial growth) process for forming an epi-silicon layer on the active regions 110 is implemented.

[0015] FIGS. 4 and 5 are views illustrating states in which epi-silicon layers are formed by an SEG process according to the conventional art.

[0016] Referring to FIG. 4, where the SEG process is implemented with the active regions 110 having a narrow width, the epi-silicon layer 160 can be formed into an abnormal shape.

[0017] Referring to FIG. 5, where the SEG process is implemented with the active regions 110 having a narrow width, a bridge phenomenon can occur between the epi-silicon layers 160.

[0018] Embodiments of the present invention are directed to a method for manufacturing a semiconductor device, which can prevent the loss of an isolation structure.

[0019] Embodiments of the present invention are also directed to a method for manufacturing a semiconductor device, which can prevent the decrease of the width of an active region.

[0020] Embodiments of the present invention are moreover directed to a method for manufacturing a semiconductor device, which can stably form epi-silicon layers.

[0021] In one aspect, a method for manufacturing a semiconductor device comprises the steps of forming trenches in a semiconductor substrate having active regions and isolation regions; forming a first insulation layer at the lower surface of the trenches; forming an etch protection layer on surfaces of the trenches which are filled with the first insulation layer; filling a second insulation layer in the trenches which are formed with the etch protection layer, and thereby forming an isolation structure in the isolation regions of the semiconductor substrate; and recessing portions of the active regions of the semiconductor substrate such that the isolation structure has a height higher than the active regions of the semiconductor substrate.

[0022] The trenches are defined using a hard mask, which is composed of a stack of a pad oxide layer and a pad nitride layer.

[0023] The pad nitride layer is formed to a thickness of 300˜800 Å.

[0024] After the step of defining the trenches and before the step of forming the first insulation layer, the method further comprises the step of forming sequentially a sidewall oxide, a linear nitride layer and a linear oxide layer on entire surfaces of the trenches.

[0025] After the step of forming the linear oxide layer, the method further comprises the step of implementing a cleaning process for the semiconductor substrate formed with the linear oxide layer, using at least one solution among SPM, SC-1, BOE and HF.

[0026] The first insulation layer is formed as a flowable insulation layer.

[0027] The flowable insulation layer is formed through an SOD (spin-on dielectric) process using polysilazane or siloxane sol gel to a thickness of 3,000˜7,000 Å.

[0028] The step of forming the first insulation layer at the lower surface of the trenches comprises the steps of filling a first insulation layer in the trenches; and recessing the first insulation layer.

[0029] The step of recessing the first insulation layer is implemented such that the first insulation layer has a height lower than the trenches by 50˜200 Å.

[0030] After the step of forming the first insulation layer at the lower surface of the trenches and before the step of recessing the first insulation layer, the method further comprises the steps of heat-treating the first insulation layer; absorbing moisture into the heat-treated first insulation layer; and oxidating the first insulation layer which has absorbed moisture.

[0031] The step of heat-treating the first insulation layer is implemented in a furnace using at least one gas among H₂, O₂, H₂O, H₂O₂ and O₃ at a temperature of 200˜650° C. for 20˜200 minutes.

[0032] The step of absorbing moisture into the first insulation layer is implemented by immersing the first insulation layer in DI (deionized) water having a temperature of 50˜95° C. for 5˜60 minutes.

[0033] The step of oxidating the first insulation layer is implemented by exposing the first insulation layer in an SPM solution having a temperature of 100˜250° C. for 5˜30 minutes.

[0034] The etch protection layer can be a nitride layer.

[0035] The etch protection layer is formed to a thickness of 50˜200 Å.

[0036] After the step of forming the etch protection layer and before the step of filling the second insulation layer, the method further comprises the step of forming a thin layer on a surface of the etch protection layer.

[0037] The thin layer can be an oxide layer.

[0038] The thin layer is formed to a thickness of 30˜200 Å.

[0039] The second insulation layer is formed as any one among an HDP layer, a flowable insulation layer and an O₃-TEOS layer.

[0040] The step of recessing the portions of the active regions is implemented such that the active regions have a height lowered by 50˜300 Å at portions of the trenches on which the etch protection layer is formed.

[0041] After the step of recessing the portions of the active regions, the method further comprises the steps of forming gates on the semiconductor substrate; and implementing an SEG process for the recessed semiconductor substrate and thereby forming an epi-silicon layer on the active regions on both sides of the gates.

[0049] In the present invention, an etch protection layer (i.e., a nitride layer) is formed between a first and second insulation for filling trenches. Therefore, the first insulation layer for filling trenches cannot be lost in a subsequent cleaning process due to the presence of the etch protection layer.

[0050] Accordingly, in the present invention, the isolation structure that is composed of the stacked first and second insulation layers for filling trenches is formed higher than the active regions of a semiconductor substrate.

[0051] As a result, in the semiconductor device manufactured according to the present invention, the occurrence of a bridge phenomenon between portions of the epi-silicon layer can be prevented since an epi-silicon layer can be stably formed in an SEG process for increasing the width of the active regions of the semiconductor substrate.

[0052] Hereinafter, a specific embodiment of the present invention will be described in detail with reference to the attached drawings.

[0053] FIGS. 6A through 6G are sectional views illustrating the processes for a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

[0054] Referring to FIG. 6A, a hard mask, composed of a pad oxide layer 611 and a pad nitride layer 612, is formed on the semiconductor substrate 600 having active regions 610 and isolation regions. The hard mask is formed such that the isolation regions are exposed. The pad nitride layer 612 is formed to a thickness of 300˜800 Å. Trenches 613 are defined in the isolation regions of the semiconductor substrate 600 by etching the exposed portions of the semiconductor substrate 600 using the hard mask as an etch mask.

[0055] A sidewall oxide 614, a linear nitride layer 615 and a linear oxide layer 616 are formed on the surfaces of the trenches 613. The linear nitride layer 615 is formed to buffer stress and to prevent oxidation. The linear oxide layer 616 is formed to improve the adhesion property of an isolation structure to be subsequently formed. A cleaning process is then performed on the semiconductor substrate 600 which is formed with the linear oxide layer 616. The cleaning process is performed using at least one solution among SPM, SC-1, BOE and HF. The cleaning process removes the organic substance formed on the surface of the liner oxide layer 616.

[0056] Referring to FIG. 6B, a first insulation layer 621 is filled in the trenches 613. The first insulation layer 621 is formed as a flowable insulation layer. The flowable insulation layer is formed through an SOD process. The flowable insulation layer is formed of polysilazane or siloxane sol gel. The flowable insulation layer is formed to a thickness of 3,000˜7,000 Å. The first insulation layer 621 is baked at a temperature of 50˜400° C. for 30˜600 seconds. The impurities contained in the first insulation layer 621 are removed by the baking.

[0057] The first insulation layer 621 is primarily heat-treated. The first insulation layer 621 is densified through the primary heat treatment. The primary heat treatment is implemented in a furnace using at least one gas among H₂, O₂, H₂O, H₂O₂ and O₃ at a temperature of 200˜650° C. for 20˜200 minutes. The first insulation layer 621 having undergone the primary heat treatment is immersed in DI (deionized) water having a temperature of 50˜95° C. for 5˜60 minutes. As a result of the immersion, moisture is absorbed into the first insulation layer 621 having undergone the primary heat treatment. The first insulation layer 621 having absorbed the moisture is exposed in an SPM compound having a temperature of 100˜250° C. for 5˜30 minutes. As a result of the exposure, the first insulation layer 621 having absorbed the moisture is oxidated. The characteristics of the first insulation layer 621 are improved through the oxidation process.

[0058] The oxidized first insulation layer 621 is CMPed (chemically and mechanically polished) to expose the pad nitride layer 612. The CMPed first insulation layer 621 is recessed leaving a portion partially filling the trenches 613. The first insulation layer 621 is recessed 50˜200 Å below the trenches.

[0059] The recessed first insulation layer 621 is heat-treated a second time. The secondary heat treatment is implemented by annealing at a temperature of 650˜980° C.

[0060] Referring to FIG. 6C, an etch protection layer 631 is formed on the surfaces of the first insulation layer 621 and the trenches 613. The etch protection layer 631 is formed as a nitride layer to a thickness of 50˜200 Å. A thin layer 632 is formed on the etch protection layer 631 to a thickness of 30˜200 Å. The thin layer 632 is formed as an oxide layer having an excellent step coverage characteristic. The thin layer 632 is formed to protect the etch protection layer 631 in subsequent processes.

[0061] Referring to FIG. 6D, a second insulation layer 622 is formed in the trenches 613 in which the first insulation layer 621 is formed. The second insulation layer 622 is filled in the trenches 613 through any one of SOD, HDP (high density plasma) and O₃-TEOS.

[0062] The second insulation layer 622 is tertiarily heat-treated. The second insulation layer 622 is densified through the tertiary heat treatment. The tertiary heat treatment is implemented in a furnace at a temperature of 300˜900° C.

[0063] Referring to FIG. 6E, the second insulation layer 622 is CMPed to expose the pad nitride layer 612. The exposed pad nitride layer 612 is then removed. As a result, an isolation structure 623 (as seen in FIG. 6F) is formed in the trenches 613 comprising the stacked first insulation layer 621 and the second insulation layer 622.

[0064] Meanwhile, after the pad nitride layer 612 is removed, the second insulation layer 622 is heat-treated at a temperature of 600˜980° C.

[0065] Referring to FIG. 6F, the pad oxide layer 611, which is exposed due to the removal of the pad nitride layer 612, is removed. The active regions 610 of the semiconductor substrate 600 which are exposed due to the removal of the pad oxide layer 611 are recessed as indicated by reference numeral 640. As a result, the isolation structure 623 has a height higher than the active regions 610 of the semiconductor substrate 600 due to the recessing of the active regions 610. Preferably, the active regions 610 are recessed 50˜300 Å below the etch protection layer 631.

[0066] Meanwhile, the recessing of the active regions 610 can be selectively implemented in the respective active regions of cell areas and peripheral areas, or only in cell areas using a mask pattern.

[0067] Referring to FIG. 6G, grooves 600H (see FIG. 7) are defined in the gate forming areas of the semiconductor substrate 600 by performing an etching process of the gate forming areas of the semiconductor substrate 600. A gate oxide layer is formed on the semiconductor substrate 600 including the grooves 600H through a gate oxidation process. A stack including a gate conductive layer and a gate hard mask layer is formed on the gate oxide layer. As a result, gates 650 (see FIG. 7) composed of the gate oxide layer, the gate conductive layer, and the gate hard mask layer are formed in and on the grooves 600H. Sources and drains 671 and 672 (see FIG. 7) are formed in the semiconductor substrate 600 on both sides of the gates 650. That is to say, the sources and drains 671 and 672 are formed in the recessed active regions 610.

[0068] An epi-silicon layer 660 is formed on the active regions 610 in the zones of the sources and drains 671 and 672. The epi-silicon layer 660 is formed through an SEG process. The epi-silicon layer 660 can be stably formed on the active regions 610 since the epi-silicon layer 660 is formed to have the width of the active regions 610 and is not decreased.

[0069] FIG. 7 is a plan view of FIG. 6G. FIG. 6G is a sectional view taken along the line X-X′ of FIG. 7.

[0070] Hereinafter, while not shown in the drawings, the semiconductor device according to the embodiment of the present invention is manufactured through a series of well-known processes subsequently performed.

[0071] As is apparent from the above description, in the semiconductor device according to an embodiment of the present invention, an isolation structure composed of first and second insulation layers for filling trenches is formed. An etch protection layer is also formed between the first and second insulation layers.

[0072] Accordingly, in the semiconductor device according to an embodiment of the present invention, a phenomenon in which the isolation structure is lost in a subsequent cleaning process is prevented from occurring due to the presence of the etch protection layer. As a result, a moat is not formed in the isolation structure and the width of the active regions of a semiconductor substrate does not decrease.

[0073] Therefore, in the semiconductor device according to the present invention, an epi-silicon layer can be stably formed by an SEG process and thereby, the contact resistance of elements can be decreased. Also, the epi-silicon layer can be highly formed than the liner nitride layer by present invention and thereby, a HEIP property of PMOS can be removed. Moreover, the epi-silicon layer can be highly formed by present invention and thereby, a short channel effect can be improved. Addition, the portion of the isolation layer at the both sides of the gate functions to support the gate and thereby, the leaning of the gate is prevented.

[0074] Although a specific embodiment of the present invention has been described for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and the spirit of the invention as disclosed in the accompanying claims.