US 8,524,533 B2Grant
Room temperature metal direct bonding
Issue Date:2013-09-03
•25 Claims
•10 Drawing Sheets
Abstract
A bonded device structure including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads formed by contact bonding of the first non-metallic region to the second non-metallic region. At least one of the first and second substrates may be elastically deformed.
Metadata
Assignee
- Ziptronix, Inc.
Inventors
- Qin-Yi Tong
- Paul M. Enquist
- Anthony Scot Rose
Application Information
Application Number:US 12/913,385
Filing Date:2010-10-27
Priority Date:2003-02-07
Art Unit:2813
Classifications
IPC:
H01L21/00
Patent Drawings (10 sheets)
Description
Cross-Reference to Related Applications
[0001] This application is a continuation of application Ser. No. 11/758,386, filed Jun. 5, 2007, which is a continuation of application Ser. No. 11/085,131, filed Mar. 22, 2005, now U.S. Pat. No. 7,602,070, which is a divisional of application Ser. No. 10/359,608, filed Feb. 7, 2003, now U.S. Pat. No. 6,962,835, which is related to application Ser. Nos. 09/410,054, 09/505,283 and 09/532,886, the entire contents of which are incorporated herein by reference.
Background of the Invention
[0002] 1. Field of the Invention
[0003] The present invention relates to the field of direct wafer bonding, preferably at room temperature, and more particularly to the bonding of substrates to be utilized in semiconductor device and integrated circuit fabrication.
[0004] 2. Description of the Related Art
[0005] As the physical limits of conventional CMOS device are being approached and the demands for high performance electronic systems are imminent, system-on-a chip (SOC) is becoming a natural solution of the semiconductor industry. For system-on-a chip preparation, a variety of functions are required on a chip. While silicon technology is the mainstay technology for processing a large number devices, many of the desired circuit and optoelectronic functions can now best be obtained from individual devices and/or circuits fabricated in materials other than silicon. Hence, hybrid systems which integrate non-silicon based devices with silicon based devices offer the potential to provide unique SOC functions not available from pure silicon or pure non-silicon devices alone.
[0006] One method for heterogeneous device integration has been the hetero-epitaxial growth of dissimilar materials on silicon. To date, such hetero-epitaxial growth has realized a high density of defects in the hetero-epitaxial grown films, largely due to the mismatches in lattice constants between the non-silicon films and the substrate.
[0007] Another approach to heterogeneous device integration has been wafer bonding technology. However, wafer bonding of dissimilar materials having different thermal expansion coefficients at elevated temperature introduces thermal stresses that lead to dislocation generation, debonding, or cracking. Thus, low temperature bonding is desired. Low temperature bonding is also crucial for the bonding of dissimilar materials if the dissimilar materials include materials with low decomposition temperatures or temperature sensitive devices such as for example an InP heterojunction bipolar transistor or a processed Si device with ultrashallow source and drain profiles.
[0008] The design of processes needed to produce different functions on the same chip containing different materials is difficult and hard to optimize. Indeed, many of the resultant SOC chips (especially those at larger integration size) show a low yield. One approach has been to interconnect fully processed ICs by wafer adhesive bonding and layer transfer. See for example Y. Hayashi, S. Wada, K. Kajiyana, K. Oyama, R. Koh, S Takahashi and T. Kunio, Symp. VLSI Tech. Dig. 95 (1990) and U.S. Pat. No. 5,563,084, the entire contents of both references are incorporated herein by reference. However, wafer adhesive bonding usually operates at elevated temperatures and suffers from thermal stress, out-gassing, bubble formation and instability of the adhesive, leading to reduced yield in the process and poor reliability over time. Moreover, adhesive bond is usually not hermetic.
[0009] Wafer direct bonding is a technology that allows wafers to be bonded at room temperature without using any adhesive. The room temperature direct wafer bond is typically hermetic. It is not prone to introduce stress and inhomogeneity as in the adhesive bonding. Further, if the low temperature bonded wafer pairs can withstand a thinning process, when one wafer of a bonded pair is thinned to a thickness less than the respective critical value for the specific materials combination, the generation of misfit dislocations in the layer and sliding or cracking of the bonded pairs during subsequent thermal processing steps are avoided. See for example Q.-Y. Tong and U. Gösele, Semiconductor Wafer Bonding: Science and Technology, John Wiley & Sons, New York, (1999), the entire contents of which are incorporated herein by reference.
[0010] Moreover, wafer direct bonding and layer transfer is a VLSI (Very Large Scale Integration) compatible, highly flexible and manufacturable technology, using that to form stacking three-dimensional system-on-a chip (3-D SOC) is highly preferable. The 3-D SOC approach can be seen as the integration of existing integrated circuits to form a system on a chip.
[0011] Moreover, as the integration complexity grows, so do the demands on the integration process to robustly unify diverse circuits at low temperature, preferably at room temperature resulting in lower or non additional stress and more reliable circuits.
[0012] Low or room temperature direct wafer bonding of metal between wafers or die being bonded is desirable for 3D-SOC preparation because this can be used in conjunction with direct wafer bonding of non-metal between wafers or die to result in electrical interconnection between wafers or die being bonded when they are mechanically bonded and thus eliminate the need to for post-bond processing, like substrate thinning, via etching, and interconnect metalization, to achieve an electrical interconnection between bonded wafers or die. Very small bonding metal pads can be used resulting in very low parasitics and resulting reduced power and increased bandwidth capability.
[0013] Bonding of metals with clean surfaces is well-known phenomenon. For example, thermocompression wire bonding has been applied to wafer-level bonding. Temperature, pressure and low hardness metals are typically employed and usually results in residual stresses. For example, see example, M. A. Schmidt, Proc. IEEE, Vol. 86, No. 8, 1575 (1998), Y. Li, R. W. Bower, I. Bencuya, Jpn. J. Appl. Phys. Vol. 37, L1068 (1988). Direct bonding of Pd metal layer covered silicon or III V compound wafers at 250-350° C. has been reported by B. Aspar, E. Jalaguier, A. Mas, C. Locatelli, O. Rayssac, H. Moricean, S. Pocas, A. Papon, J. Michasud and M. Bruel, Electon. Lett., 35, 12 (1999). However, actually Pd2Si silicide or Pd-III V alloys, not metal Pd, are formed and bonded. Bonding of Au and Al at room temperature has been achieved by using ultrasonic and compressive load at flip chip bonding, see example, M. Hizukuri, N. Watanabe and T. Asano, Jpn. J. Appl. Phys. Vol. 40, 3044 (2001). Room temperature metal bonding at wafer level has been realized in ultrahigh vacuum (UHV) systems with a base pressure lower than 3×10−8 mbar. Usually an ion argon sputtering or fast atom-beam is used to clean the bonding surfaces followed by application of an external pressure to the bonding substrates. See for example, T. Suga, Proc. The 2nd Intl. Symposium on semiconductor wafer bonding, the Electrochemical Soc. Proc. Vol. 93-29, p. 71 (1993). Room temperature bonding between two Si substrates with thin sputtered Ti, Pt and Au films has also been accomplished using applied force after thin film sputter deposition at 4-40/μbar of Ar pressure in a UHV system with base pressure less than 3×10−8 mbar. See for example, T. Shimatsu, R. H. Mollema, D. Monsma, E. G. Keim and J. C. Lodder, J. Vac. Sci. Technol. A 16(4), 2125 (1998).
Summary of the Invention
[0014] An object of the present invention is thus to obtain mechanical and electrical contact between wafers and die with a single bonding step.
[0015] Another object of the present invention is to provide a low or room temperature bonding method by which metallic bonding between wafers or die of semiconductor circuits can be formed in ambient without using external pressure.
[0016] An additional object of the present invention is to provide a low or room temperature bonding method by which metallic bonding of layers of any metal between wafers or die of semiconductor circuits can be formed at room temperature at wafer level in ambient without using external pressure by covering metal layers with a thin film of gold or copper or palladium.
[0017] Still another object of the present invention is to provide a room temperature bonding method at wafer level in ambient without using external pressure by which metallic as well as covalent bonds are formed simultaneously at room temperature on bonding surfaces of wafers or die comprised of semiconductor circuits where metal and other non-metal layers co-exist.
[0018] Another object is to provide a room temperature bonding method by which different substrates or different materials on different substrates with different thermal expansion coefficients can be bonded together without generation of catastrophic stresses between the different substrates or different materials on different substrates.
[0019] Still another object of the present invention is a room temperature bonding method by which the bond strength between substrates approaches the mechanical fracture strength of the substrates.
[0020] Another object of the present invention is to provide a bonded device structure including devices fabricated individually on separate substrates and bonded on a common substrate.
[0021] A still further object of the present invention is to provide a method and device whereby a reliable mechanical bond can be formed at or near room temperature and a reliable electrical contact can be subsequently formed with a simple low temperature anneal.
[0022] These and other objects of the present invention are achieved by a bonded method and device structure including a first substrate having a first plurality of metallic bonding pads, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second plurality of metallic bonding pads, preferably connected to a second device or circuit, aligned or alignable with the first plurality of metallic bonding pads and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads formed by either elastic deformation of elements within the first substrate and the second substrate that is a direct result of forces generated by direct wafer bonding of the first non-metallic region to the second non-metallic region, or by reflow of metal in the vicinity of the first and second sets of metallic bonding pads after direct wafer bonding of the first non-metallic region to the second non-metallic region.
Brief Description of the Drawings
[0023] A more complete appreciation of the present invention and many attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:
[0024] FIG. 1A is a schematic depiction of a pair of unbonded substrates having aligned metal bonding pads;
[0025] FIG. 1B is a schematic depiction of a pair of unbonded substrates having the aligned metal bonding pads contacted;
[0026] FIG. 1C is a schematic depiction of a pair of contacted substrates, according to the present invention, bonded in a non-metal region away from the metal bonding pads;
[0027] FIG. 1D is a schematic depiction of a pair of contacted substrates, according to the present invention, bonded across the non-metal regions except for a small unbonded ring area near the metal bonding pads;
[0028] FIGS. 2A-2C are schematic diagrams illustrating bonding substrates with multiple bonding pads;
[0029] FIG. 2D is graph, according to the present invention showing the width of an unbonded ring area W as a function of the metal pad thickness 2 h separating the semiconductor dies as shown in the insert;
[0030] FIG. 3A is a schematic depiction of semiconductor die or wafer after surface planarization;
[0031] FIG. 3B is a schematic depiction of semiconductor die or wafer in which second metal layer are formed and planarized with contact windows opened on metal pads;
[0032] FIG. 3C is a schematic depiction of second semiconductor die or wafer with a second metal layer.
[0033] FIG. 3D is a schematic depiction of an aligned metal bonding of two dies or wafers, according to the present invention;
[0034] FIG. 4A is a schematic depiction of a part of a substrate showing imbedded metal pads in an oxide coating;
[0035] FIG. 4B is a schematic depiction of a pair of unbonded substrates, according to the present invention, having reciprocal metal bonding pads;
[0036] FIG. 4C is a schematic depiction of a pair of bonded substrates, according to the present invention, showing the reciprocal metal bonding pads contacted by the forces generated when the non-metal regions contacted and bonded;
[0037] FIG. 4D is a schematic depiction of a pair of smaller substrates bonded to a larger substrate;
[0038] FIG. 5A is a schematic diagram of an embodiment of the invention having a deformable material or void beneath the metal pad;
[0039] FIG. 5B is a schematic diagram of an embodiment of the invention having a deformable material beneath the metal pad;
[0040] FIG. 5C is a schematic diagram of two devices as shown in FIG. 5A bonded together.
[0041] FIG. 6A is a schematic diagram of an embodiment of the invention having reflowable metal material exposed to the surface on two devices prior to direct wafer bonding of the non-metal surfaces.
[0042] FIG. 6B is a schematic diagram of an embodiment of the invention having reflowable metal material sealed by after direct wafer bonding of the non-metal surfaces.
[0043] FIG. 6C is a schematic diagram of an embodiment of the invention having reflowable metal reflowed after direct wafer bonding of non-metal surfaces sealed the reflowable metal.
[0044] FIG. 7A is a schematic diagram of an embodiment of the invention having reflowable metal material exposed to the surface on two devices prior to direct wafer bonding of the non-metal surfaces.
[0045] FIG. 7B is a schematic diagram of an embodiment of the invention having reflowable metal material sealed by after direct wafer bonding of the non-metal surfaces.
[0046] FIG. 7C is a schematic diagram of an embodiment of the invention having reflowable metal reflowed after direct wafer bonding of non-metal surfaces sealed the reflowable metal.
Detailed Description of the Preferred Embodiments
[0047] Referring now to the drawings, wherein like reference numerals designate like or corresponding parts throughout the several views, and more particularly to FIGS. 1A-1D and 2 illustrating a first embodiment of the bonding process of the present invention. In the first embodiment of the present invention, direct metal-metal bonding is generated when metal contact regions on separate wafers upon alignment are contact pressure bonded by the intrinsic forces generated when non-metallic regions peripheral to the metallic regions undergo room-temperature chemical bonding. Chemical bonding as used throughout this specification is defined as a bond strength developed when surface bonds on the surface of one wafer react with the surface bonds on the surface of an opposing wafer to form direct bonds across the surface elements, such as a covalent bond. Chemical bonds are manifest by their high bond strengths, approaching for instance the fracture strength of the wafer materials, and thus are differentiated for example from mere Van der Waals bonding. Examples of chemical bond strengths achieved by the methods of the present invention are discussed below. In the chemical bonding process, substantial forces are developed. These forces can be sufficiently great to elastically deform the metallic regions as the chemical bond propagates between the opposed non-metallic regions.
[0048] FIG. 1A shows two wafers 10, 13 with respective opposing wafer surfaces 11, 14. The wafer surfaces may be pure elemental semiconductor surfaces, may be pure elemental semiconductor surfaces including a relatively small amount of native oxide, or may be an insulator such as oxide-coated surface. The surfaces may be prepared as described in application Ser. Nos. 09/410,054, 09/505,283 and 09/532,886, to produce a smooth, activated surface. Techniques such as polishing or polishing and very slightly etching (VSE) may be used. A bonding layer may be deposited and polished or polished and slightly etched. The resulting surfaces are complementary and have chemical bonding surfaces that are planar and smooth, having chemical bonding surface roughness in the range of 5-15 Å, preferably no more than 10 Å, and more preferably no more than 5 Å.
[0049] Each wafer includes a set of metallic pads 12, 15 and a non-metallic region adjacent to the metallic bonding pads in the surfaces 11, 14. The non-planarity and surface roughness of the metallic bonding pads may be larger than that of the chemical bonding surfaces. Pads 12, 15 may be used to route electrical connections to the respective devices and/or circuits pre-fabricated on the wafers. The pads are preferably formed before surface treatment, and VSE is preferably performed after the pads are formed. As shown in FIG. 1A , pads 12, 15 are on the respective wafers are aligned. FIG. 1B shows the wafers upon placing the wafers together to contact the respective pads. At this stage, pads 12, 15 would be separable. In FIG. 1C , slight additional pressure is applied to the wafers to elastically deform one or both of the semiconductor wafers, resulting in contact between some of the non-metal areas on the wafers. The location shown of the contacting is an example, and the contact may occur at different locations. Also, the contact may occur at more than one point. This contact initiates chemical wafer-to-wafer bonding, and the bonded structure is shown in FIG. 1D . The bonding seam 16 expands after the initial chemical bonding to produce bonding seam 17 shown in FIG. 1D . The bond strength is initially weak and increases as the bonding propagates, as explained in Ser. Nos. 09/410,054, 09/505,283 and 09/532,886. The opposing non-metallic regions are chemically bonded at room or low temperature.
[0050] In more detail, as the wafer surfaces including the metal bonding pads contact at room temperature, the contacting non-metal parts of opposing wafer surfaces began to form a bond at the contact point or points, and the attractive bonding force between the wafers increases as the contact chemical bonding area increases. Without the presence of the metal pads, the wafers would bond across the entire wafer surface. According to the present invention, the presence of the metal pads, while interrupting the bonding seam between the opposing wafers, does not prohibit chemical wafer to wafer bonding. Due to the malleability and ductility of the metal bonding pads, the pressure generated by the chemical wafer-to-wafer bonding in the non-metal regions may results in a force by which nonplanar and/or rough regions on the metal pads may be deformed resulting in improved planarity and/or roughness of the metal pads and intimate contact between the metal pads. The pressure generated by the chemical bonding is sufficient to obviate the need for external pressure to be applied in order for these metal pads to be intimately contacted to each other. A strong metallic bond can be formed between the intimately contacted metal pads, even at room temperature, due to inter-diffusion or self-diffusion of metal atoms at the mating interface. This diffusion is thermodynamically driven to reduce the surface free energy and is enhanced for metals that typically have high inter-diffusion and/or self-diffusion coefficients. These high diffusion coefficients are a result of a cohesive energy that is typically mostly determined by the mobile free electron gas that is not disturbed by the motion of metal ions during the diffusion. The wafer-to-wafer chemical bonding in the non-metal regions thus effects electrical connection between metal pads on the two different wafers. The geometrical and mechanical constraints governing this effect are described below.
[0051] An unbonded area around the bonding pad having a width W will be generated in which the non-metal surfaces of the two wafers are precluded from contacting (see FIG. 1D ). As long as the thickness of metal films is not too large, the gaps between two bonding wafers or dies can be reduced leaving a small unbonded area around each metal pad. This is illustrated in FIGS. 2A-2C , where wafer 20 with metal pads 21 is ready to be bonded to wafer 22 with pads 23. A gap 24 is between adjacent pads. The metal pads are contacted (FIG. 2B ) and the wafers elastically deform to bond in the gaps 24 to form bonds 25 (FIG. 2C ). It is noted that the dimensions in FIGS. 2A-2C are not to scale.
[0052] The formula to calculate the width of the unbonded area as a function of metal film thickness, mechanical properties of the wafer or die, the wafer or die thickness, the bonding energy will be shown below. FIG. 2D is a graph showing the relationship between the gap height 2 h and the width w of an unbonded area. When the deformation of the wafers obeys an elastic constant given by Young's modulus E and the wafers each have a thickness of tw, according to the simple theory of small deflection of a thin plate, the width W of the unbonded area can be roughly estimated by the following equation for W>2tw, where the metal bonding pads as a pair have a height of 2 h above the wafer surface:
W=[(2E′tw3)/(3γ)]1/4h1/2 (1)
W=[(2E′tw3)/(3γ)]1/4h1/2 (1)
[0053] where E′ is given by E/(1−ν2) with ν being Poisson's ratio.
[0054] It has been suggested that with decreasing h, the situation changes drastically. See for example, U. Goesele and Q.-Y. Tong, Proc. The 2nd Intl. Symposium on semiconductor wafer bonding, the Electrochemical Soc. Proc. Vol. 93-29, p. 395 (1993). If W calculated by Eq. (1) leads to values below Wcrit=2tw, corresponding to h<hcrit where hcrit=5(twγ/E′)1/2, then an elastomechanical instability is supposed to occur, leading to an unbonded area with much smaller W that is independent of wafer thickness tw, and is given by:
W≈kh (2)
W≈kh (2)
[0055] where k is a dimensionless constant on the order of 1. Experimentally, as shown in FIG. 2D if h<300 Å, W is much smaller than what is predicted by Eq. (1). Further work by the inventors of the present application has shown that, if the spacing between metal bonding pad pairs 2 R is smaller than 2 W, the wafer pairs may not bond to each other. However, when 2 R>2 W, surfaces between the two unbonded areas around the metal posts will bond and the metal posts will be bonded and electrically connected.
[0056] The pressure P on the metal bonding pairs that is generated by the bonding of the surrounding area can be expressed as:
P=(16E′tw3h)/(3W4) (3)
P=(16E′tw3h)/(3W4) (3)
[0057] Combining Eq. (3) with Eq. (1) or (2), when W>2 tw, the following is obtained:
P=8γ/3h, (4)
and when W<2 tw, the following is obtained:
P=(16E′tw3)/(3k4h3) (5)
P=8γ/3h, (4)
and when W<2 tw, the following is obtained:
P=(16E′tw3)/(3k4h3) (5)
[0058] For bonded silicon wafers where the metal pads have height h of 500 Å and the bonding energy is 300 mJ/m2, the compressive pressure on the metal bonding pads is about 1.6×108 dynes/cm2, i.e. 160 atmospheres. Since this pressure is sufficiently high for metal bonding, there is no need to apply any external pressure during bonding. When metal height h is 300 Å or less, W<2tw is satisfied and the pressure on the metal pairs is in the order of 5000 atmospheres if k=1 is assumed.
[0059] In one example of the first embodiment of the present invention, 5 mm diameter Au bonding pads with a thickness less than 300 Å and a separation distance of 1 mm were deposited on oxide covered 100 mm silicon wafers. Since the Au bonding pads were formed on the surface of the oxide, they also had a height of 300 Angstroms above the surface of the oxide. However, h can be much smaller than actual metal thickness since metal cam be partially buried in oxide or other insulator and h is the height the metal extended above the die surface. A room temperature bonding technology has been developed that cleans and activates the metal and the oxide surfaces compatibly and simultaneously. The Au posts formed a metallic bond by room temperature bonding at wafer level in ambient without using external pressure after storage in air for a period of time, e.g. 60 hr depending on the metal thickness and bonding energy. When the wafer pairs were forcibly separated, by inserting a wedge between the bonded interface, either the Au or the Au/oxide layer peeled from the silicon substrate, indicating that the metal-to-metal bond formed was stronger than the adhesion of the Au pad on the oxide surface or the oxide on the silicon surface. As mentioned above, a strong metallic bond can be formed between the intimately contacted metal pads at room temperature due to inter-diffusion or self-diffusion of metal atoms on the mating interface to reduce the surface free energy. The inter-diffusion or self-diffusion coefficient between metal atoms increases exponentially with temperature, in order to shorten the storage time to achieve full metallic bonding, annealing can be performed after room temperature bonding. The preferred annealing time for metallic bonding between the Au posts shortened as the temperature increased. For this case, 5 hr was preferred for 100° C., 1 hr for 150° C., and 5 min for 250° C. Thinner metals require lower temperatures for bonding than thicker metals due to higher pressure generated by the bonding of non-metal surrounding areas. The time for the formation of metallic bond at room temperature and at elevated temperatures becomes longer as the Au thickness (i.e., height) increases. For example, when the thickness of Au pads h is 600 Å, 5 min at 250° C. is needed to form metallic bond while at h=500 Å, 15 min is required.
[0060] In flip-chip bonding of state-of-the art integrated circuits, the solder ball pitch is about 1000 μm. Therefore, an unbonded area width around the bonded metal posts that is comparable or less than 1000 um is sufficiently small for practical applications. Unbonded area widths substantially less than this amount can be obtained by this method. For example, experimental results show that when h=200 Å, W is 20 μm, and when h=300 Å, W is 30 μm. Because h is the height the metal extended above the die surface, h can be much smaller than actual metal thickness since metal can be partially buried in oxide or other insulator, h less than 200 Å can be readily achieved. In this case the unbonded ring width around the metal pads can be close to zero. The metal pad described above may be formed by processes such as, but not limited to, sputtering, evaporation, laser ablation, chemical vapor deposition, and other techniques know to those skilled in the art in which thickness control in the <100 Angstrom range is typical.
[0061] FIGS. 3A-3C are schematic drawings of a process according to a second embodiment of the present invention, by which two different fully processed dies are bonded. The dies are shown to have planar but uneven layer thickness, to demonstrate that the invention may be used in other instances other than even and planar layer thicknesses. In this process, as shown in FIG. 3A , a separate die 30 (only the oxide layer of die 30 is shown, for convenience of explanation) has metal pads 31. The die may be a silicon wafer including semiconductor devices and circuits have opposing surfaces of SiO2. Surface 32 results after a CMP operation.
[0062] As shown in FIG. 3B , vias 36 have been formed and filled with metal to connect with metal pads 31, metal interconnects 33 are formed on wafer 30 to connect with the metal in vias 36, and a layer 34 of thickness t2, of SiO2 or other insulating material is formed on wafer 30. Portions 35 of the SiO2 layer having a width w2 have been removed to expose metal pads 35. The surface of layer 34 is treated as described in copending application Ser. Nos. 09/410,054, 09/505,283 and 09/532,886, including polishing or polishing and slightly etching.
[0063] In FIG. 3C , a second wafer 37 has pads 38, vias 39 filled with metal, and interconnects 40 formed as shown. Interconnects 40 have a width w1 and a height t1. Surface 41 of wafer 37 has been treated like surface 32, as discussed above. The separate dies 30 and 37 are aligned and contacted one to another to produce the bonded structure shown in FIG. 3D . With the following relationships:
t1=t2+δ1 and w1=w2+δ2,
t1=t2+δ1 and w1=w2+δ2,
[0064] where t1 and δ1 are preferred to be the minimum thickness possible for the deposition technology used, and δ2 should be 2 W corresponding to the case of 2h=t1. Compared with h=t1 on both dies to be bonded, unbonded area width W is significantly reduced. Thus interconnection between the pads on wafers 30 and 37 is made. If t1 on both dies is less than the critical thickness hcrit then no layer 34 is required.
[0065] During the initial contacting of the two wafers at room temperature, the metal pads are aligned, and the surfaces of the wafers, according to the present invention, conform to each other by elastic deformation, provided the gap due to the surface topography of bonding wafers is sufficiently small and the bonding energy γ is sufficiently high. According to the present invention, direct bonding occurs between the contacted materials forming the metal interconnects between devices or circuits on adjoining dies and between the wafer surfaces. The bond begins to form on contact and the bond strength increases, at room temperature, to form a metallic bond.
[0066] As in the first embodiment, wafer surfaces 32 and 41 including metal pads 33 and 40 contact, the contacting non-metal parts of opposing wafer surfaces 32 and 41 began to form a bond at the contact points, and the bonding force increases as the contact bonding area increases. Without the presence of metal pads 33 and 40, the wafers would bond across the entire wafer surface. According to the present invention, the presence of metal pads 33 and 40, while interrupting the bonding seam between the opposing wafers, does not prohibit wafer to wafer bonding. Rather, the pressure generated by the wafer-to-wafer contact in the non-metal regions translates into a force by which metal pads 33 and 40 are contacted. No external pressure is required.
[0067] The method of the present invention can be carried out in ambient conditions rather than being restricted to high or ultra-high vacuum (UHV) conditions. Consequently, the method of the present invention is a low-cost, mass-production manufacturing technology. The size of metal films to be bonded is, according to the present invention, flexible and scalable to very small geometries because direct metallic bonding depends only on inter-molecular attraction force.
[0068] Direct metal bonding is preferable for better thermal management and power capability of semiconductor devices. The direct metal bonding, according to the present invention, can replace flip-chip bonding with much smaller bonding pads that are scalable. It is further possible that this metal bonding can be used to realize novel metal base devices (semiconductor-metal-semiconductor devices) see for example, T. Shimatsu, R. H. Mollema, D. Monsma, E. G. Keim and J. C. Lodder, IEEE Tran. Magnet. 33, 3495 (1997).
[0069] Further, the process is compatible with VLSI technology. The direct metal-to-metal bonding may be performed when wafers are fully processed. The direct metal-to-metal bonding of the present invention also utilizes room temperature bonding to minimize effects from the difference in thermal expansion, since almost all metals have significantly higher thermal expansion coefficients than silicon or silicon dioxide.
[0070] The present invention can bond locally or across an entire wafer surface area. The present invention, while not limited to the following examples, bonds heterogeneous surfaces such that metal/metal, oxide/oxide, semiconductor/semiconductor, semiconductor/oxide, and/or metal/oxide regions can be bonded between two wafers at room temperature.
[0071] Numerous advantages are offered by the present invention. For example, other methods of wafer bonding and electrically interconnected constituent electrical contacts require thinning of bonded substrates, via etching and metal deposition after wafer bonding. The present invention eliminates the need for these post-bond process steps to form electrical interconnections. Advantages of this elimination include the elimination of mechanical damage caused by the die thinning. Furthermore, the elimination of deep via etching avoids step coverage problems and allows the electrical connection to be scaled to smaller dimensions, resulting in an electrical interconnection with a smaller footprint and reduced electrical parasitics between bonded wafers. The method is compatible with other standard semiconductor processes, and is VLSI compatible.
[0072] As such, the present invention is compatible with 3-D SOC (three-dimensional system-on-a chip) fabrication. This vertical metal bonding of metal pads or interconnects using plugs between bonded dies significantly simplifies the SOC fabrication process and improves the SOC speed-power performance. The direct metal-to-metal bonding of the present invention is scalable and can be applied to multi-die stacking SOC.
[0073] Besides generation of the requisite force necessary to form metal-to-metal connections, the present invention recognizes that low resistance is desirable for the electrical interconnections from one device to another. Low resistance metal bonding is facilitated, according to the present invention, by oxide-free or nearly oxide-free surfaces of the metal bonding metal pads. For example, Au surface can be cleaned by ultraviolet/ozone and nitrogen plasma with no oxide left on the surfaces.
[0074] In another embodiment of the present invention, the surfaces of the bonding metal pads (fabricated for example from metals such as Al or Cu are coated with oxidation resistant metals, such as for example with gold (Au) or platinum (Pt) layer. Since both Au and Pt are inert metals, no oxide will be formed on the surfaces. To ensure that there is a minimum amount of oxide between Au or Pt and the host metal, sputter cleaning and evaporation deposition are employed, preferably immediately prior to the bonding process.
[0075] In a modification of the first embodiment of the present invention, a thin metal overcoat layer may be formed on the metal pad and bonded as described above. For example, a layer as thin as 50 Å of an Au layer on an Al pad produced successful metal pad bonding at room temperature. Therefore, metals such as Au can be used as a bonding layer, enabling almost all metals to be utilized for direct bonding at room temperature by the procedures of the present invention. When an insulator layer is deposed on a fully processed wafer and contact openings are formed on the metal pads followed by a metal deposition with thickness 100 Å more than the depth of the contact windows, the metal pads now are extended above oxide layer only 100 Å, the pads can be separated each other by a very small distance, e.g. 20 μm.
[0076] Besides Au or Pt, palladium (Pd) has been utilized in the present invention as an overcoat layer Pd has good oxidation resistance. The surface diffusivity of Pd on Pd is very high resulting in a significant mass transport of Pd even at room temperature, especially given the contacting pressures exerted on the metal bonding pads by the bonding of the non-metal wafer surface regions. The native oxide between the two Pd bonding layers, if any, will be mechanically dispersed allowing complete coverage with Pd of the physical interface between the two contacted metal bonding pads.
[0077] In another modification of the first embodiment of the present invention, a UV/ozone cleaning exposes the surfaces of the metal bonding pads to high ozone concentrations under a UV light to remove hydrocarbon contamination. Residual hydrocarbons on the surfaces of the metal bonding pads degrade metal bonding, and are nucleation sites for bubble formation between the bonding interfaces, resulting in out-gassing between the contacted surfaces.
[0078] Experiments have shown that UV/ozone treatments can prevent interface bubble formation. An HF dip of silicon wafers leads to hydrophobic surfaces that are terminated mostly by H. The hydrophobic silicon wafers are treated with 4.77 g/m3 of ozone concentration combined with 1850 Å and 2540 Å UV irradiation from two 235 W UV lamps at room temperature for 15 min. followed by a second HF dip and bonding. The bonded pairs of HF dipped hydrophobic silicon wafers generated no interface bubbles upon annealing from 300° C. to 700° C. for 15 hrs at each temperature clearly indicating the effective removal of hydrocarbons from the wafer surfaces.
[0079] For Au and Pt, it is adequate to use UV/ozone cleaning before bonding without formation of metal oxide on the metal surfaces. For other metals that can be oxidized by ozone, a thin layer of Au on the metals can prevent oxidation, or the oxide can be removed by e.g. immersion in NH4OH before bonding. In addition, plasma treatment with inert gases, for example plasma treatments in a reactive ion etch mode (RIE) with only inert gasses such as nitrogen and argon in the plasma chamber, can according to the present invention can clean metal surfaces and enhance the bonding energy at room temperature for both metal/metal and oxide/oxide bonds. Further, the present invention has discovered that an oxygen plasma can be used to remove contamination from the surface of metals such as Au and Pt.
[0080] While numerous surface preparation treatments and metal/metal and oxide/oxide and semiconductor/semiconductor examples have been described, other surfaces and preparation procedures could be used, according to the present invention, in which the corresponding metal, insulator, and semiconductor surfaces are sufficiently cleaned prior to contact such that the formation of room temperature bonding is not inhibited. In the case of Au protection or Au bonding, the process developed by the present invention is metal and silicon dioxide compatible. After CMP and surface planarization and smoothing of the oxide surfaces, metal bonding pads are formed on bonding wafers as described above, a modified RCA 1 (H2O:H2O2:NH4OH=5:1:0.25), UV/ozone, and plasma treatment clean the surfaces of both metal and oxide without roughening the bonding surfaces. A room temperature standard 29% NH4OH dip removes particles and oxide on the metal surfaces if any without degrading the silicon dioxide surfaces. After spin-drying and room temperature bonding and storage, strong covalent bond and metallic bond are formed spontaneously at bonding inter face between oxide layers and metal surfaces, respectively. Besides the near planar bonding structures shown in FIGS. 1A-1D , other structures can also utilize the principles of the present invention. For example, a second embodiment is shown in FIGS. 4A-4C , where wafers including metal via interconnections are bonded to a smaller die. FIG. 4A depicts a magnified view of a substrate 50 including metal interconnects 51. In FIG. 4A , the metal interconnects are embedded in a silicon dioxide layer 52 such as a PECVD oxide, thermal oxide, or spin-on glass. Interconnects 51 extend above the layer 52 to a height as discussed previously. FIG. 4A also shows smaller die 53 having metal contact 54 and silicon dioxide layer 55.
[0081] Following forming an insulating layer 58 on both dies of a material such as silicon dioxide, a standard via etch and metal fill, followed by chemical mechanical polish and surface treatment are used to prepare the layers 58 for bonding. FIG. 4B depicts a pair of opposing wafers with reciprocal metal bonding pads 56 and 57. FIG. 4C shows the contacting and subsequent bonding of these two opposing substrates, forming bond 59.
[0082] Here, as before, the bonding of the non-metal regions generates the requisite forces to form the metal-to-metal interconnections across the dies. As depicted in FIG. 4C , the bonding of the oxide layers generates the requisite bonding force for direct metal-to-metal contact of the metal bonding pads 56 and 57. A plurality of dies 53 may be prepared and bonded to die 60, as shown in FIG. 4D .
[0083] In the metal-to-metal direct bonding of the first and second embodiments of the present invention, the thickness of bonding metal films extended above die surface is preferably thin to minimize the unbonded ring area around the metal posts. Further, the thickness of bonding metal pads is scaleable, and VLSI compatible size metal posts or pads can be made and bonded. When the metal film thickness is below a certain value, the width of the unbonded ring area is significantly reduced so that the spacing between metal posts permits small spacing (e.g. <10 μm) between the metal bonding pads to be used.
[0084] A third embodiment of the invention allows a significant increase in the metal height above the non-metal surface and/or significant reduction in non-bonded area near the metal while maintaining an acceptable electrical connection between metal portions formed on separate wafers. In this embodiment, deformation of material in the vicinity of the metal material that forms the electrical contact is designed to result from the pressure at the metal surfaces from the wafer-to-wafer chemical bonding of the non-metal portions. This deformation may result in less pressure applied to the metal after the bonding process is complete, but adequate pressure to form an acceptable electrical connection between the metal portions. This deformation allows the gap near the metal surfaces to be significantly reduced or eliminated.
[0085] The object of the deformable material in the vicinity of the metal material forming the electrical contact is to allow the pressure generated by the chemical bonding of the non-metal surfaces to be sufficient to recess the metal material sufficiently into its respective surface so that the gap near the metal surface can be significantly reduced or eliminated. In general, the deformable material is comprised of non-metal portions because the pressure generated by the wafer-to-wafer chemical bonding is typically about one part in 10,000 or 1% of 1% of that required to deform typical metals. The recess of the metal into its respective surface allows the starting height of the metal surface above the non-metal surface to be substantially higher than after the recess. This significantly increases the tolerances of the metal surface required to prepare the wafers for bonding and subsequently the manufacturability of the embodiment. The deformation also substantially reduces or eliminates the non-bonded region around the metal allowing a substantial increase in the number of connections that can be made in a given area and increasing the bond strength of the bonded and interconnected parts.
[0086] The deformation is enabled by the inclusion of a non-metal region underneath the metal surface, as illustrated in FIG. 5A . A die with a substrate 55 has a metal pad 50 formed on a layer 51 that is to be bonded to a corresponding layer on another device. Region 53, filled with a deformable non-metal material such as a low K dielectric material, is formed in layer 52 by standard photolithography, etching and deposition techniques. Layer 52 and region 53 are formed on layer 54. Any number of layers may be formed on substrate 54. Also, region 53 may be much larger or layer 52 may be formed of the low K material, as shown in FIG. 5B .
[0087] Region 53 may also be a void containing a vacuum or compressible gas like air, or it may be a compressible non-gas solid material with a sufficiently low compressibility that the pressure generated by the bonding will deform the metal into the region. The void may be formed in a manner similar to that used to fabricate metallic air bridges common in compound semiconductor integrated circuit fabrication. One example of this fabrication is as follows: 1) etch a recess in a planar, non-metal surface, 2) fill the recess with a removable material like photoresist such that the removable material is in the recess, but not outside the recess. This may, for example, be done by conventional spin coating of photoresist, resulting in a thicker photoresist in the recess than outside the recess, followed by blanket (non patterned) etching of the photoresist of an amount sufficient to remove the material outside the recess but not sufficient to remove the material in the recess, 3) patterning a metal feature that transverses the recess but does not entirely cover the recess, leaving an exposed portion of the recess, and 4) removal of the removal material in the recess by accessing the exposed portion of the recess. An example of a compressible non-gas solid material is a low K dielectric used in semiconductor manufacturing. The depth of this region is typically comparable to or greater than the desired height of metal above the non-metal surface. Another die to which the die of FIG. 5A is to be bonded may also have a region such as region 53 in a corresponding position beneath a metal pad to be bonded to pad 50. This is illustrated in FIG. 5C , where it is noted that FIG. 5C is a schematic drawing and is not shown to scale. Here, pads 50 and 56 are bonded by the compressive force generated by bonding of layers 51 and 57. The upper die in FIG. 5C includes a substrate 61 with pad 56 formed over void or low K material region 59 in layer 58. Layer 58 is formed on layer 59. Again, the upper die may have many layers.
[0088] In this embodiment, when the wafers are bonded, the metal surfaces are contacted and deformation with respect to each other occurs during the chemical bonding process. The deformation relieves some of the pressure applied by the bonding process, but sufficient pressure remains to maintain the metal surfaces in contact and maintain an acceptable minimum contact resistance between the two metal surfaces on the two separate wafers. As the metal deforms into the region under the metal, the bonding surfaces are allowed to come into contact in a lateral annulus very close or immediately adjacent to the metal, resulting in a maximum bonding area between the non-metal surfaces. A minimum chemical non-bonded region of 1-10 microns, or less, adjacent to the metal contact, can thus be formed by the present invention.
[0089] The deformable region is designed to have a minimum width to maximize the number of possible electrical interconnections. The deformable region width primarily depends on the metal thickness and the metal height above the non-metal surface. These parameters are approximately determined by the following relations.
Stress=(⅔)*(Young's Modulus of Metal)(1/1−Metal Poisson's Ratio)*(metal height above surface/half width of region)2
Stress=(⅔)*(Young's Modulus of Metal)(1/1−Metal Poisson's Ratio)*(metal height above surface/half width of region)2
[0090] and
Pressure=Stress*4*metal thickness*metal height above surface/(half width of region)2
Pressure=Stress*4*metal thickness*metal height above surface/(half width of region)2
[0091] Where the pressure is that generated by the bonding process. A reference for these relations can be found in the “Handbook of Thin Film Technology”, Maissel and Glang, 1983 Reissue, pp 12-24.
[0092] For example, for a metal thickness of about 0.1 micron and a metal height above the region of about 0.1 micron above the surface and a region width of about 1 micron, the pressure generated during bonding is approximately sufficient to deform the metal into the region (assuming compressibility of the region can be neglected). Note that this 0.1 micron metal height would have resulted in an unbonded annulus or ring width around the metal of about 1 mm if the metal was not deformable. The manufacturability is thus increased substantially by requiring less control of the metal height above the non-metal surface. Furthermore, the non-bonded area is substantially decreased allowing a significant increase in the number of metal to metal contacts that can be made and resulting in an increase in the chemical bonding energy. If the compressibility of the region can not be neglected, than the thickness of the metal needs to be reduced accordingly and/or the metal height above the non-metal surface needs to be reduced accordingly and/or the width of the region needs to be increased accordingly. Note that the percentage amount the width of the region needs to be increased is less than the percentage amount the metal height above the non-metal surface, or the metal thickness, needs to be reduced.
[0093] A fourth embodiment of the invention further relaxes the mechanical design constraints in the vicinity of the metal contacts described in the first, second, and third embodiments by relying on a low temperature, post-bond reflow anneal to form reliable electrical interconnections between chemically bonded wafers. A description of this embodiment is provided with reference to FIGS. 6A-C and 7A-C.
[0094] FIG. 6A shows substrates 60 and 61 with planar surfaces. Recesses 62 and 63 are formed in substrates 60 and 61, respectively, and metal pads 64 and 65 are formed in recessed 62 and 63 respectively. The planar surfaces are suitable for chemical bonding as described previously. The metal or combination of metals making up pads 64 and 65 can reflow at low temperatures. Examples of such a metal is indium that reflows at a melting temperature of 160 degrees C., and such a combination of metals is 96.5% tin and 3.5% silver that reflows at a eutectic melting temperature of 220 degrees C.
[0095] After the surfaces in FIG. 6A are prepared for direct chemical bonding and the surfaces are placed together, a chemical bond is formed between the planar surfaces. Compared to embodiments 1 and 2, there is no gap near the metal contacts because the contacts are recessed, although a reliable electrical interconnection is not yet made.
[0096] After the chemical bond in FIG. 6B has been formed, a void 66 is formed by partially metal-filled recesses from both wafers. This void does not impede the wafer surfaces from coming together and forming a chemical bond like the metal contacts do in the first and second embodiments. A maximum bond area is thus realized that maximizes the bond energy. After this high bond energy chemical bond has been formed, a low temperature reflow anneal reflows the metal in the recesses resulting in wetting of the metal from the opposing wafers together and resulting in an interconnected metal structure with high reliability. Portions 67 are formed by the reflow to connect pads 64 and 65. This reflow is assisted with a combination of capillary action for recesses with high aspect ratios and gravity as, for example, if the wafers are rotated during the anneal.
[0097] In a fifth embodiment, similar to the fourth embodiment, one of the surfaces in FIG. 6A has the metal recesses replaced with metal plateaus, such that the height of the metal plateau above the planar surface on one wafers is less than the depth of the metal recess below the planar surface on the other wafers as shown in FIG. 7A . Substrates 70 and 71 have respective metal pads 72 and 73. Pads 72 are formed in recesses 74. In this case, the metal surfaces do not, in general, touch after the planar surfaces forming a chemical bond are placed in contact as shown in FIG. 7B . The surfaces of substrates 70 and 71 are prepared for direct chemical bonding and the surfaces are placed together as in the above example, and a chemical bond is formed between the planar surfaces (FIG. 7B ). After reflow, the metal on the two different wafers is wetted together, forming portions 75, in a manner similar to FIG. 6C , resulting in FIG. 7C .
[0098] Hence, the present invention offers numerous advantages and distinctions from prior low temperature wafer bonding techniques. The metal to metal direct bonding of the present invention is spontaneous and requires no external forces at room temperature. The pressure applied on the metal posts that is required for metal-to-metal bonding is generated by bonding process itself, and not external forces. The metal-to-metal direct bonding of the present invention is performed under ambient conditions and the following are realized: wafer level or die size bonds, strong metallic Au—Au, Cu—Cu or metal-to-metal bonds formed at room temperature, and strong metallic bond of metals other than Au and Cu can be formed at room temperature by covering the metals with a ˜50 Å Au layer. Thus, simultaneous bonding of metal/metal, oxide/oxide and metal/oxide can be achieved. The metal-to-metal direct bonding of the present invention is compatible with standard VLSI processing and therefore, is a manufacturable technology. The metal to metal direct bonding of the present invention is compatible with bonding of materials covered with silicon oxides, silicon, or silicon nitride.
[0099] Facilitating the metal-to-metal direct bonding of the present invention is the direct bonding of the non-metal regions proximate to the metal bonding pads. As previously discussed, it is the direct bonding in these regions that generates the resultant force on the opposing metal bonding pads. The direct bonding of the non-metallic regions, according to the present invention, covalently bonds in air silicon dioxide or other insulator covered wafers. Other materials can be utilized, for example, fluorinated oxide surface layers that may also be dipped in an ammonia solution prior to bonding. More generically, any material with an open structure surface that can be terminated by OH, NH or FH groups, and porous low k materials when brought into contact at room temperature can form a covalent bond.
[0100] According to the present invention, silicon dioxide formed by any method such as deposition, thermally or chemically oxidation, and spin-on glass, can be used in pure or doped states.
[0101] Applications of the present invention include but are not limited to vertical integration of processed integrated circuits for 3-D SOC, micro-pad packaging, low-cost and high-performance replacement of flip chip bonding, wafer scale packaging, thermal management and unique device structures such as metal base devices.
[0102] Numerous modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims, the invention may be practiced otherwise than as specifically described herein.
Claims
The invention claimed is:
1. A method of bonding substrates, comprising:
directly contacting a first non-metallic region proximate to a first plurality of metallic pads disposed on a first substrate with a second non-metallic region proximate to a second plurality of metallic pads disposed on a second substrate;
after directly contacting the first and second non-metallic regions, bonding the first non-metallic region to the second non-metallic region without applying external pressure;
forming a contact between a first pad of the first plurality of metallic pads with a second pad of the second plurality of metallic pads and generating pressure between the first and second pads during said bonding the first non-metallic region to the second non-metallic region; and
heating the first and second substrates in a range of about 100-250° C.
2. A method as recited in claim 1, wherein:
at least one of the first and second non-metallic regions comprises a silicon oxide layer.
3. A method as recited in claim 2, comprising:
exposing the silicon oxide layer to one of an argon, nitrogen, and oxygen plasma.
4. A method as recited in claim 1, comprising:
exposing at least one of the first and second non-metallic regions to a plasma process.
5. A method as recited in claim 1, comprising:
exposing at least of one the first and second non-metallic regions to one of an argon, nitrogen, and oxygen plasma.
6. A method as recited in claim 1, comprising:
polishing at least one of the first and second non-metallic regions to a surface roughness less than 15 angstroms.
7. A method as recited in claim 6, comprising:
etching at least one of the first and second non-metallic regions after said polishing.
8. A method as recited in claim 1, wherein:
each of the first and second plurality of metallic pads has a substantially planar upper surface.
9. A method as recited in claim 8, wherein:
said first and second non-metallic regions have substantially planar upper surfaces; and
said substantially planar upper surfaces of the first and second plurality of metallic pads are below said substantially planar upper surfaces of said first and second non-metallic regions.
10. A method as recited in claim 1, comprising:
bonding the first non-metallic region to the second non-metallic region in ambient.
11. A method as recited in claim 1, comprising:
bonding the first non-metallic region to the second non-metallic region at room temperature.
12. A method as recited in claim 1, wherein:
at least one of the first and second non-metallic regions comprises a silicon nitride layer.
13. A bonding method, comprising:
directly contacting a first non-metallic region proximate to a first plurality of metallic pads disposed on a first substrate with a second non-metallic region proximate to a second plurality of metallic pads disposed on a second substrate;
after directly contacting the first and second non-metallic regions, bonding the first non-metallic region to the second non-metallic region; and
forming a contact between a first pad of the first plurality of metallic pads with a second pad of the second plurality of metallic pads;
generating pressure between the first and second pads directly from said bonding the first non-metallic region to the second non-metallic region; and
heating the first and second substrates in a range of about 100-250° C.
14. A method as recited in claim 13, comprising bonding the first non-metallic region to second non-metallic region without applying external pressure.
15. A method as recited in claim 13, wherein:
at least one of the first and second non-metallic regions comprises a silicon oxide layer.
16. A method as recited in claim 15, comprising:
exposing the silicon oxide layer to one of an argon, nitrogen, and oxygen plasma.
17. A method as recited in claim 13, comprising:
exposing at least one of the first and second non-metallic regions to a plasma process.
18. A method as recited in claim 13, comprising:
exposing at least one of the first and second non-metallic regions to one of an argon, nitrogen, and oxygen plasma.
19. A method as recited in claim 13, comprising:
polishing at least one of the first and second non-metallic regions to a surface roughness less than 15 angstroms.
20. A method as recited in claim 19, comprising:
etching at least one of the first and second non-metallic regions after said polishing.
21. A method as recited in claim 13, wherein:
each of the first and second plurality of metallic pads has a substantially planar upper surface.
22. A method as recited in claim 21, wherein:
said first and second non-metallic regions have substantially planar upper surfaces; and
said substantially planar upper surfaces of the first and second plurality of metallic pads are below said substantially planar upper surfaces of said first and second non-metallic regions.
23. A method as recited in claim 13, comprising:
bonding the first non-metallic region to the second non-metallic region in ambient.
24. A method as recited in claim 13, comprising:
bonding the first non-metallic region to the second non-metallic region at room temperature.
25. A method as recited in claim 13, wherein:
at least one of the first and second non-metallic regions comprises a silicon nitride layer.
Patent Citations (28)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US4818728(A) | 1989-04-01 | Rai et al. | Applicant |
| US4904328(A) | 1990-02-01 | Beecher et al. | Applicant |
| US4939568(A) | 1990-07-01 | Kato et al. | Examiner |
| US5489804(A) | 1996-02-01 | Pasch | Applicant |
| US5734199(A) | 1998-03-01 | Kawakita et al. | Applicant |
| US5753536(A) | 1998-05-01 | Sugiyama et al. | Examiner |
| US6316786(B1) | 2001-11-01 | Mueller et al. | Examiner |
| US6322600(B1) | 2001-11-01 | Brewer et al. | Applicant |
| US6528894(B1) | 2003-03-01 | Akram et al. | Applicant |
| US6552436(B2) | 2003-04-01 | Burnette et al. | Applicant |
| US6555917(B1) | 2003-04-01 | Heo | Applicant |
| US6579744(B1) | 2003-06-01 | Jiang | Applicant |
| US6589813(B1) | 2003-07-01 | Park | Applicant |
| US6660564(B2) | 2003-12-01 | Brady | Applicant |
| US6828686(B2) | 2004-12-01 | Park | Applicant |
| US6909194(B2) | 2005-06-01 | Farnworth et al. | Applicant |
| US7109063(B2) | 2006-09-01 | Jiang | Applicant |
| US2002/0003307(A1) | 2002-01-01 | Suga | Applicant |
| US2002/0074670(A1) | 2002-06-01 | Suga | Examiner |
| US2002/0113241(A1) | 2002-08-01 | Kubota et al. | Applicant |
| US2002/0173120(A1) | 2002-11-01 | Enquist | Applicant |
| US2003/0092220(A1) | 2003-05-01 | Akram | Applicant |
| US2003/0157748(A1) | 2003-08-01 | Kim et al. | Applicant |
| EP465227(A2) | 1992-01-01 | Applicant | |
| JP2000-299379 | 2000-10-01 | Applicant | |
| JP2002-26123 | 2002-01-01 | Applicant | |
| TW476145 | 2002-02-01 | Applicant | |
| WO3/054954(A2) | 2003-07-01 | Applicant |
Non-Patent Literature (19)
- Tadaotomo Suga and Kanji Otsuka, Bump-less Interconnect for Next Generation System Packaging, The University of Tokyo, Research Center for Science and Technology, Tokyo, Japan, 2001 Electronic Components and Technology Conference, pp. 1-6.Applicant
- T. Suga, Feasibility of Surface Activated Bonding for Ultra-fine Pitch Interconnection—A New Concept of Bump-less Direct Bonding for System Level Packaging, The University of Tokyo, Research Center for Science and Technology, 2000 Electronics Components and Technology Conference, pp. 702-705.Applicant
- Akitsu Shigetou, Naoe Hosoda, Toshihiro Itoh and Tadatomo Suga, Room-Temperature Direct Bonding of CMP-Cu for Bumpless Interconnection, Research Center for Advanced Science and Technology, University of Tokyo, 2001 Electronic Components and Technology Conference, pp. 1-6.Applicant
- A. Shigetou, T. Itoh, M. Matsuo, N. Hayasaka, K. Okumura and T. Suga, Cu-Cu Direct Bonding for Bump-Less Interconnect, Research Center for Advanced Science and Technolog, University of Tokyo, Optoelectronic Packaging and Solder Bumps, pp. 628-639.Applicant
- Wikipedia, “Chemical bond”, <URL http://en.wikipedia.org/wiki/chemical—bond, Accessed on Mar. 31, 2010, 10 pages.Applicant
- Wikipedia, “Van der Waals force”, <URL http://en.wikipedia.org/wiki/Van-der-Waals-force>, Accessed Mar. 31, 2010, 4 pages.Applicant
- Qin-Yi Tong, et al., “Low Temperature Wafer Direct Bonding”, Journal of Microelectromechanical Systems, IEEE Service Center, Piscataway, NJ, vol. 3, No. 1, Mar. 1, 1994, pp. 29-35, XP-000885425, ISSN 1057-7157.Applicant
- Japanese Office Action issued Feb. 8, 2011, in Patent Application No. 2006-502988 (submitting English translation only).Applicant
- Korean Office Action issued Nov. 9, 2011, in Patent Application No. 10-2005-7014526. (with English Translation).Applicant
- Japanese Office Action issued Oct. 11, 2011, in Patent Application No. 2006-502988 (English-language translation only).Applicant
- Japanese Office Action, mailed May 8, 2012 in Japanese Patent Application No. 2006-502988.Applicant
- Canadian Office Action, mailed May 16, 2012 for application No. 2,515,375, with international preliminary report.Applicant
- Office Action issued Nov. 10, 2010, in Korean Patent Application No. 10-2005-7014526 (Submitting English translation only).Applicant
- Korean Office Action, mailed Apr. 13, 2012 (with English Translation).Applicant
- Korean Office Action mailed Jul. 11, 2012 for Korean Patent Application No. 10-2012-7003621.Applicant
- Japanese Office Action mailed Jan. 8, 2013 for Japanese Patent Application No. 2006-502988 (English translation).Applicant
- Takemitsu Kunio, “Three Dimensional IC Technology, Using Cubic Method,” Journal of the JWS, Japan Welding Society, Apr. 5, 1994, vol. 63, No. 3 pp. 185-189.Applicant
- Shigetou, A.; Hosoda, N.; Itoh, t.; Suga, T., Room-temperature direct bonding of CMP-Cu film for bumpless interconnection, Electronic Components and Technology Conference, 2001. Proceedings., 51th , U.S.A., IEEE, 2001, pp. 755-760.Applicant
- A. Fan, A. Rahman, and R. Reif, Copper Water Bonding, Electrochem. Solid-State Lett, U.S.A. The Electrochemical Society, Aug. 6, 1999, vol. 2, No. 10, pp. 534-536.Applicant