US 8,513,661 B2Grant
Thin film transistor having specified transmittance to light
Issue Date:2013-08-20
•8 Claims
•11 Drawing Sheets
Abstract
A first gate electrode (2) is formed on a substrate (1); a first gate insulating layer (3) is formed so as to cover the first gate electrode (2); a semiconductor layer (4) including an oxide semiconductor is formed on the first gate insulating layer (3); a second gate insulating layer (7) is formed on the semiconductor layer (4); a second gate electrode (8) having a thickness equal to or larger than a thickness of the first gate electrode (2) is formed on the second gate insulating layer (7); and a drain electrode (6) and a source electrode (5) are formed so as to be connected to the semiconductor layer (4).
Metadata
Assignee
- Canon Kabushiki Kaisha
Inventors
- Kenji Takahashi
- Ryo Hayashi
Application Information
Application Number:US 12/743,082
Filing Date:2009-01-20
Priority Date:2008-01-23
Art Unit:2814
Classifications
IPC:
H01L29/10
Patent Drawings (11 sheets)
Description
TECHNICAL FIELD
[0001] The present invention relates to a thin film transistor and a method of producing the same. More particularly, the present invention relates to a double-gate thin film transistor and a method of producing the same.
BACKGROUND ART
[0002] A thin film transistor is a kind of a field-effect transistor and is mainly applied to an active matrix liquid crystal display and an active matrix organic EL display.
[0003] At present the mainstream of the thin film transistor is a polysilicon thin film transistor in which polycrystalline silicon is used for a semiconductor layer and an amorphous silicon thin film transistor in which amorphous silicon is used for a semiconductor layer.
[0004] With regard to the polysilicon thin film transistor in which the mobility of electrons is several hundred times greater than that of the amorphous silicon thin film transistor, not only a technology for a type formed at high temperatures but also a technology for a type formed at low temperatures has been completed, and the increase in size thereof which has been difficult is now expected to be realized.
[0005] On the other hand, the amorphous silicon thin film transistor can be produced in a large area and at low temperatures (300 to 400° C.) and has therefore become a mainstream of the thin film transistor and is utilized in various fields.
[0006] In recent years, as a new kind of a thin film transistor, a thin film transistor in which a transparent oxide polycrystalline thin film mainly formed of ZnO is used for a semiconductor layer is actively developed (Japanese Patent Application Laid-Open No. 2002-076356).
[0007] Since the above-mentioned thin film can be formed at low temperatures and is transparent with respect to visible light, a flexible transparent thin film transistor can be formed on a substrate such as a plastic plate or a film.
[0008] K. Nomura et al., Nature, Vol. 432 (2004-11), pp. 488-492 discloses a technology of using a transparent amorphous oxide semiconductor formed of indium, gallium, zinc, and oxygen for a semiconductor layer of a thin film transistor. Furthermore, it also describes that a flexible transparent thin film transistor having a large mobility can be formed on a substrate such as a polyethylene terephthalate (PET) film at room temperature.
[0009] One problem which arises when a thin film transistor is produced and used is the so-called “hump” which appears in drain current (Ids)—gate voltage (Vgs) characteristics (transfer characteristics). FIG. 1B illustrates typical transfer characteristics of a thin film transistor in which a hump is observed.
[0010] The occurrence of the hump makes conspicuous such malfunctions that a threshold value which is necessary for operating a circuit cannot be obtained or an operating point of the circuit is shifted.
[0011] For example, a driving thin film transistor in a pixel circuit of an active matrix drive organic EL display controls the emission intensity of an organic EL device by a current which flows between a drain and a source thereof. Therefore, if a hump is formed, a malfunction occurs in which a desired emission intensity cannot be obtained.
[0012] Japanese Patent Application Laid-Open Nos. 2003-197915 and 2007-200930 disclose a mechanism of forming a hump in a polysilicon thin film transistor.
[0013] More specifically, in a polysilicon thin film transistor, when there is a mesa isolation structure, a sub-channel transistor is formed in a semiconductor layer region which overlaps a gate electrode. In the sub-channel transistor, a current path is formed at a pattern edge or vicinity of a semiconductor film. The term “mesa isolation structure” herein employed refers to an isolation structure thorough mesa isolation.
[0014] In a thin film transistor having a mesa isolation structure, because an electric field concentrates on a side wall portion of a semiconductor film, the side wall portion acts as a sub-channel which is not designed, and current begins to flow through the sub-channel at a lower voltage than through a channel of the thin film transistor (becomes ON state).
[0015] Therefore, in the transfer characteristics of the TFT, abnormal current characteristics (hump) appear because the sub-channel transistor is turned on (also called “parasitic characteristics”).
[0016] In order to solve this problem, in Japanese Patent Application Laid-Open No. 2003-197915, by preventing pattern edges from overlapping each other in a channel region of a semiconductor film, formation of a hump in the transfer characteristics is suppressed.
[0017] Furthermore, in Japanese Patent Application Laid-Open No. 2007-200930, by providing a thick side wall protection film on a pattern edge of a semiconductor film to thereby effectively reduce the intensity of an electric field applied to a sub-channel transistor, formation of a hump in the transfer characteristics is suppressed.
[0018] However, in the case of the above-mentioned thin film transistor in which an oxide semiconductor is used for a semiconductor layer, the mechanism of operation of the transistor is different from that of a polysilicon thin film transistor.
[0019] T. Miyasato et al., Applied Physics Letters, 86 (2005), p. 162902 discloses that a thin film transistor in which an oxide semiconductor is used for a semiconductor layer becomes OFF state by the phenomenon that a channel portion of a semiconductor film is completely depleted by application of an electric field. In other words, as the electric field is more intensely applied, the OFF state is maintained more stably.
[0020] Therefore, in the case of a thin film transistor in which an oxide semiconductor is used for a semiconductor layer, it is considered that there exists another factor for formation of a hump in the transfer characteristics than the sub-channel transistor present at pattern edges of the semiconductor film.
[0021] In the light of T. Miyasato et al., Applied Physics Letters, 86 (2005), p. 162902, there is a high probability that a hump in the transfer characteristics of a thin film transistor in which an oxide semiconductor is used for a semiconductor layer is formed due to the following factor. That is, it is considered that an interface region (back gate interface) of a semiconductor film which is opposite to an interface being in contact with a gate insulating film is different in film quality from the inside of the semiconductor film, a current path is formed.
[0022] The problem associated with a hump resulting from the back gate interface is not disclosed in Japanese Patent Application Laid-Open Nos. 2003-197915 and 2007-200930.
[0023] Meanwhile, for the purpose of preventing degradation of a thin film transistor during a device production step after formation of the thin film transistor, a protective layer is generally provided. However, particularly in a bottom gate thin film transistor, because there is only the protective layer on the semiconductor layer, if the protective layer does not function sufficiently, the back gate interface may be modified to cause a hump in the transfer characteristics.
DISCLOSURE OF THE INVENTION
[0024] Accordingly, the present invention has been accomplished in view of the above problems, and it is, therefore, an object of the present invention to provide a thin film transistor which suppresses the occurrence of a hump in the transfer characteristics of the thin film transistor in which an oxide semiconductor is used for a semiconductor layer, and a method of producing the same.
[0025] According to the present invention, in order to solve the above-mentioned problem, there is provided a thin film transistor including:
[0026] a substrate;
[0027] a first gate electrode formed on the substrate;
[0028] a first gate insulating layer formed so as to cover the first gate electrode;
[0029] a semiconductor layer including an oxide semiconductor and formed on the first gate insulating layer;
[0030] a second gate insulating layer formed on the semiconductor layer;
[0031] a second gate electrode formed on the second gate insulating layer; and
[0032] a drain electrode and a source electrode formed so as to be connected to the semiconductor layer,
[0033] wherein the second gate electrode has a thickness larger than a thickness of the first gate electrode.
[0034] According to the present invention, occurrence of a hump in the transfer characteristics of a thin film transistor in which an oxide semiconductor is used for a semiconductor layer can be suppressed.
[0035] Further, according to the present invention, a thin film transistor which can suppress occurrence of a hump in the transfer characteristics of the thin film transistor in which an oxide semiconductor is used for a semiconductor layer can be produced.
[0036] Further features of the present invention will become apparent from the following description of exemplary embodiments with reference to the attached drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0037] FIGS. 1A and 1B are graphical representations showing transfer characteristics of a thin film transistor.
[0038] FIG. 2 is a flow chart illustrating production steps of a thin film transistor according to an embodiment of the present invention.
[0039] FIGS. 3A , 3B, 3C and 3D are cross-sectional views illustrating the production steps of the thin film transistor according to the embodiment of the present invention.
[0040] FIGS. 4A , 4B and 4C are cross-sectional views illustrating the production steps of the thin film transistor according to the embodiment of the present invention.
[0041] FIG. 5 is a cross-sectional view illustrating the thin film transistor according to the embodiment of the present invention.
[0042] FIGS. 6A , 6B, 6C, 6D and 6E are cross-sectional views illustrating production steps of a thin film transistor according to Example 1 of the present invention.
[0043] FIG. 7 is a cross-sectional view illustrating the configuration of the thin film transistor according to Example 1 of the present invention.
[0044] FIGS. 8A , 8B, 8C and 8D are cross-sectional views illustrating production steps of a thin film transistor according to Example 2 of the present invention.
[0045] FIGS. 9A , 9B, 9C and 9D are cross-sectional views illustrating the production steps of the thin film transistor according to Example 2 of the present invention.
[0046] FIG. 10 is a cross-sectional view illustrating the configuration of the thin film transistor according to Example 2 of the present invention.
BEST MODE FOR CARRYING OUT THE INVENTION
[0047] Best mode for carrying out the present invention is described below with reference to the accompanying drawings.
[0048] Incidentally, the term “oxide semiconductor” as herein employed refers to an oxide semiconductor which changes, when used in a thin film transistor as an active layer, a drain current by at least two orders of magnitude.
[0049] A method of producing a thin film transistor includes eight steps as illustrated in a flow chart of FIG. 2 . FIGS. 3A , 3B, 3C, 3D, 4A, 4B and 4C are cross-sectional views illustrating the production steps of a thin film transistor according to an embodiment of the present invention. Although a planar thin film transistor is illustrated as the thin film transistor in FIGS. 3A , 3B, 3C, 3D, 4A, 4B and 4C, the configuration of the thin film transistor is not limited thereto.
[0050] As illustrated in FIG. 5 , the thin film transistor has a structure in which a first gate electrode 2, a first gate insulating layer 3, a semiconductor layer 4, a second gate insulating layer 7, a second gate electrode 8, and contact electrodes 9 are stacked in the mentioned order on a substrate 1.
[0051] The substrate 1 is an insulating substrate. For example, the substrate 1 may be a glass substrate. Furthermore, by using an organic material or a polymer material such as polyethylene terephthalate (PET) as the substrate 1, a thin film transistor can be produced on a flexible substrate.
[0052] The contact electrodes 9 are provided for the purpose of connecting the semiconductor layer 4 and a drain electrode 5 or a source electrode 6 described later.
[0053] First, as a first step, a first conductive film is deposited on the substrate 1. A film containing at least one kind of metal is used as the first conductive film. Alternatively or additionally, a conductive metal oxide (MOx wherein M represents a metal element) may be used.
[0054] The first conductive film may have either a single layer structure or a stack structure consisting of a plurality of layers. As the process of forming the first conductive film, a vapor phase process such as sputtering, pulse laser evaporation, or electron beam evaporation is desirably used. However, the film formation process is not limited to those processes. Then, the first conductive film is patterned to form the first gate electrode 2. A structure formed by the process up to and including this step is illustrated in FIG. 3A .
[0055] Next, as a second step, a first insulator film is deposited on the first gate electrode 2. The first insulator film is formed of an inorganic material selected from the group consisting of oxide, carbide, nitride, fluoride, and a compound thereof. For example, a metal oxide film containing at least one kind of metal element is used as the first insulator film. Among the metal oxides, it is more desirable to use as the insulator film a metal oxide containing at least one of SiO2, Al2O3, Ga2O3, In2O3, MgO, CaO, SrO, BaG, ZnO, Nb2O5, Ta2O5, TiO2, ZrO2, HfO2, CeO2, Li2O, Na2O, K2O, Rb2O, Sc2O3, Y2O3, La2O3, Nd2O3, Sm2O3, Gd2O3, Dy2O3, Er2O3 and Yb2O3. Alternatively or additionally, a metal nitride (MNx wherein M represents a metal element) may be used.
[0056] Furthermore, alternatively or additionally, a metal oxynitride (MOxNy wherein M represents a metal element) may be used.
[0057] As the process of forming the first insulator film, a vapor phase process such as chemical vapor deposition, sputtering, pulse laser evaporation, or electron beam evaporation is desirably used. However, the film formation process is not limited to those processes.
[0058] By patterning the first insulator film, the first gate insulating layer 3 is formed. A structure formed by the process up to and including this step is illustrated in FIG. 3B .
[0059] Then, as a third step, a semiconductor film is deposited on the first gate insulating layer 3. Specific examples of a preferable semiconductor film which can be adopted in the present invention include:
[0060] an oxide including ZnO as a main component;
[0061] an oxide including In2O3 as a main component;
[0062] an oxide including Ga2O3 as a main component;
[0063] an oxide including Sn2O3 as a main component; and
[0064] an oxide including a composite oxide including two or more of the above-mentioned oxides as a main component.
[0065] Incidentally, the term “main component” herein employed refers to an oxide having the highest content of those oxides contained in the oxide semiconductor concerned.
[0066] Furthermore, the term “oxide semiconductor” herein employed refers to an oxide semiconductor which changes, when used in a thin film transistor as an active layer, a drain current by at least two orders of magnitude.
[0067] In particular, an oxide containing In2O3 and ZnO the molar ratio of the sum of which is ½ or more of the whole is preferable.
[0068] Alternatively or additionally, the semiconductor film may contain an oxide semiconductor such as SnO2 or TiOx, or a semiconductor film containing another oxide semiconductor may also be used.
[0069] As the process of forming the semiconductor film, a vapor phase process such as sputtering, pulse laser evaporation, or electron beam evaporation is desirably used. However, the film formation process is not limited to those processes.
[0070] Then, by patterning the semiconductor film, the semiconductor layer 4 is formed. A structure formed by the process up to and including this step is illustrated in FIG. 3C .
[0071] Next, as a fourth step, a second insulator film is deposited on the semiconductor layer 4. The second insulator film is formed of an inorganic material selected from the group consisting of oxide, carbide, nitride, fluoride, and a compound thereof. For example, a metal oxide film containing at least one kind of metal element is used as the second insulator film.
[0072] Of the metal oxides, it is more desirable to use as the second insulator film a metal oxide containing at least one of SiO2, Al2O3, Ga2O3, In2O3, MgO, CaO, SrO, BaO, ZnO, Nb2O5, Ta2O5, TiO2, ZrO2, HfO2, CeO2, Li2O, Na2O, K2O, Rb2O, Sc2O3, Y2O3, La2O3, Nd2O3, Sm2O3, Gd2O3, Dy2O3, Er2O3 and Yb2O3. Alternatively or additionally, a metal nitride (MNx wherein M represents a metal element) may be used.
[0073] Further, alternatively or additionally, a metal oxynitride (MOxNy wherein M represents a metal element) may be used.
[0074] As the process of forming the second insulator film, a vapor phase process such as chemical vapor deposition, sputtering, pulse laser evaporation, or electron beam evaporation is desirably used. However, the film formation process is not limited to those processes. Through the above-mentioned steps, a structure illustrated in FIG. 3D is completed.
[0075] Then, as a fifth step, a transparent conductive film is deposited on the second insulator film. It is preferable that ITO which is a solid solution of In2O3 and SnO2 be used as the transparent conductive film. It is also preferable that an oxide material containing at least one of In, Sn and Zn be used as the transparent conductive film.
[0076] As the process of forming the transparent conductive film, a vapor phase process such as sputtering, pulse laser evaporation, or electron beam evaporation is desirably used. However, the film formation process is not limited to those processes. Through the above-mentioned steps, a structure illustrated in FIG. 4A is completed.
[0077] Then, as a sixth step, by patterning the transparent conductive film, the second gate electrode 8 is formed. Through the above-mentioned steps, a structure illustrated in FIG. 4B is completed.
[0078] Next, as a seventh step, by patterning the second insulator film, the second gate insulating layer 7 is formed. A structure formed by the process up to and including this step is illustrated in FIG. 4C .
[0079] Next, as an eight step, a second conductive film is deposited on the second gate insulating layer 7 and the second gate electrode 8. A film containing at least one kind of metal is used as the second conductive film. Alternatively or additionally, a conductive metal oxide (MOx wherein M represents a metal element) may be used.
[0080] The second conductive film may have either a single layer structure or a stack structure consisting of a plurality of layers. As the process of forming the second conductive film, a vapor phase process such as sputtering, pulse laser evaporation, or electron beam evaporation is desirably used. However, the film formation process is not limited to those processes.
[0081] Then, by patterning the second conductive film, the contact electrodes 9 are formed. A structure formed by the process up to and including this step is illustrated in FIG. 5 .
[0082] In the above, an example of the production steps of the thin film transistor according to the present invention is described.
[0083] In the production steps described above, the film thickness of the first gate electrode has an upper limit in order to form various kinds of layers thereon with good step coverage. The upper limit is the maximum film thickness with which the step coverage is satisfactory and does not adversely affect the TFT characteristics.
[0084] According to the findings of the present inventors, the film thickness of the first gate electrode may be approximately similar to the film thickness of the gate insulating film.
[0085] Incidentally, the term “step coverage” herein employed refers to such characteristics that when a coating film is formed on a substrate or the like having a step (or step difference) (for example, a substrate having a gate electrode thereon as a step), continuous coating can be attained without interruption at the step portion.
[0086] Furthermore, the term “good step coverage” herein employed refers to, for example, a state in which when a gate electrode of a TFT is covered with an insulating layer, the insulation property is not lowered and the TFT characteristics are not degraded, and also refers to a state in which when an underlayer having a step is covered with a semiconductor layer, the TFT characteristics are not degraded.
[0087] Moreover, in a case where a first gate electrode is formed so as to also serve as wiring, in order to make the voltage drop fall within an allowable value range, the film thickness has a lower limit. The lower limit is the minimum film thickness with which the voltage drop does not adversely affect the TFT characteristics.
[0088] According to the findings by the present inventors, the lower limit of the film thickness is the order of 10 nm or so. The film thickness of the first gate electrode is determined to be between the upper limit and the lower limit. On the other hand, with regard to the second gate electrode, because only a protective layer is formed thereon, the upper limit of the film thickness of the second gate electrode may be larger than that of the first gate electrode. The second gate electrode also functions as a protective layer for protecting the semiconductor layer, and as the film thickness is larger, the effect thereof is greater.
[0089] Therefore, making the thickness of the second gate electrode equal to or larger than that of the first gate electrode is effective in operating the thin film transistor stably.
[0090] In T. Miyasato et al., Applied Physics Letters, 86 (2005), p. 162902, an ITO film which is used generally as a conductive film is completely depleted by using a ferroelectric BLT gate insulating layer to thereby realize OFF state of a thin film transistor.
[0091] However, in the technology disclosed in T. Miyasato et al., Applied Physics Letters, 86 (2005), p. 162902, because the step of forming the BLT gate insulating layer requires heat treatment at a temperature as high as 750° C., a low-cost material such as glass or plastic can not be used as the substrate.
[0092] On the other hand, in the method of producing a thin film transistor according to the present invention, because all the steps can be carried out at room temperature, a low-cost material such as glass or plastic can be used as the substrate.
[0093] Furthermore, because the thin film transistor according to the present invention has a double-gate structure, an effectively high electric field can be applied to the semiconductor layer. Therefore, similarly to the case disclosed in T. Miyasato et al., Applied Physics Letters, 86 (2005), p. 162902, a semiconductor layer having a reduced resistance can be depleted, whereby transistor operation can be attained.
[0094] Furthermore, in the sixth step, for example, by performing back side light exposure with the first gate electrode 2 being used as a photomask, the transparent conductive film can be patterned. At that time, it is necessary to expose a resist film formed on a surface of a sample to light via a stack film. Therefore, in order to expose the resist film to light in the patterning in the first to the fifth steps, the transmittance to light having a wavelength of 365 nm or more used in an exposure device is set to 50% or more, and more preferably 80% or more.
[0095] Moreover, by making the material of the second gate electrode and the material of the contact electrodes identical to each other, the sixth step and the eighth step can be carried out at the same time.
[0096] In addition, by making at least one of the first gate electrode and the second gate electrode shield light having a specific wavelength, the electrode can be provided with a function as a light-shielding layer. The term “light having a specific wavelength” as herein employed refers to light having a wavelength of 365 nm or more used in an exposure device.
[0097] Furthermore, in the method of producing a thin film transistor, it is also possible to lower the resistance of the semiconductor layer 4 under the influence of a film forming atmosphere of at least one of the first gate insulating layer 3 and the second gate insulating layer 7 and hydrogen contained in those films. Also in this case, transistor operation can be attained for the above-mentioned reason.
[0098] Moreover, because of the planar structure, parasitic capacitance generated between the gate electrode and the drain electrode can be made minimum and uniform. By making the gate electrode opaque, it is also possible to make the gate electrode function as a light-shielding layer.
[0099] For a double-gate thin film transistor produced in this manner, even if the transfer characteristics of the device have a hump in single-gate driven mode, characteristics free of a hump can be obtained in double-gate driven mode. FIG. 1A shows typical transfer characteristics of a thin film transistor free of a hump, while FIG. 1B shows typical transfer characteristics of a thin film transistor having a hump.
[0100] Incidentally, the term “single-gate driving” as herein employed refers to a driving method in which one of the gate electrodes is driven with the other of the gate electrodes being grounded.
EXAMPLES
[0101] The present invention is now described in further detail below with reference to Examples. It is to be noted that the present invention is by no means limited to the examples.
Example 1
[0102] FIG. 7 is a cross-sectional view illustrating the configuration of a thin film transistor according to Example 1 of the present invention. As illustrated in FIG. 7 , this example is a bottom-contact type double-gate thin film transistor. The thin film transistor illustrated in FIG. 7 is formed on a substrate 1.
[0103] More specifically, a first gate electrode 2, a first gate insulating layer 3, a drain electrode 5, a source electrode 6, a semiconductor layer 4, a second gate insulating layer 7, and a second gate electrode 8 are formed on the substrate 1.
[0104] A glass substrate (No. 1737 manufactured by Corning Incorporated) is used as the substrate 1. The thickness of the glass substrate is 0.5 mm.
[0105] A Mo thin film is formed on the substrate 1 in the thickness of 50 nm. In this example, DC magnetron sputtering using an atmosphere of an argon gas is used to form the MO thin film.
[0106] Then, the deposited Mo thin film is finely processed by photolithography and dry etching to form the first gate electrode 2 (FIG. 6A ).
[0107] Then, an SiO2 thin film is formed on the first gate electrode 2 in a thickness of 200 nm by RF magnetron sputtering.
[0108] With respect to the film formation conditions, the substrate temperature is set to room temperature, the input RF power is set to 400 W, the supply flow rate of argon gas is set to 10 sccm, and the chamber pressure is set to 0.1 Pa.
[0109] The deposited SiO2 thin film is patterned by photolithography and wet etching using a buffered hydrofluoric acid solution to form the first gate insulating layer 3 (FIG. 6B ).
[0110] Then, an ITO thin film is formed on the first gate insulating layer 3 in a thickness of 100 nm by DC magnetron sputtering.
[0111] With respect to the film formation conditions, the substrate temperature is set to room temperature, the input RF power is set to 200 W, the supply flow rate of argon gas is set to 100 sccm, and the chamber pressure is set to 0.2 Pa. The ITO thin film produced in this manner is amorphous.
[0112] Then, the deposited ITO thin film is finely processed by photolithography and wet etching.
[0113] Then, the finely-processed ITO thin film is converted into a polycrystalline ITO thin film by heat treatment at 270° C. for 20 minutes, whereby the drain electrode 5 and the source electrode 6 are formed (FIG. 6C ).
[0114] Then, on the first gate insulating layer 3, the drain electrode 5, and the source electrode 6a, a thin film of an oxide semiconductor In—Ga—Zn—O is formed in a thickness of 40 nm by RF magnetron sputtering.
[0115] With respect to the film forming conditions, the substrate temperature is set to room temperature, the input RF power is set to 200 W, the supply flow rate of argon gas containing 5% of oxygen is set to 25 sccm, and the chamber pressure is set to 0.5 Pa. The In—Ga—Zn—O thin film produced in this manner is amorphous, and the compositional ratio of In:Ga:Zn:O is approximately 1:1:1:4.
[0116] Then, the deposited In—Ga—Zn—O thin film is patterned by photolithography and wet etching using hydrochloric acid to form the semiconductor layer 4 (FIG. 6D ).
[0117] Then, on the semiconductor layer 4, an SiO2 thin film is formed in a thickness of 200 nm by RF magnetron sputtering.
[0118] With respect to the film formation conditions, the substrate temperature is set to room temperature, the input RF power is set to 400 W, the supply flow rate of argon gas is set to 10 sccm, and the chamber pressure is set to 0.1 Pa.
[0119] The thus deposited SiO2 thin film is patterned by photolithography and wet etching using a buffered hydrofluoric acid solution to form the second gate insulating layer 7 (FIG. 6E ).
[0120] Then, on the second gate insulating layer 7, an Mo thin film is formed in a thickness of 100 nm. The film formation conditions are the same as those for the first gate electrode 2.
[0121] Then, the thus deposited Mo thin film is finely processed by photolithography and dry etching to form the second gate electrode 8 (FIG. 7 ).
[0122] The bottom-contact type double-gate thin film transistor produced as described above exhibits the transfer characteristics free of a hump as shown in FIG. 1A when driven with the same potential being applied to the first gate electrode 2 and the second gate electrode 8.
[0123] Further, because the first gate electrode 2 and the second gate electrode 8 are made of the metal and shield light, they also function as light-shielding layers.
[0124] As described above, in the thin film transistor of this example, occurrence of a hump in the transfer characteristics is suppressed and the effect of shielding light to be incident on the semiconductor layer is realized.
Comparative Example
[0125] When the thin film transistor produced in Example 1 was operated in single-gate driven mode with the second gate electrode 8 being grounded and a voltage being applied to the first gate electrode 2, a hump was observed in the transfer characteristics as shown in FIG. 1B .
[0126] It can be seen from the comparison as described above that double-gate driving can suppress occurrence of a hump in the transfer characteristics.
Example 2
[0127] FIG. 10 is a cross-sectional view illustrating the configuration of a thin film transistor according to Example 2 of the present invention. This example is an example of forming a planar double-gate thin film transistor. The thin film transistor illustrated in FIG. 10 is formed on a substrate 1.
[0128] More specifically, on the substrate 1, there are formed a first gate electrode 2, a first gate insulating layer 3, a semiconductor layer 4, a drain electrode 5, a source electrode 6, a second gate insulating layer 7, a second gate electrode 8, contact electrodes 9, and a protective layer 10.
[0129] A glass substrate (No. 1737 produced by Corning Incorporated) is used as the substrate 1. The thickness of the glass substrate is 0.5 mm.
[0130] First, a Mo thin film is formed on the substrate 1 in a thickness of 50 nm. In this example, DC magnetron sputtering using an atmosphere of argon gas is used to form the Mo thin film.
[0131] Then, the deposited Mo thin film is finely processed by photolithography and dry etching to form the first gate electrode 2 (FIG. 8A ).
[0132] Then, an SiO2 thin film is formed on the first gate electrode 2 in a thickness of 200 nm by RF magnetron sputtering.
[0133] With respect to film formation conditions, the substrate temperature is set to room temperature, the input RF power is set to 400 W, the supply flow rate of argon gas is set to 10 sccm, and the chamber pressure is set to 0.1 Pa.
[0134] The thus deposited SiO2 thin film is patterned by photolithography and wet etching using a buffered hydrofluoric acid solution to form the first gate insulating layer 3 (FIG. 8B ).
[0135] Then, a thin film of an oxide semiconductor In—Ga—Zn—O is formed on the first gate insulating layer 3 in a thickness of 40 nm by RF magnetron sputtering.
[0136] With respect to the film formation conditions, the substrate temperature is set to room temperature, the input RF power is set to 200 W, the supply flow rate of argon gas containing 5% of oxygen is set to 25 sccm, and the chamber pressure is set to 0.5 Pa. The In—Ga—Zn—O thin film produced in this manner is amorphous, and the compositional ratio of In:Ga:Zn:O is approximately 1:1:1:4.
[0137] The deposited In—Ga—Zn—O thin film is patterned by photolithography and wet etching using hydrochloric acid to form the semiconductor layer 4 (FIG. 8C ).
[0138] Then, an SiO2 thin film is formed on the semiconductor layer 4 in a thickness of 300 nm by RF magnetron sputtering. With respect to the film formation conditions, the substrate temperature is set to room temperature, the input RF power is set to 400 W, the supply flow rate of argon gas is set to 10 sccm, and the chamber pressure is set to 0.1 Pa (FIG. 8D ).
[0139] Then, an ITO thin film is formed on the SiO2 thin film in a thickness of 100 nm by DC magnetron sputtering. With respect to the film formation conditions, the substrate temperature is set to room temperature, the input RF power is set to 200 W, the supply flow rate of argon gas is set to 100 sccm, and the chamber pressure is set to 0.2 Pa. The ITO thin film produced in this manner is amorphous (FIG. 9A )
[0140] Then, a resist is patterned by back side light exposure with the first gate electrode 2 being used as a photomask, and the ITO thin film is patterned by wet etching to form the second gate electrode 8. Then, the SiO2 thin film is patterned by dry etching to form the second gate insulating layer 7.
[0141] After that, the ITO thin film is converted into a polycrystalline ITO thin film by heat treatment at 270° C. for 30 minutes (FIG. 9B ).
[0142] Then, an SiN thin film is formed on the second gate electrode 8 and the semiconductor layer 4 in a thickness of 300 nm by plasma CVD.
[0143] The substrate temperature when the SiN thin film is formed by the plasma CVD is set to 250° C. SiH4, NH3 and N2 are used as the process gases with the gas flow rate ratio being set to SiH4:NH3:N2=1:2.5:25. The input RF power density and the pressure are 0.9 W/cm2 and 150 Pa, respectively.
[0144] Here, the resistance of regions of the semiconductor layer 4 which are in contact with the SiN thin film is greatly lowered under the influence of the film forming atmosphere of the SiN thin film and hydrogen contained in the thin film. Such regions of the semiconductor layer 4 having the lowered resistance are used as the drain electrode 5 and the source electrode 6 (FIG. 9C ).
[0145] Then, the SiN thin film is patterned by photolithography and dry etching to form the protective layer 10 (FIG. 9D ).
[0146] Then, a Mo thin film is formed on the protective layer 10 in a thickness of 100 nm. The film formation conditions are the same as those when the first gate electrode 2 is formed.
[0147] Then, the deposited Mo thin film is finely processed by photolithography and dry etching to form the contact electrodes 9 (FIG. 10 ).
[0148] For the planar double-gate thin film transistor produced in this manner, even if the transfer characteristics of the device have a hump in single-gate driven mode, characteristics free of a hump can be obtained in double-gate driven mode.
[0149] Further, because of the planar structure, a parasitic capacitance generated between the gate electrode and the drain electrode can be made to be minimum and uniform.
[0150] As described above, the thin film transistor and the production method of the same of the examples can realize the effect of suppressing occurrence of a hump in the transfer characteristics, reducing and making uniform the parasitic capacitance by virtue of the planar structure, and reducing the number of production steps and realizing self-alignment by virtue of back side light exposure.
[0151] While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions.
[0152] This application claims the benefit of Japanese Patent Application No. 2008-012593, filed Jan. 23, 2008, which is hereby incorporated by reference herein in its entirety.
Claims
The invention claimed is:
1. A thin film transistor comprising:
a substrate;
a first gate electrode formed on said substrate;
a first gate insulating layer formed so as to cover said first gate electrode;
a semiconductor layer comprising an oxide semiconductor and formed on said first gate insulating layer;
a second gate insulating layer formed on said semiconductor layer;
a second gate electrode formed on said second gate insulating layer; and
a drain electrode and a source electrode formed so as to be connected to said semiconductor layer,
wherein said second gate electrode has a thickness larger than a thickness of said first gate electrode, and
wherein a thickness of said first gate electrode is equal to or smaller than a thickness of said first gate insulating layer, and
wherein said first gate electrode, said first gate insulating layer, said second gate insulating layer, said semiconductor layer, said drain electrode, and said source electrode have a transmittance of 50% or more for light having a wavelength of 365 nm or more.
2. The thin film transistor according to claim 1, wherein at least one of said drain electrode and said source electrode is in contact with said semiconductor layer.
3. The thin film transistor according to claim 1, wherein said semiconductor layer comprises an oxide semiconductor containing at least one element selected from the group consisting of Zn, Ga, In and Sn.
4. The thin film transistor according to claim 1, wherein said semiconductor layer comprises an oxide semiconductor containing In—Ga—Zn—O.
5. A thin film transistor comprising:
a substrate;
a first gate electrode formed on said substrate;
a first gate insulating layer formed so as to cover said first gate electrode;
a semiconductor layer comprising an oxide semiconductor and formed on said first gate insulating layer;
a second gate insulating layer formed on said semiconductor layer;
a second gate electrode formed on said second gate insulating layer; and
a drain electrode and a source electrode formed so as to be connected to said semiconductor layer,
wherein said second gate electrode has a thickness larger than a thickness of said first gate electrode, and
wherein a thickness of said first gate electrode is equal to or smaller than a thickness of said first gate insulating layer,
wherein at least one of said first gate electrode and said second gate electrode has a transmittance of 50% or less for light having a wavelength of 365 nm or more.
6. The thin film transistor according to claim 5, wherein at least one of said drain electrode and said source electrode is in contact with said semiconductor layer.
7. The thin film transistor according to claim 5, wherein said semiconductor layer comprises an oxide semiconductor containing at least one element selected from the group consisting of Zn, Ga, In and Sn.
8. The thin film transistor according to claim 5, wherein said semiconductor layer comprises an oxide semiconductor containing In—Ga—Zn—O.
Patent Citations (33)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US5079606(A) | 1992-01-01 | Yamamura et al. | Applicant |
| US5654573(A) | 1997-08-01 | Oashi et al. | Applicant |
| US5818070(A) | 1998-10-01 | Yamazaki et al. | Examiner |
| US5834797(A) | 1998-11-01 | Yamanaka | Examiner |
| US5923963(A) | 1999-07-01 | Yamanaka | Applicant |
| US6291366(B1) | 2001-09-01 | Sano et al. | Applicant |
| US6909118(B2) | 2005-06-01 | Hara | Applicant |
| US7091524(B2) | 2006-08-01 | Nakayama et al. | Applicant |
| US7145174(B2) | 2006-12-01 | Chiang et al. | Applicant |
| US7189992(B2) | 2007-03-01 | Wager, III et al. | Applicant |
| US7242039(B2) | 2007-07-01 | Hoffman et al. | Applicant |
| US7282782(B2) | 2007-10-01 | Hoffman et al. | Applicant |
| US7297977(B2) | 2007-11-01 | Hoffman et al. | Applicant |
| US7511343(B2) | 2009-03-01 | Li et al. | Examiner |
| US2001/0030323(A1) | 2001-10-01 | Ikeda | Applicant |
| US2003/0049940(A1) | 2003-03-01 | Matsuhashi et al. | Applicant |
| US2004/0197970(A1) | 2004-10-01 | Komatsu | Applicant |
| US2005/0199960(A1) | 2005-09-01 | Hoffman et al. | Examiner |
| US2005/0275038(A1) | 2005-12-01 | Shih et al. | Applicant |
| US2006/0170067(A1) | 2006-08-01 | Maekawa et al. | Examiner |
| US2007/0054507(A1) | 2007-03-01 | Kaji et al. | Applicant |
| US2007/0194379(A1) | 2007-08-01 | Hosono et al. | Applicant |
| US2009/0072232(A1) | 2009-03-01 | Hayashi et al. | Applicant |
| US2010/0044703(A1) | 2010-02-01 | Yabuta et al. | Applicant |
| US2010/0059751(A1) | 2010-03-01 | Takahashi et al. | Applicant |
| JP6-350089(A) | 1994-12-01 | Applicant | |
| JP2002-076356(A) | 2002-03-01 | Applicant | |
| JP2003-197915(A) | 2003-07-01 | Applicant | |
| JP2004-343018 | 2004-12-01 | Applicant | |
| JP2007-150157(A) | 2007-06-01 | Applicant | |
| JP2007-194594(A) | 2007-08-01 | Applicant | |
| JP2007-200930(A) | 2007-08-01 | Applicant | |
| TW491983 | 2002-06-01 | Applicant |
Non-Patent Literature (4)
- K. Nomura et al., “Room-temperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors,” Nature, vol. 432, pp. 488-492, Nov. 25, 2004.Applicant
- T. Miyasako, et al., “Ferroelectric-gate thin-film transistors using indium-tin-oxide channel with large charge controllability”, Applied Physics Letters, vol. 86, pp. 162902-1-162902-3, Apr. 12, 2005.Applicant
- Office Action issued by JPO Nov. 20, 2012, in counterpart Japanese patent application 2008-012593, with translation.Applicant
- Office Action dated Jun. 18, 2012, issued in counterpart Taiwan (R.O.C.) Patent Application No. 098102603, with English-language translation.Applicant