Method for thinning a bonding wafer

[0001] This application claims priority to U.S. provisional application Ser. No. 61/165,898, filed on Apr. 1, 2009, the entire contents of which are herein incorporated by reference.

[0002] The present invention relates to the field of semiconductor manufacturing, and more particularly, to methods for thinning a bonded wafer, for example a wafer containing Through Silicon Vias (TSV).

[0003] As is known, wafers for the semiconductor industry have been bonded together by a bonding layer in a sandwich type relation for various applications. Further, for these applications, the top wafer diameter needs to be reduced while the diameter of the bottom or handling wafer remains unchanged. In cases where the bonding layer does not extend to the outer diameter, the top wafer is thinned down to microns of thickness and the unsupported area beyond the bonding layer becomes problematic. The thinning process tends to chip the unsupported wafer edge and the debris created causes scratching and subsurface damage on the prime surface of the wafer. Furthermore, in the chase of wafer thinning processes that utilize wet etching, exposed areas of the bonding layer may be chemically etched or attacked by the wet etching chemicals, thereby compromising the structural integrity of a device containing the top wafer and possibly lead to a loss of yield. A more extreme example of the damage is that large pieces of the top wafer break off with the bonding layer attached.

[0004] Prior art methods have been used to try to solve the problem stated above. One such method includes photolithography and etch techniques to remove a perimeter of the top wafer. However, this technique is costly and adds long cycle times to the processing. Another solution that has been introduces to solve this problem is to reduce the diameter of the top wafer by using a fixed abrasive grind wheel on a conventional edge grinder. Such applications are currently performed by companies producing SOI wafers (silicon on insulator) and result in a ledge being formed along the periphery of the handling wafer while the diameter of the upper wafer is reduced. However, the side of the top wafer is not protected and mechanical damage can occur during subsequent planarization and thinning of the top wafer and the bonding layer may be damaged. In the case of wet etching processes, a chemical attack on the bonding layer can create mechanical instability of the device and increase the probability of damage. Furthermore, trapped chemical species on the bonded side of the top wafer can diffuse to other areas of the top wafer and degrade or destroy the device.

[0005] Therefore, new wafer thinning methods are needed that prevent chipping of the edges of the top wafer and mask wet etching chemicals from the bonding film during a wafer thinning process.

[0006] A method is provided for thinning a wafer, for example a wafer containing Through Silicon Vias (TSV).

[0007] In one embodiment, the method includes providing a bonding wafer coupled to a handling wafer, performing a wafer edge trimming process that forms a trimmed bonding wafer, where the wafer edge trimming process removes an edge portion of the bonding wafer and exposes an upper surface of the handling wafer. The method further includes forming a protective mask on the trimmed bonding wafer and on the exposed upper surface of the handling wafer, planarizing the protective mask and the trimmed bonding wafer, and removing the planarized protective mask by an etching process.

[0008] In another embodiment, the method includes providing a silicon bonding wafer coupled to a handling wafer by a low-k bonding layer, where the silicon bonding wafer contains metal filled vias extending through at least a portion of a thickness of the silicon bonding wafer, performing a wafer edge trimming process that forms a trimmed silicon bonding wafer, where the wafer edge trimming process removes an edge portion of the silicon bonding wafer and exposes an upper surface of the handling wafer. The method further includes forming a protective mask by a spin-on process on the trimmed silicon bonding wafer and on the exposed upper surface of the handling wafer, where the protective mask comprises an oxide film, a nitride film, or an oxynitride film, planarizing the protective mask and the trimmed silicon bonding wafer, performing a first wet etching process that selectively removes a portion of the planarized trimmed silicon bonding wafer relative to the protective mask, and after the first wet etching process, performing a second wet etching process that selectively removes the planarized protective mask.

[0009] In yet another embodiment, the method includes providing a silicon bonding wafer coupled to a handling wafer by a low-k bonding layer, where the silicon bonding wafer contains metal filled vias extending through at least a portion of a thickness of the silicon bonding wafer, and where the metal filled vias are in direct contact with the bonding layer, performing a wafer edge trimming process that forms a trimmed silicon bonding wafer, where the wafer edge trimming process removes an edge portion of the silicon bonding wafer and exposes an upper surface of the handling wafer. The method further includes forming a protective mask by a spin-on process on the trimmed silicon bonding wafer and on the exposed upper surface of the handling wafer, where the protective mask comprises a SiO₂ film, planarizing the protective mask and the trimmed silicon bonding wafer, performing a first wet etching process that selectively removes a portion of the planarized trimmed silicon bonding wafer relative to the protective mask, where the first wet etching process comprises exposing the planarizing protective mask and the planarized trimmed silicon bonding wafer to a liquid bath containing TMAH (tetramethyl ammonium hydroxide), HNA (aqueous solution containing hydrogen fluoride, nitric acid, and acetic acid), or KOH (potassium hydroxide), and after the first wet etching process, performing a second wet etching process that selectively removes the planarized protective mask, where the second wet etching process comprises exposing the planarized protective mask to liquid bath containing an organic solvent, or an aqueous solution, where the aqueous solution includes an aqueous solution of hydrogen fluoride.

[0013] Methods for thinning wafers, for example wafers containing Through Silicon Vias (TSV), are disclosed in various embodiments.

[0014] FIG. 1A schematically shows a structure 10 containing a handling wafer 100 coupled to a silicon bonding wafer 102 using a bonding layer 104. The handling wafer 100 and the silicon bonding wafer 102 may be silicon wafers having a radius of 100 mm, 150 mm, 225 mm, or larger. Furthermore, the handling wafer 100 and the silicon bonding wafer 102 may each have total thickness of approximately 1 mm. The silicon bonding wafer 102 further contains a plurality of metal filled vias (holes) 106 in contact with the bonding layer 104. The metal filled vias 106 can, for example, have a diameter between about 1 micron (micron=10⁻⁶ meter) and about 50 microns, for example about 25 microns or about 40 microns. In one example, the metal filled vias 106 may have a diameter of about 25 microns and a height of about 25 microns. In some examples, the metal filled vias 106 can contain or consist of Cu metal. As schematically shown in FIG. 1A, the metal filled vias 106 may extend through only a lower portion of the thickness of the silicon bonding wafer 102.

[0015] The bonding layer 104 can, for example, include a low dielectric constant (low-k) material having a dielectric constant lower than that of SiO₂ (k˜3.9). Such low-k materials can be deposited by a spin-on dielectric (SOD) method similar to the application of photo-resist, by chemical vapor deposition (CVD), or physical vapor deposition (PVD). Low-k dielectric materials may have a dielectric constant of less than 3.7, or a dielectric constant ranging from 1.6 to 3.7. Low-k dielectric materials can include fluorinated silicon glass (FSG), carbon doped oxide, a polymer, a SiCOH-containing low-k material, a non-porous low-k material, a porous low-k material, a spin-on dielectric (SOD) low-k material, or any other suitable dielectric material. The low-k dielectric material can include BLACK DIAMOND® (BD) or BLACK DIAMOND® II (BDII) SiCOH material, commercially available from Applied Materials, Inc., or Coral® CVD films commercially available from Novellus Systems, Inc. Other commercially available carbon-containing materials include SILK® (e.g., SiLK-I, SiLK-J, SiLK-H, SiLK-D, and porous SiLK semiconductor dielectric resins) and CYCLOTENE® (benzocyclobutene) available from Dow Chemical, and GX-3™, and GX-3P™ semiconductor dielectric resins available from Honeywell. In addition, low-k materials can include a silicate-based material, such as hydrogen silsesquioxane (HSQ) or methyl silsesquioxane (MSQ), deposited using SOD techniques. Examples of such films include FOx® HSQ commercially available from Dow Corning, XLK porous HSQ commercially available from Dow Corning, and JSR LKD-5109 commercially available from JSR Microelectronics.

[0016] FIG. 1B shows the structure 10 following a wafer edge trimming process where an edge portion of the silicon bonding wafer 102 and the bonding layer 104 are removed. The resulting trimmed silicon bonding wafer 108 has an upper surface 109b and a sidewall surface 109a above an exposed upper surface 100a of the handling wafer 100. In some examples, the wafer edge trimming process may include a mechanical grinding process.

[0017] FIG. 1C shows a protective mask 110 formed on the structure 10 according to an embodiment of the invention. The protective mask 110 coats the entire trimmed silicon bonding wafer 108, including the sidewall surface 109a and the upper surface 109b, and the upper surface 100a of the handling wafer 100. The protective mask 110 may contain or consist of an oxide film (e.g., SiO₂), a nitride film (e.g., SiN), or an oxynitride film (e.g., SiON).

[0018] According to one embodiment of the invention, the protective mask 110 may be deposited by a spin-on process. The spin-on process can include coating the structure 10 with material that is originally in the liquid form, where the liquid is dispensed onto the wafer surfaces in predetermined amount and the wafers are rapidly rotated. During the rotating (spinning), liquid is uniformly distributed on the surfaces by centrifugal forces, and the material is then solidified by a low temperature bake.

[0019] According to some embodiments of the invention, the protective mask 110 may be deposited by a chemical vapor deposition (CVD) process, a plasma-enhanced CVD (PECVD) process, or a physical vapor deposition (PVD) process. In one example, a conformal protective mask 110 may be formed over the surfaces 109a, 109b, and 100a.

[0020] FIG. 1D shows the structure 10 following a wafer planarizing process. The wafer planarizing process removes the portion of the protective mask 110 on the upper surface 109b and reduces the thickness the trimmed silicon bonding wafer 108 from an initial thickness (e.g., about 1 mm) to a thickness 113 (e.g., about 50 microns). The wafer planarizing process further reduces the thickness of the protective mask 110 on the upper surface 100a of the handling wafer 100. As depicted in FIG. 1D, the resulting structure 10 is planarized and contains planarized protective mask 115 and planarized trimmed silicon bonding wafer 112. In some examples, the wafer planarizing process may be a mechanical grinding process or a chemical mechanical polishing (CMP) process.

[0021] FIG. 1E shows the structure 10 following a first wet etching process that forms an etched planarized trimmed silicon bonding wafer 116 with a thickness 117. The first wet etching process can be highly selective to removal of the silicon material of the planarized trimmed silicon bonding wafer 112 compared to removal of the material (e.g., SiO₂) of the planarized protective mask 115. According to some embodiments of the invention, the first wet etching process may be performed in a liquid bath containing TMAH (tetramethyl ammonium hydroxide), HNA (aqueous solution containing hydrogen fluoride, nitric acid, and acetic acid), or KOH (potassium hydroxide). According to some embodiments of the invention, the first wet etching process may be performed in a liquid bath consisting of TMAH, HNA, or KOH. However, other liquid baths may be used that contain one or more etchants that provide etch good selectivity between the planarized protective mask 115 and planarized trimmed silicon bonding wafer 112.

[0022] As shown in FIGS. 1D and 1E, the presence of the planarized protective mask 115 protects the sidewall surface 109a of the planarized trimmed silicon bonding wafer 112 during the wafer thinning process. In particular, the planarized protective mask 115 prevents chipping of the edges of the silicon bonding wafer 112 and masks wet etching chemicals from the bonding film 104 during a wafer thinning process.

[0023] According to one embodiment of the invention, the thickness 117 of the etched planarized trimmed silicon bonding wafer 116 can be equal to or approximately equal to the original height of the metal filled vias 106 in FIG. 1D. In the embodiment depicted in FIG. 1E, upper surfaces of the metal filled vias 106 are exposed following the first wet etching process.

[0024] FIG. 1F shows the structure 10 following a second wet etching process that removes the planarized protective mask 115 from the handling wafer 100 without removing or thinning the etched planarized trimmed silicon bonding wafer 116. According to one embodiment of the invention, the second wet etching process may be performed in a liquid bath containing an organic solvent, or an aqueous solution, where the aqueous solution includes an aqueous solution of hydrogen fluoride. In one example, the aqueous solution consists of an aqueous solution of hydrogen fluoride. However, other liquid baths may be used that contain one or more etchants that provide etch good selectivity between the planarized protective mask 115 and etched planarized trimmed silicon bonding wafer 116.

[0025] Referring back to FIGS. 1C and 1D, the protective mask 110 can prevent or reduce mechanical damage to the sidewall surface 109a of the planarized trimmed silicon bonding wafer 108 during the wafer planarizing process that was described above and forms the planarized silicon bonding wafer 112. Furthermore, the planarized protective mask 115 shown in FIG. 1D can prevent or reduce damage to the bonding layer 104 during the first wet etching process. Potential damage to the bonding layer 104 can include partial removal (undercutting) of the portion of the bonding layer 104 exposed to the liquid bath used in the first wet etching process.

[0026] Following the second wet etching process, the structure 10 shown in FIG. 1F may be further processed to form a semiconductor device. The further processing can include removing the handling wafer 100 from the wet etched silicon bonding wafer 116.

[0027] FIGS. 2A-2C schematically show cross-sectional views of a process of thinning wafers containing Through Silicon Vias according to other embodiments of the invention. The structure 10 from FIG. 1D is reproduced in FIG. 2A. According to the embodiment depicted in FIG. 2A-2C, the structure 10 may be further planarized to yield the structure 11 shown in FIG. 2B. The further planarizing may be performed by extending the first planarizing process described in FIG. 1D or by performing a second wafer planarizing process that uses different planarizing conditions than the first planarizing process. In some examples, the second planarizing process may have a lower rate of material removal than the first planarizing process.

[0028] The wafer planarizing process depicted in FIGS. 2A-2B further reduces the thickness of the planarized protective mask 115 on the upper surface 100a of the handling wafer 100 and reduces the thickness 113 of the planarized trimmed silicon bonding wafer 112 to a thickness 121. As depicted in FIG. 2B, the resulting structure 11 is planarized and contains planarized protective mask 119 and planarized trimmed silicon bonding wafer 120.

[0029] FIG. 2C shows the structure 11 following a wet etching process that removes the planarized protective mask 119 from the handling wafer 100 without removing the planarized trimmed silicon bonding wafer 120. According to one embodiment of the invention, the wet etching process may be performed in a liquid bath containing an organic solvent, or an aqueous solution, where the aqueous solution includes an aqueous solution of hydrogen fluoride. However, other liquid baths may be used that contain one or more etchants that provide etch good selectivity between the planarized protective mask 119 and planarized silicon bonding wafer 120.

[0030] A plurality of procedures for thinning wafers, for example wafers containing Through Silicon Vias (TSV), have been disclosed in various embodiments. The foregoing description of the embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. This description and the claims following include terms that are used for descriptive purposes only and are not to be construed as limiting. For example, the term “on” as used herein (including in the claims) does not require that a film or a layer “on” a wafer be directly on and in immediate contact with the wafer; there may be a second film or second layer or other structure between the film or layer and the wafer.

[0031] Persons skilled in the relevant art can appreciate that many modifications and variations are possible in light of the above teaching. Persons skilled in the art will recognize various equivalent combinations and substitutions for various components shown in the Figures. It is therefore intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.