Disk drive comprising an interconnect with transmission lines forming an approximated lattice network

[0001] The head in a disk drive is typically mounted on a slider attached to the end of a suspension. The suspension is attached to a distal end of an actuator arm which is rotated about a pivot by a voice coil motor (VCM) in order to actuate the head radially over the disk. The suspension is fabricated with traces (e.g., copper traces) which act as transmission lines that carry the write/read signals between the head and a preamp. It is important to fabricate the traces so as to optimize the signal-to-noise ratio of the write/read signals.

[0012] FIG. 1A shows a disk drive according to an embodiment of the present invention comprising a disk 2, a head 4 actuated over the disk 2, a preamp 6, and an interconnect 8 for coupling the head 4 to the preamp 6. The interconnect 8 comprises a first transmission line 10A stacked over a second transmission line 10B, and a dielectric 12 between the first transmission line 10A and second transmission line 10B (FIGS. 2A-2C). A shape of the first and second transmission lines 10A and 10B varies along a length of the interconnect 8 such that the interconnect 8 comprises an approximation of an inductor/capacitor ladder network (FIG. 2D).

[0013] In the embodiment of FIG. 1A, the head 4 is coupled to a distal end of an actuator arm 14 by a suspension 16 that biases the head 4 toward the surface of the disk 2. As the disk 2 spins, an air bearing forms between the head 4 and disk surface such that the head 4 is said to “fly” over the disk surface. Control circuitry 18 generates a write signal applied to the head 4 through the preamp 6 during write operations, and during read operations demodulates a read signal emanating from the head 4 through the preamp 6. The control circuitry 18 may demodulate embedded servo sectors 20₀-20_N recorded around the circumference of the disk 2 in order to generate a VCM control signal 22 applied to a voice coil motor (VCM) 24 which rotates the actuator arm 14 about a pivot in order to position the head 4 radially over the disk 2.

[0014] Any suitable head 4 may be employed in the embodiments of the present invention, such as a head 4 comprising an inductive write element and a magnetoresistive (MR) read element. A write operation is performed by modulating a write current emanating from the preamp 6 and passing through the transmission lines 10A and 10B and through the inductive write element in order to write magnetic transitions onto the disk surface. During a read operation, the read element senses the magnetic transitions to generate a read signal carried by transmission lines 10A and 10B to the preamp 6. Either or both of the write transmission lines and read transmission lines may comprise an approximated inductor/capacitor ladder network according to different embodiments of the present invention.

[0015] FIG. 2A shows a top-down view of the top transmission line 10A and FIG. 2B shows a top-down view of the bottom transmission line 10B. The transmission lines 10A and 10B may comprise any suitable conductive material, such as copper. FIG. 2C shows the transmission lines 10A and 10B in a stacked configuration having a suitable dielectric 12 (e.g., a suitable plastic) there between. Any suitable technique may be used to fabricate the stacked transmission lines 10A and 10B such as with a suitable etching technique.

[0016] In the embodiment shown in FIGS. 2A-2B, the shape of the first and second transmission lines 10A and 10B that varies comprises a width of the first and second transmission lines as illustrated in the figures. Also in the embodiment of FIGS. 2A-2B, the width of the first transmission line 10A varies symmetrically with the width of the second transmission line 10B.

[0017] FIG. 2D shows a perspective view of the stacked transmission lines 10A and 10B according to an embodiment of the present invention (the dielectric is omitted for clarity). The first transmission line 10A comprises a first segment 26A, and the second transmission line 10B comprises a second segment 26B symmetric with the first segment 26A. The first transmission line 10A comprises a third segment 28A, and the second transmission line 10B comprises a fourth segment 28B symmetric with the third segment 28A. The first segment 26A forms a first series inductance 30A, and the second segment 26B forms a second series inductance 30B. The third and fourth segments 28A and 28B form a shunt capacitance 32. In the embodiment of FIG. 2D, a width of the first and second segments 26A and 26B is less than a width of the third and fourth segments 28A and 28B in order to form the inductor and capacitor elements.

[0018] The transmission lines 10A and 10B shown in FIG. 2D comprise additional symmetrical segments of varying widths to form the remaining inductor and capacitor elements that form the approximation of the inductor/capacitor ladder network. In an embodiment shown in FIG. 3, the transmission lines 10A and 10B are fabricated such that the approximated inductor/capacitor ladder network helps to flatten a magnitude response of the interconnect 8 over a frequency band of at least one of a read signal and a write signal.

[0019] In one embodiment, the approximated inductor/capacitor ladder network boosts the magnitude response at higher frequencies in order to flatten the magnitude response as shown in FIG. 3. However, the approximated inductor/capacitor ladder network may also distort the group delay at higher frequencies. To compensate for the group delay distortion, in an embodiment shown in FIGS. 4A-4C a shape of the first and second transmission lines 10A and 10B varies along a length of the interconnect 8 such that the interconnect comprises an approximation of an inductor/capacitor lattice network. In one embodiment, the approximated inductor/capacitor lattice network compensates for the group delay distortion by flattening the group delay as shown in the embodiment of FIG. 3.

[0020] FIG. 4D shows an embodiment of the present invention wherein the transmission lines 10A and 10B of the interconnect 8 comprise an approximated inductor/capacitor ladder network and an approximated inductor/capacitor lattice network. Any suitable length of transmission line may separate the two networks, and any suitable number of ladder networks (and optionally lattice networks) may be employed along the length of the interconnect 8. In one embodiment, the approximated inductor/capacitor ladder network is fabricated so as to substantially match an impedance of the interconnect 8 to an impedance of the read or write element in the head 4. To facilitate the impedance matching, the approximated inductor/capacitor ladder network is fabricated near the read or write element, whereas the approximated inductor/capacitor lattice network may be fabricated closer to the preamp 6.

[0021] Any suitable configuration of an interconnect for approximating an inductor/capacitor lattice network may be employed in the embodiments of the present invention. FIGS. 5A-5E show an alternative embodiment of an interconnect comprising an approximation of an inductor/capacitor lattice network. Similar to the embodiments described above, the interconnect of FIGS. 5A-5E comprises a first transmission line 10A stacked with a second transmission line 10B, and a dielectric (not shown) between the first transmission line 10A and second transmission line 10B. The inductor/capacitor lattice network comprises a first leg 34A comprising part of the first transmission line 10A stacked with part of the second transmission line 10B, wherein the transmission lines are shorted at a first end 36A of the first leg 34A and open at a second end 38A of the first leg 34A. The inductor/capacitor lattice network further comprises a second leg 34B comprising part of the first transmission line 10A stacked with part of the second transmission line 10B, wherein the transmission lines are shorted at a first end 36B of the second leg 34B and open at a second end 38B of the second leg 34B. A cross-over hub 40 (FIG. 5D) interconnects the first leg 34A and the second leg 34B, wherein as shown in the exploded view of FIG. 5C, the cross-over hub 40 connects a first bottom part 42 of the first leg 34A to a first top part 44 of the second leg 34B, and connects a second bottom part 46 of the first leg 34A to a second top part 48 of the second leg 34B. In the embodiment shown in FIG. 5C, the cross-over hub 40 employs vias (e.g., via 50) to interconnect the legs 34A and 34B, wherein each via comprise part of the transmission line conductor material flowing through an aperture in the dielectric. FIG. 5E shows an exploded view of the shorted ends 36A and 36B (FIG. 5A) of the legs 34A and 34B including vias 52A and 52B.

[0022] The configuration and interconnection of the transmission lines 10A and 10B shown in FIGS. 5A-5E for approximating the inductor/capacitor lattice network may be modified in other embodiments while still performing the desired function of a lattice network. For example, the legs 34A and 34B may be fabricated with any suitable spacing except that a sufficient spacing should be used to avoid cross-talk. In the embodiment of FIGS. 5A-5E the legs 34A and 34B are shown as being parallel to one another; however, the legs may be fabricated with any suitable configuration, such as with a star configuration. In other words, the legs 34A and 34B may be fabricated with any suitable angle with respect to the cross-over hub 40.