Low-cost passive optical waveguide using Si substrate

[0001] Embodiments of the present invention are directed to optical waveguides and, more particularly, to optical waveguides fabricated on a Silicon (Si) substrate.

[0002] High-bandwidth, power efficient, and reliable optical links have potential to change the consumer electronics and server markets as internet data traffic continues to grow exponentially over the years and electronic interconnects are reaching their limits to sustain such growth. Integrated optoelectronic technology can serve as critical enabler to allow personal computing devices to send and receive data at unprecedented rate. In recent years, many successes in optical-component research in the field of silicon photonics have made silicon-on-insulator (SOI) a promising material for the future generations of integrated optoelectronic systems. A typical integrated optoelectronic system could include lasers, modulators, multiplexers/demultiplexers, photo-detectors, and other passive components such as filters, couplers and waveguides.

[0003] Silicon Photonics relies largely on the use of SOI wafers to create passive optical waveguides. A silicon on insulator (SOI) wafer may comprise a silicon substrate having a buried oxide (BOX) layer and a silicon handle layer on the BOX layer. While an SOI based waveguide provides a strong confinement of optical field and the ease of integration with other optical/electrical components, it may not be without tradeoffs.

[0004] First, the cost of SOI process may be substantially larger than a simpler Si process, including both substrate and fabrication expenses. For this reason, a majority of leading foundries have never stepped into SOI market. Second, the buried oxide in SOI tends to block excess heat flow that is inevitably generated by the optical/electrical components, and therefore may feature poor thermal conductivity and stability.

[0013] Described is a passive optical waveguide, which is solely built on a Si substrate while still maintaining high optical quality. It is also suitable for the integration with a variety of active components including, for example, hybrid lasers, modulators, and photodetectors, and therefore enables a new solution to low-cost, high-quality Silicon Photonics.

[0014] Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0015] Referring now to FIG. 1, there is shown a cross-sectional view of a Si wafer 100 having a (100) orientation. Mask layer 102, which may be, for example a hard mask nitride layer, may be deposited on the Si wafer 100 and patterned.

[0016] As shown in FIG. 2, the wafer 100 with mask 102 may be etched to form two trenches 200 and 202. The trenches may be etched with any suitable etching process. In one embodiment the trenches 200 and 202 may be formed with a dry etch process, such as reactive ion etching. The two trenches 200 and 202 may define the lateral boundaries of the final waveguide. The width and depth of the trenches 200 and 202 may be chosen dependent on the desired design parameters of the final waveguide geometry. For example, the trenches 200 and 202 may have a width of 100 nm and a depth of 1 nm.

[0017] Referring now to FIG. 3, the two trenches 200 and 202 may be then exposed to crystallographic etchant such as, for example, KOH (potassium hydroxide), EDP (ethylene diamene pyrocatechol), TMAH (tetramethyl ammonium hydroxide), or _NH₄OH (ammonium hydroxide).

[0018] This wet etch process will create two diamond-like openings, 300 and 302, with an Si neck piece 304 remaining in-between. The openings or cavities 300 and 302 may comprise a ˜54.7° angle with respect to normal. The exact shape depends on the initial trench width & depth, as well as the wet-etch rate and duration.

[0019] As shown in FIG. 4, a layer of silicon oxide 400 may be grown, such as by thermal oxide growth, on the inner walls of the diamond shaped openings 300 and 302. As shown, the oxide 400 may be grown thick enough that that it converges at the opposing inner vertices 412 of the diamond shaped openings 300 and 302, creating an inverted triangular section of Si 410. This inverted triangular section comprises the Si waveguide 410 according to one embodiment of the invention. Of course, the apex of the triangle may not be at a perfect point, thus the shape of the inverted triangular Si waveguide may be considered generally inverted triangular or inverted trapezoidal waveguide dubbed ITWG. The Si ITWG 410 being enclosed by surrounding oxide 400 enables guiding of light by Total Internal Reflection (TIR).

[0020] As shown in FIG. 5, the wafer 100 may thereafter be replanarized, such as by depositing and then reflow an oxide (or polymer) material 500 to fill the diamond holes.

[0021] Because the IT waveguide 410 sidewalls are created by wet-etching a re-entrant (111) Si crystal plane, ultra-smoothness is expected. Unlike the popular rib/ridge SOI waveguide where sidewalls are defined by dry etch that induces surface roughness, the IT waveguide 410 according to embodiments of the invention feature negligible scattering loss compared to even the best passive optical waveguide that exists in the literature.

[0022] From the integration point of view, the IT waveguide 410 may provide advantages for many applications. First, as shown in FIG. 6, an optic or optoelectronic device 600 may be provided on top of the waveguide 410. The device 600 may be, for example, a hybrid laser, which is an active layer (e.g. InP wafer) bonded directly on top of waveguide 410. This may allow a cost effective solution as well as a better thermal sink compared to current SOI waveguide architecture.

[0023] Second, the device 600 may comprise an electroabsorption modulator (e.g. SiGe Franz-Keldysh effect) built on the proposed device. The device 600 may also comprise a waveguide photodetector (e.g. Ge direct band-gap absorption) also built on the proposed device. Minimum modifications on the existing process flows of these two devices are expected. Finally, the device 600 may comprise optoelectronics integrated with IC components (e.g. drivers and amplifiers) formed on a single Si wafer 100. Additional changes on the IC fabrication due to the buried oxide in SOI wafers are not necessary according to some embodiments.

[0024] FIG. 7 shows a flow diagram for forming a Si IT waveguide according to one embodiment. In box 700, the process may start with a standard (100) Si wafer. A hard mask (e.g. nitride layer) may then be deposited and patterned on the wafer surface.

[0025] In box 702, two side-by-side trenches may be dry-etched (e.g. reactive ion etch) to define waveguide lateral boundaries. The width and depth of the two trenches depends on the designed final IT waveguide geometry. In box 704, the wafer may then be immersed, for example, in a crystallographic etchant (e.g. NH4OH), which opens up two side-by-side diamond-like shaped cavities with a ˜54.7° angle with respect to normal. The exact shape depends on the initial trench width & depth, as well as the wet-etch rate & duration.

[0026] In box 706, a thermal oxide may be grown on the Si wafer surface and in the cavities until the “neck” of the Si piece sandwiched in-between the two diamond shaped cavities is filled with oxide. The mask may be first removed if desired. The IT waveguide 410 is now formed as shown in the cross-section view, for example of FIG. 6. Thereafter devices that utilize the waveguide may be fabricated or placed in the wafer.

[0027] Waveguide bend may also be made by adopting similar process flow. However, the mask shape may be re-designed instead of a simple curve because the crystallographic wet-etch attacks the (111) Si plane, which may results into a zigzag shape (top view) along a non-straight waveguide.

[0028] According to embodiments, a low-cost, high-quality Si waveguide is provided which could potentially replace the existing SOI waveguides. In addition, the thermal stability of any active components build on the invention is expected to be superior, simply because the Si wafer is an efficient heat sink compared to SOI wafers. In addition, using Si wafers is generally preferred for high-volume manufacture because the majorities of leading foundries that can provide sufficient volumes for consumer electronics process Si wafers and generally do not process SOI wafers because of the additional cost of SOI wafer and processing.

[0029] The above description of illustrated embodiments of the invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize.

[0030] These modifications can be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed in the specification and the claims. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.