Data storage device employing high quality metrics when decoding logical block address appended to a data sector

[0001] Computer systems (e.g., desktops, laptops, portables, etc.) typically employ some form of a non-volatile data storage device such as a disk drive, or a solid state drive comprising a non-volatile semiconductor memory such as flash memory. A solid state drive typically emulates a disk drive so that the same communication protocol may be employed. That is, a host typically interfaces with a solid state disk drive using a standard disk drive communication protocol, such as the Advanced Technology Attachment (ATA) protocol.

[0002] When manufacturing a conventional disk drive, servo sectors 2₀-2_N are written to a disk 4 which define a plurality of radially-spaced, concentric data tracks 6 as shown in the prior art disk format of FIG. 1. Each data track 6 is partitioned into a plurality of data sectors wherein the servo sectors 2₀-2_N are considered “embedded” in the data sectors. Each servo sector (e.g., servo sector 2₄) comprises a preamble 8 for synchronizing gain control and timing recovery, a sync mark 10 for synchronizing to a data field 12 comprising coarse head positioning information such as a track number, and servo bursts 14 which provide fine head positioning information. The coarse head position information is processed to position a head over a target track during a seek operation, and the servo bursts 14 are processed to maintain the head over a centerline of the target track while writing or reading data during a tracking operation.

[0003] The ever increasing complexity of the control programs to coordinate the numerous components of the disk drive increases the probability of a programming error resulting in the wrong data being transferred to the host during read operations or written to the disk during write operations. To help protect against transferring bad data to the host, prior art disk drives have implemented “data path protection” techniques wherein the logical block address (LBA) received from the host during a write operation is used to encode error detection code (EDC) data that are appended to the corresponding data sector written to the disk. Alternatively, the host may use the LBA to encode the EDC data which is transmitted to the disk drive together with the user data for the write command. During a read operation of the data sector, the disk drive may generate check data using the LBA received from the host to verify the integrity of the read data, and/or the host may generate check data using the LBA to verify the integrity of the read data once received. If the check data does not match the EDC data appended to the data sector, an error condition is triggered.

[0014] FIG. 2A shows a disk drive according to an embodiment of the present invention comprising a disk 16 having a plurality of data tracks 18, wherein each data track comprises a plurality of data sectors. The disk drive further comprises a head 20 actuated over the disk 16 and control circuitry 22 for executing the flow diagram of FIG. 2B. A read command is received from a host (step 24), wherein the read command comprises a read logical block address (LBA_R). A target data sector is read in response to the LBA_R to generate a read signal (step 26). The read signal is processed to detect user data and redundancy data using a soft-output detector that outputs quality metrics for the user data and redundancy data (step 28). A high quality metric is assigned to the LBA_R (step 30), and errors are corrected in the user data using an error correction code (ECC) decoder in response to the quality metrics output by the soft-output detector and the quality metrics assigned to the LBA_R (step 32).

[0015] In the embodiment of FIG. 2A, the disk 16 comprises a plurality of servo sectors 34₀-34_N that define the plurality of data tracks 18. The control circuitry 22 processes the read signal 36 to demodulate the servo sectors 34₀-34_N into a position error signal (PES). The PES is filtered with a suitable compensation filter to generate a control signal 38 applied to a voice coil motor (VCM) 40 which rotates an actuator arm 42 about a pivot in order to position the head 20 radially over the disk 16 in a direction that reduces the PES. The servo sectors 34₀-34_N may comprise any suitable position information, such as a track address for coarse positioning and servo bursts for fine positioning.

[0016] FIG. 3A shows control circuitry 22 according to an embodiment of the present invention for executing a write command to write user data to a data sector, and a corresponding read command to read the user data from the data sector. When the write command is received from the host, the write command includes the user data and a write logical block address (LBA_W) which identifies the target data sector to be written. An ECC encoder 44 encodes the user data and the appended LBA_W to generate redundancy data. The LBA_W is then stripped 46 from the resulting codeword and only the user data and redundancy data are written to the disk 16. When a corresponding read command is received to read the target data sector, the data sector is read to generate a read signal 36 processed by a soft-output detector 48 to detect the user data and redundancy data d0-dn as well as generate associated quality metrics QM0-QMn. An ECC decoder 50 processes the user data, the redundancy data, and the quality metrics using an iterative algorithm in order to correct errors in the user data. Since the redundancy data is also generated over the LBA_W during the write operation, during the read operation the read logical block address (LBA_R) received from the host is processed by the ECC decoder 50 together with quality metrics (LBA_QM) assigned to the LBA_R. After successfully correcting the user data, the control circuitry checks whether a correction was also made to the LBA_R 52. If a correction was made to the LBA_R in order to generate the LBA_W, then an error is returned to the host since the LBA_R does not match the LBA_W.

[0017] When initially attempting to recover the user data, high quality metrics (LBA_QM) are assigned to the LBA_R for processing by the ECC decoder 50. In this manner, the ECC decoder 50 will assume the LBA_R matches the LBA_W (no error in the LBA_R) and thereby focus the correction power of the ECC on the user data. In an embodiment described below, if the ECC decoder 50 is unsuccessful in correcting the user data using high quality metrics for the LBA_R, then the quality metrics are modified (e.g., set to a low value) and the ECC decoding re-executed.

[0018] Any suitable soft-output detector 48 may be employed in the embodiments of the present invention. In an embodiment shown in FIG. 3B, the soft-output detector comprises a suitable Viterbi detector 54 which outputs a quality metric for each symbol of the detected data sequence. Another suitable soft-output detector for generating quality metrics is the Bahl-Cocke-Jelinek-Raviv (BCJR) detector. Any suitable quality metric may be generated, wherein the quality metric represents a probability that the detected data symbol was accurately detected. An example quality metric is a log likelihood ratio (LLR), wherein a value of 0 may represent the lowest probability and a value of 1 may represent the highest probability. In one embodiment, the quality metrics associated with the LBA_R are initially set at or near the highest possible value (step 30 of FIG. 2B) indicating a high probability that there are no errors in the LBA_W (i.e., a high probability that the LBA_R will match the LBA_W).

[0019] Any suitable ECC decoder 50 capable of processing the quality metrics generated by the soft-output detector may be employed in the embodiments of the present invention. The ECC decoder 50 processes the redundancy data as well as the quality metrics output by the soft-output detector 48 in order to increase the likelihood of accurately recovering the user data as compared to a straight “binary” ECC decoder. In one embodiment, the ECC decoder 50 operates according to a trellis of a Viterbi algorithm wherein the quality metrics are evaluated as branch metrics. In another embodiment, the ECC decoder 50 comprises an iterative decoder such as a low-density parity-check (LDPC) decoder 56 as shown in the embodiment of FIG. 3B. An iterative ECC decoder processes the detected data in iterations, wherein after each iteration the quality metrics are updated. Typically an iterative decoder will either converge successfully, or “time out” after exceeding a predetermined number of iterations. In an embodiment shown in FIG. 3C, after each iteration the iterative ECC decoder 60 feeds back the updated quality metrics to a soft-input-output detector 58, such as a soft-input-output Viterbi detector or a Turbo Code detector. The soft-input-output detector 58 processes the updated quality metrics in order to improve the accuracy of the detected data sequence input into the iterative ECC decoder 60 for the next iteration.

[0020] FIG. 4A is a flow diagram according to an embodiment of the present invention wherein the control circuitry 22 receives a write command from the host including user data and a write logical block address (LBA_W) identifying one or more target data sectors (step 62). Redundancy data is generated over the user data and the LBA_W (step 64), and the user data and redundancy are written to the target data sector (step 66). The LBA_W may also be written to the target data sector and used to verify the accuracy of the LBA during a read operation by comparing the LBA_W read from the target data sector to the LBA_R received from the host during the read operation.

[0021] FIG. 4B is a flow diagram according to an embodiment of the present invention wherein the LBA_W is not written to the target data sector. The control circuitry 22 receives a read command from the host including a read logical block address (LBA_R) identifying one or more target data sectors (step 68). The target data sector identified by the LBA_R is read (step 70), and the read signal processed by a soft-output detector to detect the user data and the redundancy data and generate associated quality metrics (step 72). High quality metrics are assigned to the LBA_R (step 74) which is then combined with the user data and the redundancy data to form a codeword (step 76). The codeword is then decoded by an ECC decoder using the quality metrics associated with the user data, redundancy data, and LBA_R (step 78).

[0022] FIG. 5 is a flow diagram according to an embodiment which extends on the flow diagram of FIG. 4B. When the ECC decoding of the user data fails (step 80) using high quality metrics assigned to the LBA_R, it may mean that the LBA_R contains an error. In order to correct this error, low quality metrics are assigned to the LBA_R (step 82) and the user data is decoded again by the ECC decoder using the updated quality metrics (step 84). If the ECC decoding fails again (step 86), an error message is returned to the host. Otherwise if the ECC decoding is successful, but the LBA_R was corrected, it means the LBA_R received from the host did not match the LBA_W of the target data sector, and therefore an error is returned to the host (step 88).

[0023] FIG. 6 is a flow diagram according to an embodiment of the present invention wherein the LBA_R received from the host during a read operation is copied (step 90) to a codeword placeholder (LBA_RC). The LBA_RC is combined (step 92) with the user data and redundancy data generated by the soft-output detector to form a codeword that is decoded by the ECC decoder using the quality metrics (step 94). If the ECC decoding fails (step 96), an error is returned to the host. Otherwise if the ECC decoding is successful, but the LBA_R received from the host does not match the codeword placeholder (LBA_RC), it means that the LBA_RC was corrected during the ECC decoding and therefore an error is returned to the host (step 98) since the LBA_R does not match the LBA_W.

[0024] Any suitable control circuitry may be employed to implement the flow diagrams in the embodiments of the present invention, such as any suitable integrated circuit or circuits. For example, the control circuitry may be implemented within a read channel integrated circuit, or in a component separate from the read channel, such as a disk controller, or certain steps described above may be performed by a read channel and others by a disk controller. In one embodiment, the read channel and disk controller are implemented as separate integrated circuits, and in an alternative embodiment they are fabricated into a single integrated circuit or system on a chip (SOC). In addition, the control circuitry may include a suitable preamp circuit implemented as a separate integrated circuit, integrated into the read channel or disk controller circuit, or integrated into an SOC.

[0025] In one embodiment, the control circuitry comprises a microprocessor executing instructions, the instructions being operable to cause the microprocessor to perform the steps of the flow diagrams described herein. The instructions may be stored in any computer-readable medium. In one embodiment, they may be stored on a non-volatile semiconductor memory external to the microprocessor, or integrated with the microprocessor in a SOC. In another embodiment, the instructions are stored on the disk and read into a volatile semiconductor memory when the disk drive is powered on. In yet another embodiment, the control circuitry comprises suitable logic circuitry, such as state machine circuitry.

[0026] Although the above embodiments have been described with reference to a disk drive, the aspects of the present invention may be employed within any suitable data storage device comprising any suitable storage medium, such as a magnetic disk of a disk drive, a semiconductor memory of a solid state drive, etc.