Data storage device employing data path protection using both LBA and PBA

[0001] Data storage devices, such as disk drives and solid state drives are employed in numerous areas such as computer systems (e.g., desktops, laptops, portables, etc.) and consumer devices (e.g., music players, cell phones, cameras, etc.). User data is typically stored in a non-volatile memory, such as a magnetic disk or a non-volatile semiconductor memory (e.g., flash memory). In order to enable defect mapping (mapping out of defective memory segments of the non-volatile memory), as well as enable wear leveling in solid state drives, the memory segments are typically accessed indirectly by mapping logical block addresses (LBAs) to physical block addresses (PBAs). That is, host access commands (write or read) comprise an LBA that is mapped to a PBA representing a memory segment, where the PBA may change over time due to relocating from a grown defect, or wear leveling to evenly distribute access to the memory segments.

[0002] When accessing a memory segment using LBA to PBA mapping, it is important for the storage device to access the correct memory segment. For various reasons, such as malfunctioning firmware, a data storage device may write/read data to/from the wrong PBA, or write the wrong data to the correct PBA, perhaps because of an error in accessing a cache buffer, or in the LBA to PBA mapping algorithm, or in the mapping of PBA to the memory segment. The prior art has employed various forms of “data path protection” wherein the LBA or the PBA may be used during the write/read operations to ensure the correct memory segment is read and that the memory segment stores the correct data during a read operation. For example, the prior art has suggested to seed an error code with either the LBA or the PBA during writing and reading which helps ensure the correct memory segment is being accessed, and that the correct data was written to the memory segment.

[0015] FIG. 1A shows a data storage device 2 according to an embodiment of the present invention comprising a non-volatile memory 4 including a plurality of memory segments. The data storage device 2 further comprises control circuitry 6 for executing the flow diagram of FIG. 1B. A write command is received comprising a logical block address (LBA) and user data (step 8). The LBA is mapped to a physical block address (PBA) for addressing one of the memory segment (step 10). First error code redundancy is generated in response to the LBA (step 12), and second error code redundancy in response to the PBA (step 14). User data and the first and second error code redundancy are written to the memory segment addressed by the PBA (step 16).

[0016] FIG. 1C illustrates a memory segment after executing the write operation of FIG. 1B, wherein the written data comprises user data 18, first error correction redundancy 20 generated in response to the LBA, and second error correction redundancy 22 generated in response to the PBA. Any suitable error code may be employed to generate the first and second redundancy. In an embodiment shown in FIG. 1D, the first error code comprises an error detection code, such as a cyclic redundancy check (CRC) code, and the second error code comprises an error correction code (ECC) such as a Reed-Solomon code or a low-density parity-check (LDPC) code. In yet another embodiment illustrated in FIG. 1E, the LBA 24 is also written to the memory segment to facilitate data path protection and/or rebuilding of LBA to PBA mapping after a power failure.

[0017] FIG. 2A illustrates a write operation according to an embodiment of the present invention which is understood with reference to the flow diagram of FIG. 3. A write command is received from a host comprising user data and a target LBA to write the user data (step 26). The LBA is mapped to a PBA representing a memory segment in the non-volatile memory (step 28). An EDC redundancy generator 30 is seeded with the target LBA 24 (step 32), and an ECC redundancy generator 34 is seeded with the PBA 36 mapped from the LBA 24 (step 38). The EDC generator 30 generates first error code redundancy 20 over the user data and target LBA 24 (step 40). The ECC redundancy generator 34 generates second error code redundancy 22 over the user data and target LBA 24 as well as over the first error code redundancy 20 (step 42). The user data 18 and target LBA 24, first error code redundancy 20, and second error code redundancy 22 are written to a memory segment in the non-volatile memory 4 in any suitable order (step 44).

[0018] FIG. 2B illustrates a read operation according to an embodiment of the present invention which is understood with reference to the flow diagram of FIG. 4. A read command is received from a host comprising a target LBA 46 to read from (step 48). The LBA 46 is mapped to a PBA 50 representing a memory segment in the non-volatile memory (step 52). An ECC syndrome generator 54 is seeded with the PBA 50 (step 56), and an EDC syndrome generator 58 is seeded with the LBA 46 (step 60). The user data 18, LBA 24, first error code redundancy 20, and second error code redundancy 22 are read from the memory segment (step 62). The ECC syndrome generator 54 generates a first error syndrome 64 over all the data (step 66), wherein the first error syndrome 64 is processed to determine whether the memory segment is correctable (step 68). If the memory segment is correctable, an error corrector 70 processes the first error syndrome 64 to correct errors in the data read from the memory segment (step 72), which may include an error in the LBA 24. After correcting the errors, the EDC syndrome generator 58 generates a second error syndrome 74 over the user data 18, LBA 24, and first error code redundancy 20 (step 76). If the second error syndrome 74 indicates an error (step 78), it means a miss-correction occurred, or it means the target LBA 46 received with the read command does not match the LBA 24 read from the memory segment and an error is generated. Otherwise the user data 18 read from the memory segment is returned to the host (conceptually illustrated with an AND gate 80 in FIG. 2B).

[0019] As illustrated in the embodiment of FIG. 1D, the above described write/read operations may be implemented without writing the target LBA 24 of the write command to the memory segment. This embodiment will still provide protection against a mismatch between the target LBA received in a read command and the corresponding LBA used during a write operation. In the embodiment of FIG. 1E where the target LBA 24 of a write command is written to the memory segment, the written LBA 24 may be used to rebuild the LBA to PBA mapping information, for example, after a power failure.

[0020] When a power failure occurs, the more recently generated LBA to PBA mapping data stored in the volatile semiconductor memory of the data storage device may be lost. However, the most recently written PBAs may be known (e.g., when implementing a log-structured file system or derivative thereof). If the target LBA 24 of a write command is written to each memory segment as illustrated in the embodiment of FIG. 1E, the LBA 24 read from the memory segment can be used to regenerate the LBA to PBA mapping after a power failure. This embodiment is understood with reference to the flow diagram of FIG. 5 wherein a target PBA to read is determined based on the location of previous write operations (step 82). The ECC syndrome generator is seeded with the target PBA (step 84), and the user data, LBA, and first/second error code redundancy are read from the memory segment (step 86) to generate the ECC error syndromes (step 88). If the ECC error syndromes indicate the memory segment is correctable (step 90), the data read from the memory segment is corrected (step 92) which may include correcting an error in the LBA. The LBA is then extracted from the read data (step 94) and the flow diagram of FIG. 4 is re-executed (step 96) in order to verify that it is the correct LBA. If the flow diagram of FIG. 4 returns successfully, then the LBA to PBA mapping is updated (step 98).

[0021] In the embodiment of FIG. 2A, the first error code redundancy 20 and the second error code redundancy 22 are shown as being generated concurrently as the user data and LBA are written to the memory segment of the non-volatile memory 4. In an alternative embodiment not shown, the first error code redundancy 20 may be generated as the user data and LBA are received from the host in a write command, wherein the user data, LBA, and first error code syndrome 20 are staged in a buffer. When the staged write data is ready to be written to the memory segment, the second error code redundancy 22 is generated as the user data, LBA, and first error code redundancy 20 are read from the buffer.

[0022] The embodiments of the present invention may be employed in any suitable data storage system. FIG. 6 shows a data storage system comprising a disk drive including a head 100 actuated over a disk 102 and control circuitry 104 for executing at least part of the flow diagrams described herein. FIG. 7 shows a solid state drive comprising a plurality of non-volatile semiconductor memories 106A, 106B, etc., such as flash memories, and control circuitry 108 for executing at least part of the flow diagrams described herein. A hybrid data storage system may also be employed comprising components of a disk drive shown in FIG. 6 combined with the non-volatile semiconductor memories shown in FIG. 7.