Fully compensated adaptive interference cancellation system

[0001] This document claims the benefit of the filing date of U.S. Provisional Patent Application No. 61/177,231, entitled “Fully Compensated Adaptive Interference Cancellation System” to Lianfeng Peng et al. which was filed on May 11, 2009, the disclosure of which is hereby incorporated entirely herein by reference.

[0002] 1. Technical Field

[0003] Aspects of this document relate generally to telecommunication systems and methods for signal interference cancellation for data transmission through a telecommunication channel.

[0004] 2. Background Art

[0005] Conventional telecommunications systems utilize circuitry relating to interference cancellation such as that described in U.S. Publication No. 2002/0197958A1 (www.ptodirect.com/publication/?20020197958) which is herein incorporated by reference in its entirety. Conventional circuits have the following disadvantages:

• • [0006] a) The adaptive filter or least mean square (LMS) equalizer operates far from full scale which results in reduced precision and accuracy in cancellation performance. While the conventional circuit does have a front-end automatic gain control (AGC), this AGC optimizes only the analog-to-digital (A/D) dynamic range which is commonly implemented in digital communications systems.
  • [0007] b) The adaptive filter is only capable of correcting a limited range of phase errors just as the digital phase locked loop (DPLL) is which therefore results in the adaptive FIR filter and the DPLL having an increased chance of phase correction conflict.
  • [0008] c) When the adaptive filter has more taps (i.e. more than 11 taps), the phase tracking capability of the DPLL is slow, making adaptation more difficult.
  • [0009] d) The delay tracking capability is poor because when there is a delay handover from the adaptive equalizer to the delay manager, there is no practical way for the DPLL to adjust to the change immediately. This leads to difficulty in tracking a high Doppler rate of change.
  • [0010] e) The adaptive FIR filter has to be complex because phase and frequency correction of the interference is done before the adaptive FIR filter. In applications where spectrum linear distortion is minimal, the complex adaptive FIR filter requires unnecessary extra resources.

[0011] U.S. Pat. No. 4,736,455, which is herein incorporated by reference in its entirety, includes another example of a conventional interference cancellation system. Like the above described conventional interference cancellation system, implementations of the present interference cancellation system may be used in multiple carrier frequency reuse communications systems, such as satellite communications systems.

[0012] Implementations of telecommunication systems like those disclosed in this document may include implementations of a system for removing interference from a composite received baseband signal comprising a receive decimation filter that accepts the composite received baseband signal and generates filtered sampled data at a decimation rate wherein the composite received baseband signal comprises a desired signal and an interfering signal, a transmit decimation filter that accepts a digitally converted replica of the interfering signal and generates filtered sampled data at a decimation rate and an integer sample delay control (ISDC) that provides multiple sample delay control for the replica of the interfering signal and stores an estimated delay value. The system further comprises an adaptive filter that provides fractional sample delay control for the replica of the interfering signal and optimizes cancellation of the interfering signal present in the composite received baseband signal, a digital phase-locked loop (DPLL) programmed with a known frequency offset of the interfering signal that tracks a phase and frequency of the replica of the interfering signal, an automatic gain control (AGC) that maintains near full scale operation of adaptive filtering and the DPLL, a slicer which is effectively a subtractor, and an error estimator which is formed by the slicer, a mixer and a delay unit.

[0013] Particular implementations may include one or more of the following. The estimated delay value corresponds to a delay difference between the interfering signal and the replica of the interfering signal. The DPLL is located after the adaptive filter. The adaptive filter uses a least mean square (LMS) algorithm and a finite impulse response (FIR) filter.

[0014] The integer sample delay control (ISDC) further comprises a computer readable medium that stores a complex sample of the replica of the interfering signal and a multiple sample delay control mechanism.

[0015] The computer readable medium uses double data rate synchronous dynamic random access memory (SDRAM) or any memory device capable of storing the sample data.

[0016] The adaptive filter further comprises a finite impulse response (FIR) filter. The FIR filter can be a real or complex FIR filter, and may be configured to switch between a real and a complex FIR filter.

[0017] The DPLL further comprises a phase detector that includes an arctangent function and a complex multiplier, a second order loop filter or a third order loop filter, an adder that accepts an initial frequency offset and an output of the loop filter, and a complex numerical controlled oscillator (NCO) that accepts a sum of the initial frequency offset and the output of the loop filter and provides a complex sinusoidal output.

[0018] The AGC further comprises an FIR coefficient calculator that sums the LMS coefficients and determines an absolute value of the sum, a subtractor that calculates a difference between the absolute value and a target gain, a multiplier to scale the difference, and an integrator that accumulates the scaled difference.

[0019] The error estimator further comprises a complex multiplier that accepts a complex conjugate of a delayed output of the complex NCO and an output of the slicer to update the LMS coefficients.

[0020] In another aspect, implementations of an interference cancellation may further provide for a method for removing interference from a composite received baseband signal comprising accepting, by a receive decimation filter, the composite received baseband signal wherein the composite received baseband signal comprises a desired signal and an interfering signal, generating, by the receive decimation filter, filtered sampled data at a decimation rate, and accepting, by a transmit decimation filter, a digitally converted replica of the interfering signal. The method further comprises generating, by a the transmit decimation filter, filtered sampled data at a decimation rate, providing, by an integer sample delay control (ISDC), multiple sample delay control for the replica of the interfering signal, storing, by the integer sample delay control (ISDC), an estimated delay value, providing, by an adaptive filter, fractional sample delay control for the replica of the interfering signal, optimizing, by the adaptive filter, cancellation of the interfering signal present in the composite received baseband signal, tracking, by a digital phase-locked loop (DPLL) that is programmed with a known frequency offset of the interfering signal, a phase and frequency of the replica of the interfering signal, maintaining, by an automatic gain control (AGC), near full scale operation of adaptive filtering and the DPLL, and updating an adaptive filter coefficient by an error estimator having a conjugate multiplier and a slicer.

[0021] Particular implementations may include one or more of the following. The estimated delay value corresponds to a delay difference between the interfering signal and the replica of the interfering signal. The DPLL is located after the adaptive filter. A least mean square (LMS) algorithm and a finite impulse response (FIR) filter is used. The adaptive filter further comprises a finite impulse response (FIR) filter. The FIR filter can be a real or complex FIR filter, and may be configured to switch between a real and a complex FIR filter. The method further comprises storing by the integer sample delay control (ISDC) on a computer readable medium, a complex sample of the replica of the interfering signal and providing a multiple sample delay control mechanism.

[0022] The method further comprises using, by the computer readable medium, double data rate synchronous dynamic random access memory (SDRAM) or any memory device capable of storing sample data.

[0023] The adaptive filter further comprises a finite impulse response (FIR) filter. The FIR filter can be a real or complex FIR filter, and may be configured to switch between a real and a complex FIR filter. The tracking by the DPLL further comprises detecting a phase using an arctangent function and a complex multiplier, determining estimated loop parameters based on a sampling rate for a second order loop filter or a third order loop filter, accepting, by an adder, an initial frequency offset and an output of the loop filter, accepting, by a complex numerical controlled oscillator (NCO), a sum of the initial frequency offset and the output of the loop filter; and providing, by the complex NCO, a complex sinusoidal output.

[0024] Maintaining, by an automatic gain control (AGC) further comprises summing, by an FIR coefficient calculator, the LMS coefficients, determining, by the FIR coefficient calculator, an absolute value of the sum, calculating, by a subtractor, a difference between the absolute value and a target gain, scaling the difference by a multiplier; and accumulating, by an integrator, the scaled difference.

[0025] Updating an adaptive filter coefficient by the error estimator further comprises accepting, by a complex multiplier, a complex conjugate of a delayed output of the complex NCO and an output of the slicer to update the LMS coefficients.

[0026] The foregoing and other aspects, features, and advantages will be apparent to those artisans of ordinary skill in the art from the DESCRIPTION and DRAWINGS, and from the CLAIMS.

[0037] This disclosure, its aspects and implementations, are not limited to the specific components or assembly procedures disclosed herein. Many additional components and assembly procedures known in the art consistent with the intended interference cancellation system and/or assembly procedures for a telecommunication system using interference cancellation will become apparent for use with particular implementations from this disclosure. Accordingly, for example, although particular implementations are disclosed, such implementations and implementing components may comprise any shape, size, style, type, model, version, measurement, concentration, material, quantity, and/or the like as is known in the art for such telecommunication systems using interference cancellation and implementing components, consistent with the intended operation.

[0038] Implementations of interference cancellation systems as provided in this disclosure improve the performance of conventional interference cancelling systems and may be implemented with the use of a field-programmable gate array (FPGA), digital signal processor (DSP), or general purpose processor which is capable of using most digital signal processing techniques.

[0039] It is assumed that the initial delay and frequency offset estimations of the undesired signal relative to its replica are known. These initial parameters can be determined using some known algorithms found in literatures, such as described by Stein, “Algorithms for Ambiguity Function Processing”, IEEE Transactions on Acoustics, Speech, and Signal Processing, Vol. ASSP-29, No. 3, pp 588-599, June 1981, which is hereby incorporated entirely by this reference.

[0040] Implementations of the interference cancellation systems disclosed herein may operate on baseband or near baseband signals wherein analog signals are converted to digital samples for signal processing. The cancellation of the interfering signal from the composite received signal employs digital signal processing (DSP) techniques such as adaptive filtering or equalization, which can be easily implemented in FPGA's, DSP's, or a general purpose processor.

[0041] This disclosure also provides a method and system for canceling the interfering signal from the composite received signal containing the undesired signal and desired signal, wherein the digital phase-locked loop (DPLL) does not intervene with the adaptive equalizer in terms of phase tracking capability and delay tracking capability. Hence it improves delay tracking performance at high Doppler rate of change for satellite applications. It also allows use of the real adaptive filter instead of the complex one if applicable in a particular application, which substantially reduces the required resource.

[0042] In other aspects, this disclosure provides for a method and system for improving the cancellation performance by providing automatic gain control (AGC) that is driven by the adaptive filter (or LMS equalizer) in order to operate nearly full scale in digital form.

[0043] Unlike conventional interference cancellation systems, this disclosure and related implementations may be embedded in a digital communications system containing a modulator and demodulator such as a satellite modem as shown in FIG. 1, but may also be implemented as a separate component similar to that which is found in the conventional system and may be utilized in any wireless or wired communication system such as, for example, a cellular communications network.

[0044] FIG. 1 depicts a satellite communications system having an adaptive interference cancellation system embedded within the satellite modem. In this diagram, the radio frequency (RF) equipments such as up converter, down converter, high-power amplifier, and low-noise amplifier are omitted for simplicity of illustration. As shown in the diagram, the adaptive interference canceller mimics the delay, frequency, and phase offsets as well as the amplitude (not shown) of the interfering signal contained in a composite received signal to a replica of the interfering signal. In this diagram for example at Site A, S_A is the replica of the interfering signal, while S_A(Δd,Δf,Δφ)+S_B is the composite received signal containing the interfering signal S_A(Δd,Δf,Δφ) having delay offset (Δd), frequency offset (Δf), and phase offset (Δφ) and the desired signal S_B.

[0045] FIG. 2 illustrates an implementation of an adaptive interference cancellation system. The system comprises a receive decimation filter 1 and a transmit decimation filter 2 which may be identical in configuration, an Integer Sample Delay Control (ISDC) 3 that handles delay of integer multiple samples, a Fractional Sample Delay Control (FSDC) 4 that uses an adaptive filter to handle fractional sample delay (delay less than one sample), a Digital Phase-Locked Loop (DPLL) 5, an Automatic Gain Control (AGC) 6, two mixers (Mixers 1 & 2) 8, 9 which are effectively two complex multipliers, a Gain Controller 12, a Slicer 7 and two matching delay elements (Delay Units 1 & 2). The Slicer 7, Mixer 2, 9 and Delay Unit 2, 11 form an error estimator. Transmit decimation filter 2 is used to filter an interfering signal or a replica of an interfering signal and receive decimation filter 1 is used to filter the composite received signal to achieve a required sampling or decimation rate. Provided that both decimation filters 1, 2 are identical, the replica of the interfering signal mimics the filtered characteristics of the interfering signal contained in the composite received signal. The decimation filters may be implemented with any known digital filters which can decimate digital signals from one sample rate to another. A commonly used and simple one is the cascaded integrator-comb (CIC) filter, although one of ordinary skill in the art would recognize that any appropriate decimation filter may also be used.

[0046] The ISDC 3 stores an initial delay estimate and delays the interference signal in integer multiple samples during operation. The FSDC 4 may use a least mean square (LMS) adaptive equalizer to track fractional sample delay wherein the delay is less than one sample. It consistently monitors the mass center of the LMS finite impulse response (FIR) coefficients' power. When the mass center has shifted by one tap or more, FSDC 4 signals ISDC 3 to advance or delay the interference signal by one sample and shifts the LMS coefficients accordingly to accommodate this shift in the interference signal. This event is called delay handover.

[0047] As shown in FIG. 2, phase and frequency correction of the interference signal by the DPLL 5 is done after the FSDC 4, where delay of the interference has been matched to that in the composite received signal. Because the delay handover from the FSDC 4 to ISDC 3 is completely transparent to the DPLL 5, the handover is thus smoother and implementation is simpler and easier than in the conventional circuits as found in the prior art. Delay tracking capability is also substantially improved.

[0048] Another advantage of locating the DPLL 5 after the FSDC 4 is that the FSDC 4 may use a real adaptive equalizer if a complex adaptive equalizer is unnecessary in particular applications, which is impossible in the conventional circuits of the prior art. This is advantageous because a real adaptive equalizer uses far fewer resources than a complex adaptive equalizer.

[0049] The DPLL 5 may be a second-order or third-order loop, depending on the particular applications, and its initial frequency estimate is assumed to be loaded prior to running the digital phase-locked loop (DPLL). The DPLL phase detector uses a complex multiplier with one complex conjugate input from the rotated FSDC output and another complex input from composite received signal, and an arctangent function. It is possible to provide low-pass filtered or smoothed samples before and/or after the arctangent function. The DPLL lock is used as an indication of the canceller lock.

[0050] The purpose of the AGC 6 is, among other things, to isolate the processing signal level before the slicer from the composite received signal level, so that the adaptive equalizer in the FSDC 4 and DPLL 5 can operate at a selectable, desired level, which is as near full scale as possible. It accomplishes this goal by maintaining the adaptive equalizer gain at a selectable, desired level. It substantially improves the cancellation performance and contributes to the increasing delay tracking capability. In a particular implementation, near full scale is typically at about 70% of full scale, but may be set higher or lower depending upon the needs of particular applications.

[0051] As illustrated in FIG. 3, an implementation of the integer sample delay control (ISDC) 3 comprises two major functional blocks: a delay control 3.1 and a memory device 3.2. While delay control 3.1 can be implemented inside a field programmable gate array (FPGA), digital signal processor (DSP) or general purpose processor, the memory device 3.2 is usually implemented with an external physical memory device such as, but not limited to DDR or DDR2.

[0052] The ISDC 3 delays the interference by integer multiple samples. The initial delay is estimated and loaded. During operation, when it receives Advance (adv) signal from the fractional sample delay control (FSDC), it reduces the delay by one sample. On the other hand, when the ISDC receives Delay (dly) signal from the FSDC 4, it increases the delay by one sample.

[0053] As shown in FIG. 4, the FSDC 4 comprises three major functional blocks. It uses an LMS adaptive equalizer, which is comprised of an LMS FIR block 4.1 and an LMS coefficient update block 4.2, to track delay in a fractional sample (less than one sample). Calculation of coefficient powers' center of mass 4.3 consistently monitors the mass center of the FIR coefficients' power and generates Advance (adv) and Delay (dly) signals to LMS coefficient update block 4.2 and the ISDC 3 to shift the coefficients and interference samples.

[0054] The following derivation shows how the LMS coefficients or weights should be updated with introduction of Mixer 18 and Gain Controller 12. For simplicity of derivation, the delay in Mixer 1, Gain Controller, and Slicer have been omitted.
y_n=W_n−1^TX_n  Equation 1
e_n=d_n−α_ny_ne^jnΩ=d_n−W_n−1^TX_n(α_ne^jnΩ)  Equation 2

[0055] Where α_n is the AGC gain, and X_n and W_n are the input and LMS weight vectors, respectively:
X_n=(x_nx_n−1 . . . x_n−(L−1))^T  Equation 3
W_n=(w_0,nw_1,n . . . w_L−1,n)^T  Equation 4

[0056] L is the number of the LMS taps. Now the input to the complex LMS can be treated as Z_n:
Z_n=X_n(α_ne^jnΩ)  Equation 5
e_n=d_n−α_ny_ne^jnΩ=d_n−W_n−1^TZ_n  Equation 6

[0057] Then the weight update becomes that

[0058] $\begin{array}{cc}{W}_n=W_{n-1}+\mu e_n{Z}_n^{*}=W_{n-1}+\mu {e_n\left(\left({\alpha }_n{e}^{jn\Omega }\right)X_n\right)}^{*}=W_{n-1}+\mu \left({\alpha }_n{e}_n{e}^{-jn\Omega }\right)X_n^{*}& \mathrm{Equation}7\end{array}$

[0059] To simplify implementation and save resource, the LMS weight update can be done with the sign of e_n as long as the adaptation constant μ is smaller enough. Because AGC gain α_n is real and positive, α_n e_n doesn't change the sign of e_n. Therefore,
W_n=W_n−1+μ(α_ne_ne^−jnΩ)X_n*=W_n−1+μ(e_ne^−jnΩ)X_n*=W_n−1+μv_nX_n*  Equation 8

[0060] Where v_n is the input to the FSDC as shown in FIG. 2:
v_n=e_ne^−jnΩ  Equation 9

[0061] The offset center of mass (CoM) of the FIR coefficients' power is calculated as

[0062] $\begin{array}{cc}{\mathrm{CoM}}_n=\frac{\sum _{i=1}^{L-1}i{w_{i,n}}^2}{\sum _{i=0}^{L-1}{w_{i,n}}^2}-\frac{L-1}{2}& \mathrm{Equation}10\end{array}$

[0063] CoM takes values between +/−0.5(L−1). If CoM<0, delay leans towards decreasing. If CoM>0, delay leans toward increasing. When CoM<=−1, Block 4.3 generates Advance and W_n shifts down by one tap. When CoM>=1, it generates Delay and W_n shifts up by one tap.

[0064] In hardware implementation, it is likely that pipeline exists to increase the processing speed. Therefore, pipeline is likely introduced in Mixer 1, Gain Controller and Slicer. The LMS algorithm requires exactly match in sample delay. This is the purpose of Delay Units 1 and 2 as shown in FIG. 2.

[0065] Though the main function of the adaptive equalizer is to track fractional delay (delay less than one sample), the complex adaptive equalizer can also compensate linear distortion in the interference in the composite received signal. However, in applications where the linear distortion is minimal, the compensation may not be necessary. In that case, a real adaptive equalizer can be used instead of a complex adaptive equalizer. The real adaptive equalizer uses only half the multipliers that the complex one of the same impulse response length uses, resulting in saving substantial resources in implementation.

[0066] If the real adaptive equalizer is used, Wn is a real vector and its update is defined as
W_n=W_n−1+μRe(v_nX_n*)  Equation 11

[0067] In summary, the FSDC algorithm is as follows.

[0068] LMS FIR Block:
y_n=W_n−1^TX_n  Equation 12

[0069] Complex LMS Coefficient Update Block:
W_n=W_n−1+μv_nX_n*  Equation 13

[0070] Real LMS Coefficient Update Block:
W_n=W_n−1+μRe(v_nX_n*)  Equation 14

[0071] Advance adv=1, shift down:
W_n=(0w_0,n−1 . . . w_L−2,n−1)^T  Equation 15

[0072] Delay dly=1, shift up:
W_n=(w_1,nw_2,n . . . w_L−1,n0)^T  Equation 16

[0073] The DPLL is a typical digital phase-locked loop having Phase Detector 5.1, Loop Filter 5.2, Complex NCO 5.3, PLL Lock Detection 5.4, and Initial Frequency Estimation 5.5 as shown in FIG. 5. The loop can be the second or third order loop depending on particular applications. In some applications where up and down converters have large frequency drift, the third-order DPLL may be required to operate at low symbol rates.

[0074] One implementation of the phase detector is shown in FIG. 6. The two input d_n and u_n are conjugate-multiplied to generate the phase difference as the phase of c_n:
c_n=d_nu_n*  Equation 17

[0075] The real and imaginary parts of c_n run through two identical low pass filters, respectively, in the Low Pass Filter block 5.1.1. The complex output g_n runs through an arctangent function 5.1.2 to calculate the phase difference q_n between d_n and u_n. q_n can run through another low pass filter 5.1.3 to further smooth the phase difference as output p_n.

[0076] One commonly used PLL lock detection method is to average the absolute value of the phase detector output. When the PLL is locked, the average absolute value of the phase detector output is relatively small and thus, can be used as PLL lock indication when the average absolute value is below a predetermined threshold.

[0077] The AGC as shown in FIG. 7 regulates the level of z_n to match d_n, so that the circuitry before Gain Controller can operate at a level we see as proper and independent of d_n. The AGC accomplishes this by keeping the LMS FIR gain at a desired level we choose.

[0078] The LMS FIR gain calculation 6.1 is defined by Equation 18.

[0079] $\begin{array}{cc}{G}_n=\sum _{i=0}^{L-1}{w}_{i,n}& \mathrm{Equation}18\end{array}$

[0080] The AGC gain α_n is updated by Equation 19 as seen in FIG. 7.
α_n=α_n−1+μ_a(G_n−G_t)  Equation 19

[0081] Where G_t is the target LMS FIR gain 6.2 and μ_a is the AGC constant controlling how sensitive the AGC gain α_n is to the LMS FIR gain change prior to reaching the Integrator 6.3. The AGC constant μ_a should be less than 10% of the LMS adaptation constant μ to avoid disturbance to the LMS adaptation.

[0082] When using a configuration that allows use of a real adaptive equalizer, the LMS equalizer can be configured as switchable between real FIR and complex FIR as shown in FIG. 8 to maximize delay acquisition range with the same amount of resources. During initial acquisition (acquisition mode), the LMS equalizer can be configured as real FIR which has the advantage of long taps to have a larger acquisition range of the signal delay. After acquisition is done, the LMS equalizer switches to complex FIR to track the signal delay and phase (tracking mode).

[0083] As shown in FIG. 9, the present disclosure also provides for methods of interference cancellation that involve a receive decimation filter accepting the composite received baseband signal and generating filtered sampled data at a decimation rate 10. A transmit decimation filter also accepts a digitally converted replica of the interfering signal and generates filtered sampled data at a decimation rate 20. An integer sample delay control (ISDC) provides multiple sample delay control for the replica of an interfering signal and stores an estimated delay value 30. An adaptive filter, such as that found in a fractional sample delay control (FSDC), assists in optimizing cancellation of the interfering signal that is present in the composite received baseband signal 40. A DPLL 60 that that is programmed with a known frequency offset of the interfering signal tracks a phase and frequency of the replica of the interfering signal 50 and an AGC is used to maintain near full scale operation of adaptive filtering and the DPLL 60. An error estimator that is comprised of a mixer, a delay unit, and a slicer then updates the adaptive filter coefficient 70.

[0084] In places where the description above refers to particular implementations of adaptive interference cancellation systems, it should be readily apparent that a number of modifications may be made without departing from the spirit thereof and that these implementations may be applied to other telecommunication systems having adaptive interference cancellation systems.