DC capacitor balancing

[0001] Techniques for balancing voltage across capacitors may be used in several different types of electronic devices including voltage source inverters, multilevel inverters, ultra-capacitors, and capacitor banks. Multilevel inverters provide an output waveform that exhibits multiple steps at several voltage levels. Further, ultra-capacitors may be electrochemical capacitors that may have a relatively high energy density when compared to common capacitors, typically on the order of thousands of times greater than a high capacity electrolytic capacitor. In addition, ultra-capacitors may have a variety of applications, such as in “energy smoothing” and momentary-load devices. Also, ultra-capacitors have applications as energy-storage devices in vehicles as well as home solar systems.

[0002] Other electronic devices that may use voltage balancing techniques for capacitors may be groups of large, specially constructed, low-inductance high-voltage capacitors banks that may used to supply large pulses of current for many pulsed power applications. Such applications may require accumulating energy over a relatively long period of time and releasing it quickly thus increasing the instantaneous power provided to the applications. Pulsed power applications may include electromagnetic Banning, Marx generators, pulsed lasers (especially TEA lasers), pulse forming networks, radar, fusion research, and particle accelerators. Further, large capacitor banks may be used as energy sources for the exploding-bridgewire detonators or slapper detonators in nuclear weapons and other specialty weapons. Also, banks of capacitors may be used as power sources for electromagnetic armor and electromagnetic rail guns and coil guns.

[0003] Voltage source inverters (VSI) are electronic devices that convert direct current (DC) to alternating current (AC). VSIs may be used in various applications such as computer power supplies, uninterrupted power supplies (UPS), High Voltage Direct Current (HVDC) power transmission, and electric vehicles. Further, voltage source inverters may be used in applications that have a DC power source, such as batteries or solar panels. In addition, a VSI may be used in Distribution Static Compensator (DSTATCOM) applications.

[0004] An electronic device such as a VSI, for example, may be constructed in several different configurations. Depending on a configuration, DC voltages across different components of the electronic device may drift from a reference voltage, and thus, may degrade performance. Voltage drift may arise due to minor effects such as capacitor leakage, unequal delays of other devices, presence of DC components in circuit current, etc. Imbalances in voltages across different components within the electronic device may also be present.

[0005] Techniques may be implemented to reduce voltage imbalances across different components (e.g. capacitors) in the electronic device. The components may be controlled to discharge and charge the device components such that voltages across the components are substantially balanced. Sensors may also be coupled to the electronic device to measure voltages to detect a voltage imbalance as well as to measure output currents.

[0006] Within embodiments described below, a device for balancing voltages of capacitors, or charge storage devices, in an electronic circuit is disclosed. The device includes a chopper circuit having a chopper inductor. Further, the chopper circuit may measure or detect the voltages across the capacitors of the electronic circuit as well as an output current of the electronic circuit. In addition, the device may include a chopper control unit receiving the output current and then generating a signal representing charging of the chopper inductor based on the output current. The signal may have a switching frequency and a duty cycle. Also, the chopper control unit may receive the voltages across the capacitors and detect an imbalance between the voltages based on a polarity of the output current. Additionally, the chopper control unit may control a transfer of charge between two or more capacitors, using the chopper inductor and the signal representing charging of the chopper inductor. Further, the chopper inductor is substantially discharged, based on the switching frequency and the duty cycle of the signal, during the transfer of charge between the capacitors.

[0007] In another aspect, the present disclosure includes a method for balancing voltages of capacitors, or charge storage devices, in an electronic circuit. The method may include receiving voltages across two or more capacitors of the electronic circuit as well as an output current of the electronic circuit. The method also includes generating a signal representing charging of a chopper inductor in a chopper circuit based on the output current. The signal may have a switching frequency and a duty cycle. The method further includes detecting an imbalance between the voltages of the capacitors based on a polarity of the output current. In addition, the method includes transferring charge between capacitors (two or more) using the chopper inductor based on the voltage imbalance and the signal representing charging of the chopper inductor. Further, the chopper inductor is substantially discharged based on the switching frequency and the duty cycle during transfer of charge between the capacitors.

[0008] The foregoing summary is illustrative only and is not intended to be in any way limiting. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features will become apparent by reference to the drawings and the following detailed description.

[0019] In the following detailed description, reference is made to the accompanying drawings, which a part hereof. In the drawings, similar symbols typically identify similar components, unless context dictates otherwise. The illustrative embodiments described in the detailed description, drawings, and claims are not meant to be limiting. Other embodiments may be utilized, and other changes may be made, without departing from the spirit or scope of the subject matter presented herein. It will be readily understood that the aspects of the present disclosure, as generally described herein, and illustrated in the Figures, can be arranged, substituted, combined, separated, and designed in a wide variety of different configurations, all of which are explicitly contemplated herein.

[0020] FIG. 1 is an example functional block diagram of a system 100 to balance voltages across the capacitors of an electronic device 140. The system 100 can be used in a variety of applications such that the electronic device 140 may include a multilevel inverter, ultra-capacitors, capacitor banks, and a voltage source inverter. Further, the electronic device 140 may provide an output current i_o. Portions of the output current i_o, namely i_o1 and i_o2, may be placed in feedback with the electronic device 140 or be provided to other system components (e.g. chopper circuit 110), respectively. Further, the electronic device 140 may have capacitors, C₁ and C₂. During operation of the electronic device 140, voltages of V₁ and V₂ of capacitors, C₁ and C₂, respectively, may become imbalanced. For example, due to various deleterious effects (leakage, high DC component of the output current i_o, etc.), capacitor C₁ may be overcharged, and capacitor C₂ may be undercharged, consequently creating a voltage imbalance between capacitors C₁ and C₂.

[0021] A chopper circuit 110 may be used to balance voltages V₁ and V₂ of capacitors, C₁ and C₂, respectively. The chopper circuit 110 may receive the output current, i_o1 as well as be coupled to electronic device 140, a chopper control unit 120 and a chopper pulse generator 130. Also, the chopper circuit 110 may use one or more switches and one or more diodes to balance the voltages of V₁ and V₂ of capacitors, C₁ and C₂, respectively. Further, the chopper circuit 110 may detect or measure the voltages of V₁ and V₂ of capacitors, C₁ and C₂, respectively, and the output current, i_o using Hall effect transducers. Subsequently, the Hall effect transducers may forward V₁, V₂, and i_o, to the chopper control unit 120. After processing the V₁, V₂, and i_o parameters, the chopper control unit 120 calculates output parameters and provides the output parameters to the chopper pulse generator 130. Based on the output parameters, the chopper pulse generator 130 controls the one or more switches within the chopper circuit 110 to balance the voltages of V₁ and V₂ of capacitors, C₁ and C₂, respectively.

[0022] In addition, a computing device 160 may be coupled to the chopper control unit 120. The computing device 160 may receive V₁, V₂, and i_o parameters as well as other input parameters, process the parameters, and provide output parameters to the chopper control unit 120 to assist in balancing the voltages of V₁ and V₂ of capacitors, C₁ and C₂. Alternative embodiments may have the chopper control unit 120 and/or the chopper pulse generator 130 be part of the computing device 160.

[0023] FIG. 2 is an example circuit diagram of an electronic device 200 that uses an example capacitor balancing system in accordance with the present disclosure, in a Distribution Static Compensator (DSTATCOM) application. A voltage source inverter (VSI) converts direct current (DC) to alternating current (AC) and may be used in various applications such as computer power supplies, HVDC power transmission, and electric vehicles as well as any application that has a DC power source, such as batteries or solar panels, that may need to be converted to an AC source.

[0024] However, in FIG. 2, the VSI is part of a DSTATCOM that may act as a shunt active filter that may operate in parallel to the load. Further, i_o1 may be equal to i_o and i_o2, may be equal to zero for perfect compensation. As the load requires reactive power and contains non-linearities, harmonics are generated which may cause deleterious effects such as heating in cables, false tripping of circuit breakers, de-rating of transformers, over sizing of neutral conductors and malfunctioning of sensitive components in the electronic device 200. In order to avoid such deleterious effects, an electronic device 200 may supply a three phase balanced sinusoidal waveform. Therefore, DSTATCOM tries to supply the reactive and harmonic currents required by the load and thereby a source supplies only active current. With the control of inverter power switches (S₁-S₆) two voltage levels (+V_dc and −V_dc) are produced For achieving desired DSTATCOM function, reference currents i_fa*, i_fb*, and i_fc* may be generated such that reactive currents are generated from the shunt active filter (DSTATCOM). Different methods may be used for generating the reference currents such as Instantaneous Symmetrical Component Theory, Instantaneous Reactive Power Theory, Synchronous Reference Frame Theory, and a Frequency Based Approach. The electronic device 200 may use Instantaneous Symmetrical Component Theory for ease of implementation reasons and accuracy of the generated reference currents. Once the three reference currents i_fa*, i_fb*, and i_fc* are generated, the three reference currents, i_fa*, i_fb*, and i_fc* are tracked independently using three legs of the VSI based on a hysteresis current control method. In using the hysteresis current control, a current hysteresis band of (+h,−h) around the reference currents are generated. The VSI operates in such a manner so as to provide output currents, i_fa, i_fb, and i_fc that track the reference currents i_fa*, i_fb*, and i_fc* within the current hysteresis band according to the following:

[0025] $\begin{array}{cc}{\mathrm{error}}_k=\sum _{k=a,b,c}{i}_{{\mathrm{fk}}^{*}}-\sum _{k=a,b,c}{i}_{\mathrm{fk}}\mathrm{If}{\mathrm{error}}_k\ge h\mathrm{then}{u}_k=-1\mathrm{Elseif}{\mathrm{error}}_k\le -h\mathrm{then}{u}_k=1\mathrm{Elseif}h\le {\mathrm{error}}_k\le -h\mathrm{then}\mathrm{No}\mathrm{change}\mathrm{in}{u}_k& \left(1\right)\end{array}$

[0026] where i_fk is the output current of the VSI and i_fk tracks the reference current based on u_k.

[0027] FIG. 3 is an example waveform 300 for an output current of the VSI that tracks a reference current in a Distribution Static Compensator application. The reference current is shown to be substantially in the center of the band bounded by (h,−h). The reference current may be i_fa*, i_fb*, or i_fc*. The VSI output current may be i_fa, i_fb, or i_fc.

[0028] Referring to FIG. 2, the voltage source inverter 210 may be used as the current source for the AC system 220. The DC power source V_DC (e.g. battery) may be connected to the voltage source inverter 210 at input nodes “x” and “y”. DC link or coupling capacitors, C₁ and C₂, of the VSI 210 may hold charge produced by the DC voltage source V_DC. Currents, i₁ and i₂, are produced as capacitors C₁ and C₂ are discharged. Diodes D₁-D₆ and Insulated-gate bipolar transistor (IGBT) switches S₁-S₆ are controlled in such a way to produce currents i_fa, i_fb, and i_fc, through the interface inductors L_fa, L_fb, and L_fc, respectively. In the circuit, R_fa, R_fb and R_fc, represent resistances of the corresponding interface inductors. Further, currents i_fa, i_fb, and i_fc are the currents between nodes a′ and a, b′ and b, and c′ and c, respectively, that are provided to the AC system 220. Currents i_fa, i_fb, and i_fc, are combined with currents i_sa, i_sb, and i_sc generated by model voltage sources v_sa, v_sb, and v_sc of the AC system 220 to produce load currents i_la, i_lb, and i_lc which are combined at node “n”. Consequently, i_o is the output current of the AC system 220 and is the combination of load currents i_la, i_lb, and i_lc. Furthermore, a portion of i_o, namely i_o1, flows from node “n” to node “n′” and is placed in feedback with the voltage source inverter 210. In addition, another portion of i_o, namely i_o2, flows from node “n” to node “N” and is placed in feedback with the AC system 220. Currents i_fa, i_fb, and i_fc, are produced such that load balancing takes place and the current i_o2 will be zero.

[0029] Control and coordination of the VSI switches (S₁-S₆) are based on the reference currents i_fa*, i_fb*, and i_fc* and given by equation (2) below. Further, persons of ordinary skill in the art would understand that a Proportional-Integral (PI) controller (not shown) regulates the total voltage across the two capacitors (V₁+V₂) around a reference value 2V_REF which may be based on V_DC. However, if the output current (i_o) has a DC component, the two capacitors may charge to different voltage levels, though the total voltage across the two capacitors is maintained constant. Hence, a chopper regulation circuit may be used for individual capacitor voltage balancing.

[0030] In addition, the source voltages, v_sa, v_sb, and v_sc, of the AC system 220 are assumed to be balanced and sinusoidal. Further, the load may include three phase unbalanced R-L loads, and a non-linear load similar to a full-wave diode bridge rectifier on the load side. The load currents i_la, i_lb, i_lc are as shown in FIG. 2. The reference currents i_fa*, i_fb*, and i_fc*, are extracted using the instantaneous symmetrical component theory and given as the follows equation.

[0031] $\begin{array}{cc}{i}_{{\mathrm{fa}}^{*}}=i_{\mathrm{la}}-i_{\mathrm{sa}}=i_{\mathrm{la}}-\frac{v_{\mathrm{sa}}+\gamma \left(v_{\mathrm{sb}}-v_{\mathrm{sc}}\right)}{\Delta }\left(P_{\mathrm{lavg}}+P_{\mathrm{loss}}\right)i_{{\mathrm{fb}}^{*}}=i_{\mathrm{lb}}-i_{\mathrm{sb}}=i_{lb}-\frac{v_{\mathrm{sb}}+\gamma \left(v_{\mathrm{sc}}-v_{\mathrm{sa}}\right)}{\Delta }\left(P_{\mathrm{lavg}}+P_{\mathrm{loss}}\right)i_{{\mathrm{fc}}^{*}}=i_{\mathrm{lc}}-i_{\mathrm{sc}}=i_{\mathrm{lc}}-\frac{v_{\mathrm{sc}}+\gamma \left(v_{\mathrm{sa}}-v_{\mathrm{sb}}\right)}{\Delta }\left(P_{\mathrm{lavg}}+P_{\mathrm{loss}}\right)& \left(2\right)\end{array}$

[0032] Where

[0033] $\Delta =\sum _{j=a,b,c}{v}_{\mathrm{sj}}^2$
and γ=tan φ/√{square root over (3)}, φ being a desired power factor angle. For a unity power factor (UPF) operation, γ=0. Equation (2) may be used for any type of load. Persons of ordinary skill in the art would recognize that P_lavg, represents the average or mean power of the load is obtained through a moving average filter. The losses of the VSI 210, (P_loss) are generated using a capacitor voltage PI controller. Consequently, reference currents are then realized using the VSI from equation (1).

[0034] FIG. 4 is an example electronic device 400 that includes a chopper circuit 422 to balance voltages of capacitors of an example application circuit 425. The application circuit may be a voltage source inverter, multilevel inverter as well as devices that include ultra-capacitors, and capacitor banks. The example chopper circuit 422 may include circuit components such as diodes D_P and D_N, switches S_P and S_N, chopper resistor R_CH, chopper inductor L_CH, Hall effect voltage sensors HV1 414 and HV2 418, Hall effect current sensor HC1 432, and a low pass filter 434. In addition, to Hall effect sensors, those skilled in the art would understand that other methods of sensing voltage and current could also be used. The electronic device 400 includes the application circuit 425 that has several circuit components such as capacitors C₁ and C₂, as well other circuit components.

[0035] The chopper circuit 422 may balance the charge between capacitors C₁ and C₂ by controlling the switches S_P and S_N. For example, when capacitor C₁ is detected to be overcharged and capacitor C₂ is detected to be undercharged, switch S_P may be closed. Consequently, charge stored in capacitor C₁ is discharged and current i_CH flows from capacitor, C₁, to chopper inductor, L_CH. Further, chopper inductor L_CH is charged until voltage across capacitor, C₁, is substantially close to a reference voltage based on a DC power source (not shown). Subsequently, switch S_P is opened causing chopper inductor L_CH to discharge and current to flow through diode D_N to capacitor C₂, thereby charging capacitor C₂. When the chopper inductor L_CH is substantially discharged, the voltage across capacitor C₂ may be substantially balanced with the voltage across capacitor C₁. Note that the diodes D_N and D_P function as one-way switches. Thus, persons of ordinary skill in the art would understand that other circuit components that function as one-way switches may be used instead of diodes D_N and D_P.

[0036] Controlling and coordination of switches Sp and S_N are based on voltages V₁ and V₂ across capacitors C₁ and C₂, respectively, and a DC component of AC output current, i_o. Hall effect transducers or sensors HV1 414 and HV2 418 are coupled to the VSI 424 to detect or measure the voltages across capacitors C₁ and C₂. Further, HC1 432 is a Hall effect transducer that detects or measures the AC output current, i_o. In addition, a portion of the output current, i_o, namely, i_o1, is placed in feedback with the VSI 435 at node “n′”. After being detected by Hall effect current transducer HC1 432, i_o, is passed through a low pass filter 434 which provides as an output a DC component of the AC output current, I_OAVG. The values of V₁, V₂, and I_OAVG may be provided as input parameters for a chopper control unit as shown FIG. 5.

[0037] FIG. 5 is a functional block diagram 500 of a chopper circuit 510, chopper control unit 520, chopper pulse generator 540, and a computing device 560 used to balance voltages V₁ and V₂ across capacitors C₁ and C₂ of an application circuit 570. Further, the application circuit 570 may be a voltage source inverter, multilevel inverter as well as devices that include ultra-capacitors, and capacitor banks. The chopper control unit 520 may receive various parameters, such as I_OAVG, V₁, and V₂, from a chopper circuit 510 coupled to the application circuit 570. I_OAVG may be the DC component of an output current for the application circuit 570 (See FIG. 4).

[0038] The chopper control unit 520 may process and provide parameters, f_s and D, to the chopper pulse generator 540. Subsequently, the chopper pulse generator 540 processes the input parameters f_s and D and may provide control signals to chopper circuit 510 to coordinate and control switches S_P and S_N thereby balancing voltages of capacitors C₁ and C₂. A computer or computing device 560 may be coupled to the chopper control unit 520 to provide further control of the chopper control circuit 520 and/or processing of the parameters I_OAVG, V₁, V₂ and f_s and D. Alternatively, the chopper control unit 520 may be a part of a computer or computing device.

[0039] The chopper control unit 520 may process the input parameters V₁, V₂, and I_OAVG in different ways using a digital signal processor and other electronic circuits. I_OAVG may be used by the chopper control unit 520 to generate a signal that represents current, i_CH that charges and discharges an inductor, such as the chopper inductor L_CH of the chopper circuit 510.

[0040] In describing FIGS. 6A-C, reference may be made to components illustrated in FIG. 5. FIG. 6A shows a graph 600 of example triangular carrier waveform. A signal representing a chopper inductor current, i_CH may be generated by the chopper control unit 520 based on the received I_OAVG parameter.

[0041] Further, the signal may be represented by a substantially triangular carrier waveform (also called a carrier signal) because the chopper inductor current, i_CH may have an equal rate of rise and fall based on a voltage V_REF and inductor value of the chopper inductor, L_CH. Analyzing the carrier signal in FIG. 6A, the I_OAVG current may be given by the following equation:

[0042] $\begin{array}{cc}{I}_{\mathrm{oavg}}=\frac{\frac{1}{2}\left(I_{\mathrm{peak}}\right)\left(t_{on}+t_{\mathrm{off}}\right)}{T_s}& \left(3\right)\end{array}$

[0043] where, I_peak, t_on, and t_off, are peak chopper current, on and off time for the chopper switches S_N or S_P, respectively, and T_s is a time period of the carrier signal. Further, switching frequency, f_s, is inverse to the time period, T_s.

[0044] Assuming that t_on=t_off=T_s/2 (or duty cycle D=0.5), the I_OAVG current may be given by:

[0045] $\begin{array}{cc}{I}_{\mathrm{oavg}}=\frac{\frac{1}{2}\left(I_{\mathrm{peak}}\right)\left(2t_{\mathrm{on}}\right)}{T_s}& \left(4\right)\end{array}$

[0046] A duty cycle D=0.5 may be used because in a steady state operation of a chopper circuit 510 because the capacitors C₁ and C₂ of the application circuit 570 fluctuate around a reference value. Thus, any error when compared to a reference voltage would be substantially constant. Simplifying equation (4) reveals:

[0047] $\begin{array}{cc}\frac{I_{\mathrm{oavg}}}{I_{\mathrm{peak}}}=D;D=\frac{t_{\mathrm{on}}}{T_s};T_s=t_{\mathrm{on}}+t_{\mathrm{off}}+t_{\mathrm{rest}}& \left(5\right)\end{array}$

[0048] where t_rest is the period in between the switch S_N or S_P is on or off. Further, based on i_CH,

[0049] $\begin{array}{cc}{I}_{\mathrm{peak}}=\frac{V_{\mathrm{ref}}}{L_{\mathrm{ch}}}{t}_{\mathrm{on}};t_{\mathrm{on}}=\frac{L_{\mathrm{ch}}}{V_{\mathrm{ref}}}{I}_{\mathrm{peak}}& \left(6\right)\end{array}$

[0050] From equation (5), t_on can be expressed as

[0051] $\begin{array}{cc}{t}_{\mathrm{on}}={\mathrm{DT}}_s;f_s\frac{D}{t_{\mathrm{on}}}& \left(7\right)\end{array}$

[0052] Substituting the value of t_on from equation (6) reveals:

[0053] $\begin{array}{cc}{f}_s=\frac{D*V_{\mathrm{ref}}}{I_{\mathrm{peak}}*L_{\mathrm{ch}}}& \left(8\right)\end{array}$

[0054] The switching frequency, fs, provides the frequency of the triangular carrier waveform in FIG. 6A. Note that as I_peak increases, the value of D decreases, from equation (5). This implies that a higher peak current value requires a lower duty cycle, to achieve the same capacitor balancing effect. Further, D from equation (8) is directly proportional to the frequency of the triangular carrier waveform. Therefore as D decreases, t_on decreases, the switching frequency f_s also decreases, and the error increases as the time of operation of the switches S_P and S_N decreases. Voltage error is the difference between a voltage across a capacitor (e.g., C₁) and a reference voltage (V_REF) of a capacitor (e.g., C₁ or C₂) based on a DC power source. There is a trade off between decreasing duty cycle, D, and capacitor voltage error. Values of D between about 0.3 and about 0.5 may be used in such an example chopper control unit to substantially discharge the chopper inductor L_CH of chopper circuit 510 in FIG. 5 when transferring charge between capacitors C₁ and C₂, thereby substantially balancing the voltage across capacitors C₁ and C₂, for example.

[0055] Otherwise, if the chopper inductor, L_CH, is not substantially discharged, then the chopper inductor, L_CH, may be damaged and/or subsequent balancing of the voltages of capacitors C₁ and C₂ in FIG. 5 may be inhibited. For example, if chopper inductor, L_CH, is not substantially discharged in a previous cycle, then the charge already accumulated in the chopper inductor, L_CH, during the previous cycle may be added to the charge which is accumulated in a current cycle. As the charging of chopper inductor, L_CH, continues through subsequent cycles, the accumulated charge in the chopper inductor, L_CH, may continue to increase leading to possibly damaging the chopper inductor, L_CH. A way to prevent damage to the chopper inductor, L_CH, may be to ensure that the charge through the chopper inductor, L_CH, is substantially discharged. In other words the chopper inductor circuit may operate in discontinuous conduction mode, with a duty cycle D less than 0.5, or a t_rest>0.

[0056] From equation (8) the switching frequency, f_s, for a chosen duty cycle, D, is obtained. Further, a substantially triangular carrier waveform is generated representing the charge of chopper inductor L_CH of a chopper circuit 510 and may be used to balance voltages across capacitors C₁ and C₂ as shown in FIG. 5. Specifically, the generated triangular carrier waveform is compared with a calculated error signal, such as for example either V₁-V_ref or V₂-V_REF, where V₁ and V₂ are measured capacitor voltages across C₁ and C₂ that are sensed by Hall effect transducers (See FIG. 4) of the chopper circuit 510, and V_REF is a reference voltage (based on the DC power source), all of which may be inputs to a chopper control unit 520. For example, if I_OAVG received by the chopper control unit 520 (See FIG. 5) has a negative polarity, then capacitor C₁ is overcharged and the positive error signal V₁-V_REF is provided to the chopper control unit 520 and compared with a substantially triangular carrier waveform representing charge of the chopper inductor, L_CH. Conversely, if I_OAVG received by the chopper control unit 520 has a positive polarity, then capacitor C₂ is overcharged and the positive error signal V₂-V_REF is provided to the chopper control unit 520 and compared with the substantially triangular carrier waveform. The comparison of voltage error signal of a capacitor to a substantially triangular carrier waveform representing the charge of the chopper inductor L_CH is further explained in describing FIGS. 6B and 6C.

[0057] An example error signal and the corresponding switching pulses are shown in FIGS. 6B and 6C. The triangular carrier waveform in FIG. 6A represents the current flowing through the chopper inductor, L_CH of chopper circuit 510 in FIG. 5. However, the triangular carrier waveform generated and given to the chopper control unit 520 represents the error signal to the chopper. The error signal in FIG. 6B may be the difference between V₁, the voltage across capacitor, C₁ in FIG. 5 and V_REF, a reference voltage value. At a time instance, t_A, when the error signal is greater than the triangular carrier waveform, capacitor C₁ is overcharged. Consequently, switch S_P is closed, as shown in FIG. 6C, by a chopper control unit 520 such that capacitor C₁ is discharging and the chopper inductor, L_CH, is charging. At another time instance, t_B, when the error signal V₁-V_REF is less than the triangular carrier waveform, capacitor C₁ is discharged to a value substantially close to the reference voltage, V_REF. Hence, the switch S_P is opened (See FIG. 6C) such that the chopper inductor, L_CH is discharged through diode D_N and capacitor C₂ is charged thereby substantially balancing capacitors C₁ and C₂.

[0058] A triangular carrier waveform may be used to substantially discharge a chopper inductor, L_CH, because the triangular carrier waveform is a symmetrical and can be generated by the chopper control unit 520. Further, the triangular carrier waveform may be used such that the frequency of the switch is decided by the frequency of the triangular carrier waveform. As the triangular carrier waveform operates at a higher frequency than the frequency of the application circuit 570, the charging and discharging of the capacitors are faster than the system and hence chopper circuit effect on the system is minimized. Further, Pulse Width Modulation (PWM) is achieved for the switches S_P or S_N. That is, as the error increases, the width of the pulses increase and hence the corresponding switch, Sp or S_N, is operated for more time based on the duty cycle D and peak current I_peak

[0059] The results of comparing the first error signal value and the second error signal value with the substantially triangular carrier waveform as well as the resulting position of switch S_P is summarized in Table 1.

[0060]

	TABLE 1
	Comparison of Error Signal Values with	Position of
	Triangular Carrier Waveform	Switch SP
	First Error Signal Value > Triangular Carrier	Closed
	Waveform
	Second Error Signal Value < Triangular Carrier	Open
	Waveform

Switch S_N of chopper circuit 510 in FIG. 5 operates in the same manner as switch S_P when capacitor C₂ is overcharged and capacitor C₁ is undercharged.

[0061] FIG. 7 is a block diagram illustrating an example computing device 700 that may be used as part of, or in conjunction with, a chopper control unit for balancing voltages across capacitors in an inverter. In a basic configuration 701, computing device 700 typically includes one or more processors 710 and system memory 720. A memory bus 730 can be used for communicating between the processor 710 and the system memory 720. Depending on the desired configuration, processor 710 can be of any type including but not limited to a microprocessor (μP), a microcontroller (μC), a digital signal processor (DSP), or any combination thereof. Processor 710 can include one more levels of caching, such as a level one cache 711 and a level two cache 712, a processor core 713, and registers 714. The processor core 713 can include an arithmetic logic unit (ALU), a floating point unit (FPU), a digital signal processing core (DSP Core), or any combination thereof. A memory controller 715 can also be used with the processor 710, or in some implementations the memory controller 715 can be an internal part of the processor 710.

[0062] Depending on the desired configuration, the system memory 720 can be of any type including but not limited to volatile memory (such as RAM), non-volatile memory (such as ROM, flash memory, etc.) or any combination thereof. System memory 720 typically includes an operating system 721, one or more applications 722, and program data 724. Application 722 includes control input processing algorithm 723 that is arranged to provide inputs to the electronic circuits, in accordance with the present disclosure. Program Data 724 includes control input data 725. In some example embodiments, application 722 can be arranged to operate with program data 724 on an operating system 721 such that power consumption by an electronic circuit is minimized. This described basic configuration is illustrated in FIG. 7 by those components within dashed line 701.

[0063] Computing device 700 can have additional features or functionality, and additional interfaces to facilitate communications between the basic configuration 701 and any required devices and interfaces. For example, a bus/interface controller 740 can be used to facilitate communications between the basic configuration 701 and one or more data storage devices 750 via a storage interface bus 741. The data storage devices 750 can be removable storage devices 751, non-removable storage devices 752, or a combination thereof. Examples of removable storage and non-removable storage devices include magnetic disk devices such as flexible disk drives and hard-disk drives (HDD), optical disk drives such as compact disk (CD) drives or digital versatile disk (DVD) drives, solid state drives (SSD), and tape drives to name a few. Exemplary computer storage media can include volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information, such as computer readable instructions, data structures, program modules, or other data.

[0064] System memory 720, removable storage 751 and non-removable storage 752 are all examples of computer storage media. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by computing device 700. Any such computer storage media can be part of device 700.

[0065] Computing device 700 can also include an interface bus 742 for facilitating communication from various interface devices (e.g., output interfaces, peripheral interfaces, and communication interfaces) to the basic configuration 701 via the bus/interface controller 740. Exemplary output interfaces 760 include a graphics processing unit 761 and an audio processing unit 762, which can be configured to communicate to various external devices such as a display or speakers via one or more A/V ports 763. Exemplary peripheral interfaces 760 include a serial interface controller 771 or a parallel interface controller 772, which can be configured to communicate with external devices such as input devices (e.g., keyboard, mouse, pen, voice input device, touch input device, etc.) or other peripheral devices (e.g., printer, scanner, etc.) via one or more I/O ports 773. An exemplary communication interface 780 includes a network controller 781, which can be arranged to facilitate communications with one or more other computing devices 790 over a network communication via one or more communication ports 782. The Communication connection is one example of a communication media. Communication media may typically be embodied by computer readable instructions, data structures, program modules, or other data in a modulated data signal, such as a carrier wave or other transport mechanism, and includes any information delivery media. A “modulated data signal” can be a signal that has one or more of its characteristics set or changed in such a manner as to encode information in the signal. By way of example, and not limitation, communication media can include wired media such as a wired network or direct-wired connection, and wireless media such as acoustic, radio frequency (RF), infrared (IR) and other wireless media. The term computer readable media as used herein can include both storage media and communication media.

[0066] Computing device 700 can be implemented as a portion of a small-form factor portable (or mobile) electronic device such as a cell phone, a personal data assistant (PDA), a personal media player device, a wireless web-watch device, a personal headset device, an application specific device, or a hybrid device that include any of the above functions. Computing device 700 can also be implemented as a personal computer including both laptop computer and non-laptop computer configurations.

[0067] FIG. 8 and FIG. 9 are flowcharts of example methods (800, 900) for balancing the capacitors in an application circuit, such as a voltage source inverter. The steps in the example methods (800, 900) may be implemented by an electronic device that includes a chopper circuit, chopper control unit, chopper pulse generator, and a computing device. The example methods (800, 900) will be described with reference to components illustrated in FIG. 5.

[0068] With reference to the flowchart of FIG. 8, initially, voltages V₁ and V₂ across capacitors C₁ and C₂ of the application circuit 570 as well as the output current, I_OAVG, are detected by a chopper circuit 510 and are forwarded to and received by a chopper control unit 520, as shown in block 810. The chopper control unit 520 receives the voltages V₁ and V₂ and the current I_OAVG, and a substantially triangular carrier waveform is generated based on the duty cycle D and the peak chopper current I_peak of chopper circuit 510, as shown in block 820. Further, the signal has a switching frequency and a duty cycle based on I_OAVG. Additionally, the chopper control unit 520 detects an imbalance between voltages V₁ and V₂ based on a polarity of I_OAVG, as shown in block 830. For example, if I_OAVG has a negative polarity then there is an imbalance in charge between capacitors C₁ and C₂ such that C₁ is overcharged and C₂ is undercharged. However, if I_OAVG has a positive polarity then there is an imbalance in charge between capacitors C₁ and C₂ such that C₂ is overcharged and C₁ is undercharged, for example.

[0069] In addition, the chopper control unit 520 controls the chopper circuit 510, through a chopper pulse generator 540, to transfer charge between capacitors C₁ and C₂ using the chopper inductor L_CH of the chopper circuit 510 based on the imbalance between voltages V₁ and V₂, as shown in block 840. Charge is transferred such that the chopper inductor, L_CH, is substantially discharged based on the switching frequency and the duty cycle of the signal representing charge of the chopper inductor, L_CH simultaneously charging the capacitor which has lower voltage.

[0070] FIG. 9 is another flowchart of an example method 900 for balancing voltages across capacitors of an application circuit 570 such as a voltage source inverter. Initially, a chopper control unit 520 receives I_OAVG from chopper circuit 510, as shown in block 905. The chopper control unit 520 may then generate a substantially triangular carrier waveform based on the duty cycle D and the peak chopper current I_peak, as shown in block 910. Further, the triangular carrier waveform may have a switching frequency and a duty cycle based on I_OAVG. A chopper control unit 520 receives a voltage across capacitor C₁ of the application circuit 570 at a particular time instance from chopper circuit 510, as shown in block 915. For example, the chopper control unit 520 may receive a voltage, V_1A, across capacitor C₁ of application circuit 570 at a time instance t_A. Further, the chopper control unit 520 generates a first error signal value that may be the difference between voltage V_1A and a reference voltage, as shown in block 920. The reference voltage may be dependent upon a DC power source coupled to the application circuit 570.

[0071] Additionally, the chopper control unit 520 may compare the value of first error signal at time instance t_A with the value of the triangular carrier waveform representing charge of chopper inductor L_CH at time instant t_A, as shown in block 925. If the value of the first error signal is greater than the value of the triangular carrier waveform representing charge of chopper inductor L_CH, then capacitor C₁ is overcharged. Thus, the example method 900 may include a chopper circuit closing switch S_P, as shown in block 930. However, if the value of the first error signal is less than the value of the triangular carrier waveform representing charge of chopper inductor L_CH, then capacitor C₁ is not overcharged and therefore, switch S_P remains open. Next, the example method 900 may include chopper control unit 520 receiving another voltage measurement across capacitor C₁ at a separate time instance 915.

[0072] Closing the switch S_P of chopper circuit 510, as shown in block 930, results in charge (current) to be transferred (flow) from capacitor C₁ of the application circuit 570 to chopper inductor L_CH of the chopper circuit 510, as shown in block 935. The example method 900 may further include the chopper control unit 520 receiving another voltage across capacitor C₁ at a different time instant, as shown in block 940. For example, the chopper control unit 520 may receive voltage V_1B across capacitor C₁ at a time instant t_B. Further, the chopper control unit 520 generates a second error signal value that may be the difference between voltage V_1B and the reference voltage, as shown in block 945.

[0073] Additionally, the chopper control unit 520 may compare the value of second error signal at time instance t_B with the value of the triangular carrier waveform signal representing charge of chopper inductor L_CH at time instant t_B. as shown at block 950. If the value of the second error signal is less than the value of the triangular carrier waveform signal representing charge of chopper inductor L_CH, then capacitor C₁ of the application circuit 570 has been discharged substantially close to the reference voltage. Thus, the example method 900 may include the chopper circuit 510 opening the switch S_P, as shown in block 955. However, if the value of the first error signal is greater than the value of the triangular carrier waveform signal representing charge of chopper inductor L_CH, then capacitor C₁ has not discharged to a value substantially close to the reference voltage. Thus, the example method 900 may include the chopper control unit 520 receiving another voltage measurement across capacitor C₁ at a separate time instance 940. Opening the switch S_P, as shown in block 955, results in charge (current) to be transferred (flow) from chopper inductor L_CH to capacitor C₂, as shown in block 960, through diode D_N of the chopper circuit 510. Further, the chopper inductor L_CH is substantially discharged during the charge transfer between the chopper inductor L_CH and the capacitor C₂,

[0074] In general, it should be understood in the circuits described herein, capacitors can be any suitable charge storage devices, including but not limited to capacitors, ultra-capacitors, capacitor banks. Further, a diode can be any circuit component that can function as a one-way switch. In addition, control circuits can be implemented using DSP, FPGA, ASIC or any other types of circuits. V₁, V₂ and I_0AVG may be measured by Hall effect transducers, or any other suitable measurement techniques or devices. Although VSI application is discussed in detail, the techniques could be used in any capacitor balancing application.

[0075] In general, it should be understood that the circuits described herein may be implemented in hardware using integrated circuit development technologies, or yet via some other methods, or the combination of hardware and software objects that could be ordered, parameterized, and connected in a software environment to implement different functions described herein. For example, the present application may be implemented using a general purpose or dedicated processor running a software application through volatile or non-volatile memory. Also, the hardware objects could communicate using electrical signals, with states of the signals representing different data.

[0076] It should be further understood that this and other arrangements described herein are for purposes of example only. As such, those skilled in the art will appreciate that other arrangements and other elements (e.g. machines, interfaces, functions, orders, and groupings of functions, etc.) can be used instead, and some elements may be omitted altogether according to the desired results. Further, many of the elements that are described are functional entities that may be implemented as discrete or distributed components or in conjunction with other components, in any suitable combination and location.

[0077] It should be further understood that this and other arrangements described herein are for purposes of example only. As such, those skilled in the art will appreciate that other arrangements and other elements (e.g. machines, interfaces, functions, orders, and groupings of functions, etc.) can be used instead, and some elements may be omitted altogether according to the desired results. Further, many of the elements that are described are functional entities that may be implemented as discrete or distributed components or in conjunction with other components, in any suitable combination and location.

[0078] The present disclosure is not to be limited in terms of the particular embodiments described in this application, which are intended as illustrations of various aspects. Many modifications and variations can be made without departing from its spirit and scope, as will be apparent to those skilled in the art. Functionally equivalent methods and apparatuses within the scope of the disclosure, in addition to those enumerated herein, will be apparent to those skilled in the art from the foregoing descriptions. Such modifications and variations are intended to fall within the scope of the appended claims. The present disclosure is to be limited only by the terms of the appended claims, along with the full scope of equivalents to which such claims are entitled. It is to be understood that this disclosure is not limited to particular methods, reagents, compounds compositions, or biological systems, which can, of course, vary. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to be limiting.

[0079] With respect to the use of substantially any plural and/or singular terms herein, those having skill in the art can translate from the plural to the singular and/or from the singular to the plural as is appropriate to the context and/or application. The various singular/plural permutations may be expressly set forth herein for sake of clarity.

[0080] It will be understood by those within the art that, in general, terms used herein, and especially in the appended claims (e.g., bodies of the appended claims) are generally intended as “open” terms (e.g., the term “including” should be interpreted as “including but not limited to,” the term “having” should be interpreted as “having at least,” the term “includes” should be interpreted as “includes but is not limited to,” etc.). It will be further understood by those within the art that if a specific number of an introduced claim recitation is intended, such an intent will be explicitly recited in the claim, and in the absence of such recitation no such intent is present. For example, as an aid to understanding, the following appended claims may contain usage of the introductory phrases “at least one” and “one or more” to introduce claim recitations. However, the use of such phrases should not be construed to imply that the introduction of a claim recitation by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim recitation to embodiments containing only one such recitation, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an” (e.g., “a” and/or “an” should be interpreted to mean “at least one” or “one or more”); the same holds true for the use of definite articles used to introduce claim recitations. In addition, even if a specific number of an introduced claim recitation is explicitly recited, those skilled in the art will recognize that such recitation should be interpreted to mean at least the recited number (e.g., the bare recitation of “two recitations,” without other modifiers, means at least two recitations, or two or more recitations). Furthermore, in those instances where a convention analogous to “at least one of A, B, and C, etc.” is used, in general such a construction is intended in the sense one having skill in the art would understand the convention (e.g., “a system having at least one of A, B, and C” would include but not be limited to systems that have A alone, B alone, C alone, A and B together, A and C together, B and C together, and/or A, B, and C together, etc.). In those instances where a convention analogous to “at least one of A, B, or C, etc.” is used, in general such a construction is intended in the sense one having skill in the art would understand the convention (e.g., “a system having at least one of A, B, or C” would include but not be limited to systems that have A alone, B alone, C alone, A and B together, A and C together, B and C together, and/or A, B, and C together, etc.). It will be further understood by those within the art that virtually any disjunctive word and/or phrase presenting two or more alternative terms, whether in the description, claims, or drawings, should be understood to contemplate the possibilities of including one of the terms, either of the terms, or both terms. For example, the phrase “A or B” will be understood to include the possibilities of “A” or “B” or “A and B.”

[0081] In addition, where features or aspects of the disclosure are described in terms of Markush groups, those skilled in the art will recognize that the disclosure is also thereby described in terms of any individual member or subgroup of members of the Markush group.

[0082] As will be understood by one skilled in the art, for any and all purposes, such as in terms of providing a written description, all ranges disclosed herein also encompass any and all possible subranges and combinations of subranges thereof. Any listed range can be easily recognized as sufficiently describing and enabling the same range being broken down into at least equal halves, thirds, quarters, fifths, tenths, etc. As a non-limiting example, each range discussed herein can be readily broken down into a lower third, middle third and upper third, etc. As will also be understood by one skilled in the art all language such as “up to,” “at least,” “greater than,” “less than,” and the like include the number recited and refer to ranges which can be subsequently broken down into subranges as discussed above. Finally, as will be understood by one skilled in the art, a range includes each individual member. Thus, for example, a group having 1-3 cells refers to groups having 1, 2, or 3 cells. Similarly, a group having 1-5 cells refers to groups having 1, 2, 3, 4, or 5 cells, and so forth.

[0083] While various aspects and embodiments have been disclosed herein, other aspects and embodiments will be apparent to those skilled in the art. The various aspects and embodiments disclosed herein are for purposes of illustration and are not intended to be limiting, with the true scope and spirit being indicated by the following claims.