Digital compensator for power supply applications

[0001] The present application claims priority to U.S. Provisional Application No. 61/116,874 filed Nov. 21, 2008 entitled DIGITAL COMPENSATOR FOR POWER SUPPLY APPLICATIONS, which is incorporated herein in its entirety by reference.

[0002] These teachings relates generally to control of power supplies and similar devices.

[0003] Power supplies and in particular buck regulators are an important parts of today's technology. These devices consist of mainly two main parts, the power electronics and the controller. The controller functions to operate the power electronics in a manner that satisfies the system requirements of the load. Both the power electronics section and the controller need to be designed to meet the demanding objectives of the electrical specifications and cost. Due to the reduction in cost of digital electronics as popularized by Moore's law, a recent trend is the use of digital electronics for the controller.

[0004] Key desired features of an effective controller are: fast settling time, low DC error, adjustable output impedance, current limit, and stability.

[0005] There is a need for a high performance digital compensator controller with the above listed desired features.

[0006] Digital compensators are typically implemented as a PID or PID with additional filtering. These are typically digital implementations of older analog designs.

[0007] There are three common methods used for current sensing. The first method measures the voltage drop across one or more of the power FETs and uses the on resistance of power FET to calculate inductor current. This method has significant limitations. First, the on resistance of the power FET has a large tolerance and as temperature dependence. Second voltage across the FETs are very small and is difficult to measure accurately.

[0008] FIG. 2 illustrates the second method of a sense resistor in series with the inductor. The voltage across sense resistor is measured and the current is then determined. The limitation with this method is the requirement for an external power resistor in series with the inductor. This resistor lowers the supply efficiency and increases cost. To improve efficiency, the resistor value can be lowered, but this complicates measurements due to noise.

[0009] As shown in FIG. 3, the third method uses an external RC network to model the inductor and its series equivalent resistance, Rdc. One difficulty of this method is that the series resistance of the inductor is temperature dependent and may be unknown. In addition, other practical limitations occur due to the fast switching of the FET outputs and its noise.

[0010] All of the above methods suffer from noise sensitivity and, in two of the cases, parameter uncertainty. Also, what is desired for compensation is not the actual inductor current but the inductor current average over one PWM cycle. In continuous conduction, inductor current has a triangular like waveform due to the pulse width modulated drive signal from the power FETs. None of these methods provide the actual average inductor current.

[0011] There is a need for a method that reduces component cost, reduces noise sensitivity, is parametric stable and provides the average inductor current over one PWM cycle.

[0012] In one embodiment, the system of these teachings includes a mixed signal state estimator, and average inductor current estimator, and duty cycle calculation. In one instance, the average inductor estimator includes utilizing the average switch voltage and the average output voltage to obtain the estimate of the average inductor current. In another instance, measurements are utilized to adjust the estimate. In one embodiment in which measurements are utilized to adjust the estimate, low pass filters with predetermined pole locations are used to correct aliasing problems.

[0013] In one embodiment, the mixed-signal state estimator includes both a high dynamic range DAC and a low dynamic range ADC. Other embodiments of the mixed-signal state estimator and also disclosed.

[0014] Embodiments of the duty cycle calculation are also disclosed.

[0015] For a better understanding of the present teachings, together with other and further needs thereof, reference is made to the accompanying drawings and detailed description and its scope will be pointed out in the appended claims.

[0028] FIG. 1 shows a block diagram of an embodiment of the present teachings. This embodiment includes a mixed signal state estimator, inductor current estimator, and duty cycle calculation. Referring to FIG. 1, shown therein is a switching power supply including a circuit having two or more reactive components 10, 15 configured to provide output voltage, where one of the two or more reactive components is an inductor, a switching component 20 switching the circuit between two or more switching states, the two are more switching states including one output state and another voltage state, a pulse width modulator

[0029] 25 and a controller 30. The pulse width modulator 25 receives the duty cycle and dives the switching component 20 in order to cause switching between two of the two or more switching states. The controller 30 includes an inductor current estimator 35 providing an inductor current estimate, where inductor current is not measured directly, a state estimator 40 receiving the inductor current estimate on providing an estimate of the system states, where the state estimator includes both analog and digital components (also referred to as a mixed signal state estimator) and a duty cycle determination component 45 (also referred to as a duty cycle calculation component) receiving the estimate of the system states and the inductor current estimate and providing a duty cycle to the pulse width modulator 25. Also shown in FIG. 1, is a computer usable medium 50 having computer readable code that causes the processor 55 to execute operations needed in the performance of the functions of the current estimators 35, the mixed-signal state estimator 40 and the duty cycle calculation 45.

[0030] The embodiment shown in FIG. 1 uses a buck converter topology. However the methods of these teachings are applicable to any generic converter of buck, boost, or buck-boost, forward, fly-back, SEPIC, cuk, etc type.

[0031] As shown in FIG. 1, the embodiment shown therein is the combination of the three parts working together to achieve the desired digital compensator. These parts are: average inductor current estimator, mixed signal state estimator and duty cycle calculator.

[0032] Average Inductor Current Estimator

[0033] In one embodiment of the average inductor current estimator, the average switch voltage combined with the average voltage across the inductor are utilized to obtain the average inductor current. In the typical digital power supply application, the output voltage and supply voltage are digitized by analog to digital converters.

[0034] One embodiment of a switching power supply including an inductor current predictor component is shown in FIGS. 4a and 4b (other components of the controller are not shown). Referring to FIG. 4a, an analog to digital converter (ADC) 60 digitizes the output voltage across the capacitor 15. The digitized output voltages provided to the inductor current predictor component 70. Another ADC 65 is shown digitizing the input voltage Vdd. Average values of the output voltage and the switch voltage (sw) can be obtained by conventional means for a running average

[0035] $\left(\frac{1}{N}\sum _{j=i}^{j=i+N}{x}_j\right).$
(In other embodiments, analog circuits can be used for averaging before the ADC or other conventional definitions of a running average can be used. See, for example, Watts, D., Practical averaging circuits, IEEE Transactions on Automatic Control, Volume 10, Issue 3, Date: July 1965, Pages: 363-364, for analog means, and Sanders, S. R.; Noworolski, J. M.; Liu, X. Z.; Verghese, G. C., Generalized averaging method for power conversion circuits, IEEE Transactions on Power Electronics, Volume 6, Issue 2, Date: April 1991, Pages: 251-259, for other discrete implementation approaches, both of which are incorporated by reference herein in their entirety.) Referring to FIG. 4b, in which a more detailed embodiments of the inductor current predictor is shown, the switch voltage is digitized by an ADC 75. (In other embodiments, the average switch voltage can be obtained recursively. That is, once the duty cycle calculation is performed, the average switch voltage is given by the input voltage-Vdd-multiplied by the duty cycle. In those embodiments, the ADC 75 and the averaging component 80 in FIG. 4b are omitted.) The digitized switch voltage (in embodiments where the average switch voltage is measured) and the digitized output voltage are provided to two averaging components 80, 85 (it should be noted that the averaging components could be implemented using computer usable memory 50 and processor 55 in FIG. 1). The averaged switch voltage and the averaged output voltage are provided to an inductor current estimate generator 90, which provides the inductor current estimate.

[0036] The derivation of the average inductor current model is as follows:

[0037] The equation for the instantaneous inductor current is:

[0038] $L\frac{di\left(t\right)}{dt}=\mathrm{sw}\left(t\right)-\mathrm{Ri}\left(t\right)-\mathrm{vout}\left(t\right)$
When averaged over a PWM cycle, this reduces to:

[0039] $L\frac{1}{T}\frac{d}{dt}{\int }_0^{T}i\left(t\right)dt=\frac{1}{T}{\int }_0^T\mathrm{sw}\left(t\right)dt-R\frac{1}{T}{\int }_0^{T}i\left(t\right)dt-\frac{1}{T}{\int }_0^T\mathrm{vout}\left(t\right)dt$

[0040] Using the definition of averaging over one period, this simplifies to:

[0041] $L\frac{d\mathrm{avgi}\left(t\right)}{dt}=\mathrm{avgsw}\left(t\right)-\mathrm{Ravgi}\left(t\right)-\mathrm{vest}\left(t\right)$
where:

• • [0042] avgi is the average inductor current
  • [0043] avgsw is the average switch voltage
  • [0044] vest Is the average output voltage as measured or estimated
  • [0045] L, R are the inductor inductance and power stage DC resistance

[0046] These differential equations may be simplified to a discreet time equation of the form:
avgi(n+1)=Aext avgi(n)+Bext(avgsw(n)−vest(n))
where Aext and Bext may be computed using standard zero order hold discrete time approximations. For example, but not limited to, the c2d( ) function in Mathworks Matlab. Other approximations can be obtained using the methods outlined in Franklin and Powell (Franklin, Powell, Workman, Digital Control of Dynamic Systems, chapter 6, ISBN 0-201-8204-4) or other conventional methods.

[0047] In many instances, the L/R time constant of the inductor is much longer than the sample rate. In this case Aest & Best can be approximated by:
Best=T/L
Aest=1−RT/L

[0048] The block diagram for an embodiment of the current estimator is shown in FIG. 5. Referring to FIG. 5, the current estimator shown therein includes a subtraction component 105 receiving the average of the switch voltage and the average of the output voltage, a first multiplying component 110 receiving an output of the subtraction component and multiplying the output of the subtraction component by a first model parameter, a second multiplying component 160 multiplying an input to the second multiplier component by a second model parameter, an adding component 120 receiving an output of the first multiplying component and an output of the second multiplying component and a delay component 125 receiving an output of the adding component, an input to the second multiplier 160 being an output of the delay component 125.

[0049] Combined Method

[0050] Sometimes the inductor model is not accurately known. In this case it is necessary to optimize or adapt the inductor model to match measurements. To achieve this, measurements of the inductor current are utilized. In the method of these teachings, inductor voltage is measured rather than inductor current, which is a measured quantity in the conventional methods.

[0051] Referring to FIGS. 6a and 6b, the external (measured) inductor voltage is filtered by a simple low-pass filter 170 with a known pole to correct for aliasing problems. The resulting filtered voltage is digitized by an ADC 175 and filtered by a pole and zero digital filter 130. The zero is adjusted to compensate for the external anti-aliasing filter and the pole is adjusted to match inductor time constant. The DC gain of the filter is adjusted to compensate for the temperature dependents of the inductor DC resistance. The output of the pole-zero filter 130, after multiplying by the filter gain (using multiplier 135) is the measured inductor current.

[0052] This external current measurement is compared against the internal current estimate and adjustments to the model coefficients (Aest, Best) to match each other and minimize the internal current estimations error. The combination method provides for the excellent noise performance of the internal model with the DC accuracy of the external model. One method for implementing these adjustments is the LMS algorithm. This adjustment strategy can be seen in FIG. 6a. Referring to FIG. 6a, a comparison component 140 compares the predicted inductor current and the measured inductor current and an adjustment component 145, 165 receives an output of the comparison component 140 and providing adjusted values for parameters of the discrete time representation of the circuit equation for inductor current. The estimated inductor current is obtained by subtracting, utilizing a subtraction component 105, the average of the switch voltage and the average of the output voltage. Adjusted values of a first and second model parameters are obtained from the adjustment component 145, 165. The predicted inductor current is obtained by a sum (obtained from adding component 120) of a product (obtained from multiplying component 155) of the first model parameter (after adjustment) times an output of the subtraction component plus a product of the second model parameter (after adjustment) and a delayed value (obtained from delay component 125) of a previously predicted inductor current. (Delay component 150 is utilized the adjustment process.) In the embodiment shown in FIG. 6a, the adjustments are performed utilizing the LMS method and the difference between the estimated and measured inductor current is multiplied by an LMS gain (by a multiplier 145).

[0053] The equations for the combined method are:
imeas(n+1)=Kfilt(filtn1iext(n+1)+filtn2iext(n)−filtd imeas(n))
iest(n+1)=Aest(n)iest(n)+Best(n)(avgsw(n)−vest(n))
Aest(n+1)=Aest(n)+LMSgain(imeas(n+1)−iest(n+1))
Best(n+1)=Best(n)+LMSgain(imeas(n+1)iest(n+1))
where:

• • [0054] Kfilt is the external sense gain
  • [0055] filtn1, filtn2, filtd are pole zero filter gains
  • [0056] Aest, Best are current model parameters
  • [0057] LMSgain is the LMS algorithm adaptation gain
  • [0058] iext in the ADC output from the inductor voltage anti-aliasing filter
  • [0059] imeas is the measured inductor current
  • [0060] iest is the estimated inductor current

[0061] Mixed Signal State Estimator

[0062] The mixed signal state estimator allows high accuracy estimation of plant (external component) state variables with a low performance ADC. Classic (conventional) designs use an ADC to measure the plant outputs and implement the state estimator in either logic or software. This method requires an ADC with both high dynamic range and high resolution. The mixed signal estimator uses a high dynamic range DAC and a low dynamic range ADC. The ADC digitizes only the output error which has significantly lower dynamic range. This saves both cost & power. FIG. 7 shows the mixed signal estimator with load current feedforward added. Referring to FIG. 7, the embodiment shown therein includes a high dynamic range digital to analog converter (DAC) 205 receiving an estimated output voltage, the estimated output voltage being obtained by multiplying, utilizing multiplier 210, an estimated state vector by an output matrix. An analog subtraction component 215 subtracts an output of the high dynamic range DAC 205 from a measured output voltage. A first delay component 225 receives the estimated output voltage and an addition component 230 receives an output of the ADC 220 and an output of the first delay component 225. A subtraction component 235 receives an output of the addition component 230 and the estimated output voltage; an output of the subtraction component is the voltage error, the voltage error being utilized in obtaining the estimated state vector. A first multiplier 240 receives the voltage error and multiplies the voltage error by an output error feedback matrix. A second multiplier 245 receives a predetermined/previously obtained feedback signal and multiplies the feedback signal by an input matrix. A third multiplier 260 receives an output of a second delay component 250. Another addition component 255 receives outputs of the first, second and third multiplier and provides a sum of received quantities. The sum of the received quantities is provided to the second delay component 250 and represents the estimated state. In one embodiment, also shown in FIG. 7, the state estimator also includes load current feedforward. In the embodiment including load current feedforward, the state estimator also includes a low resolution ADC 265 receiving a load current signal, a fourth multiplier 270 receiving an output of the low resolution ADC 265, the fourth multiplier 270 multiplies the output of the low resolution ADC 265 by a feedforward matrix. An output of the fourth multiplier 270 is received by the other addition component 255.

[0063] The Equations for the embodiment shown in FIG. 7 are:
state(n+1)=Ad state(n)+Bd feedback(n)+Ed iload(n)+Le error(n)
error(n)=vout(n)−Cd state(n)
where:

[0064] Ad is state transition matrix

[0065] Bd is input matrix

[0066] Cd is output matrix

[0067] Ed is the optional feedforward matrix

[0068] Le is output error feedback matrix

(It should be noted that, in the above equation, the terms state transition matrix, input matrix, output matrix, output error feedback matrix and feedforward matrix are used in the sense of “modern”-circa 1960-control theory.

[0069] Mixed Signal:
adc(n)=vout(nTs)−dac(nTs)
Subtraction is done in the analog domain
dac(nTs)=Cd state(n−1)
DAC has a one sample delay to allow for settling
error(n)=adc(n)−Cd state(n)+Cd state(n−1)
The error term has correction for single cycle DAC delay. This lower DAC/ADC requirements.

[0070] For low estimation error, the requirements for the ADC are high resolution and low offset. The gain is less critical. The DAC has to have a dynamic range that is larger then the output voltage range. This allows the state estimator to follow any output voltage and, thus, allow for closed loop operation. This is an advantage for start up, shut down, and current limit. If the control loop dynamics are not demanding, the estimator bandwidth may be lowered. This in turn lowers the resolution requirement. In the case where the estimator sampling rate is very high and the output voltage feedback loop is slow, the ADC can be only 1 bit, a comparator. When the estimator has to be very fast and the control disturbances are very large, such as in the case of point of load regulators, a multi-resolution ADC can be used. This ADC increases the dynamic range while providing low error. FIG. 8 shows the multi-resolution ADC concept.

[0071] This ADC can be simply made out of two or more low bit count, low cost ADCs. This embodiment can be seen in FIG. 9. Referring to FIG. 9, the embodiment shown therein includes a low dynamic range, high resolution ADC 290 and a high dynamic range low resolution ADC 275; the low dynamic range high resolution ADC 290 and said high dynamic range low resolution ADC 275 having a same input. A saturation component 280, having a same dynamic range as said low dynamic range, high resolution ADC 290, receives an output of the high low dynamic range, low resolution ADC 275 and a subtraction component 285 provides a difference between an output of the high dynamic range low resolution ADC 275 and an output of the saturation component 280. An addition component to 95 receives an output of the subtraction component 285 and an output of the low dynamic range high resolution ADC 290; an output of the addition component 295 is an output of the multiresolution ADC.

[0072] Predictive Duty Cycle Current Limit

[0073] Current limit is implemented by calculating the maximum duty cycle that can be allowed such that the predicted average for the next control cycle is less than or equal to maximum allowed current. The equations for the maximum allowed next duty cycle is:
swmax(n+1)=vest(n)+ILmit(R+L/Ts)−(L/Ts)iest(n)
where:

[0074] swmax is the maximum allowed next average switch voltage

[0075] vest is the estimated or measured output voltage

[0076] ILmit is the maximum allowed average inductor current

[0077] L is the power stage inductance

[0078] R is the power stage total resistance

[0079] Ts is the sample rate

[0080] iest is the average inductor current estimate

[0081] An embodiment of a system providing current limit can be seen in FIG. 10.

[0082] The controlled output resistance is achieved by Kdroop. This gain subtracts (or adds) from the normal, feedback control to make the DC resistance the desired value. For example, if the feedback states are the output capacitor voltage (vcap) and the output capacitor current (icap), the output resistance is just:
Rout=Kdroop/Kfb₁
where Kfb is the state feedback gain matrix. Kfb₂ and Kdroop are the current feedback terms and they control the feedback loop damping.

[0083] Power Electronics Resistance Canceller

[0084] Instead of requiring integral control to minimize error, the DC error correction provides for the extra duty cycle needed to remove the power stage voltage drop. This is done by setting Kcancel equal to the total power stage resistance.

[0085] With fixed average current estimator
Kcancel=R

[0086] With adaptive average current estimator
Kcancel=(1−Aest(n))/Best(n)

[0087] Final duty cycle calculation for the case when the states are vcap & icap and the duty cycle is not saturated by either the current limit or the duty cycle saturations.
duty(n+1)=(Kfb₁(vcap(n)−Vref)−Kfb₂icap(n)−(Kdroop+Kcancel)iest(n))/Vdd
where:

[0088] Vdd is the power stage input voltage

[0089] Vref is the desired output voltage

[0090] Kfb, Kdroop, Kcancel are gains

[0091] vcap and icap are states

[0092] iest is estimation inductor current

[0093] duty is the duty cycle (fractional)

[0094] An embodiment of the duty cycle determination system is shown in FIG. 10. Referring to FIG. 10, the embodiment shown therein includes a first multiplier 305 receiving and inductor current estimate and multiplying the inductor current estimate by a first gain (Kdroop), a subtraction component 310 receiving a capacitor voltage, which is one state in a state vector, and a predetermined voltage reference value and providing a difference between the capacitor voltage and the predetermined voltage reference value, a second multiplier 315 receiving state vector elements other than capacitor voltage and an output of said another subtraction component and multiplying said received state vector elements and said output of said another subtraction component by a second gain vector (Kfb) and a first combining component 320 receiving an output of the first multiplier 305 and an output of the second multiplier 315; the first combining component 320 providing a negative of a sum of the output of the first multiplier 305 and the output of the second multiplier 315. In the embodiment shown in FIG. 10, the components implementing the effect of the current limit on the duty cycle (and on the average switch voltage) include a third multiplier 325 receiving the inductor current estimate and multiplying the inductor current estimate by a power stage inductance divided by a sample rate and a second combining component 330 receiving an output of the third multiplier 325, a measurer/estimated output voltage and a product of a maximum allowed average inductor current (also referred to as the current limit) times a sum of a power stage total resistance and the power stage inductance divided by the sample rate. The second combining component 330 provides a difference between a sum of the output of the third multiplier 325 and the measures/estimated output voltage and the product of the current limit times the sum of the power stage total resistance and the power stage inductance divided by the sample rate; an output of the second combining component 330 being a maximum allowed average switched voltage at a next sampling time.

[0095] The embodiment shown in FIG. 10 also includes a first saturation component 335 receiving an output of the first combining component 320, the first saturation component 335 restricting the output of the first combining component 320 and a minimum selecting component 340 receiving an output of the first saturation component 335 and the output of the second combining component 330, the minimum selecting component 340 providing a smallest of the output of the first saturation component 335 and the output of the second combining component 330.

[0096] In the embodiment shown in FIG. 10, the DC error correction is implemented by a fourth multiplier 345 receiving the inductor current estimate and multiplying the inductor current estimate by a fourth gain (Kcancel) and another addition component 350 receiving an output of the minimum selecting component 340 and an output of the fourth multiplier 345 and providing a sum of the output of the minimum selecting component 340 and the output of the fourth multiplier 345. The sum of the output of the minimum selecting component 340 and the output of the fourth multiplier 345 is provided to a second saturation component 355, the output of the second saturation component being the average switch voltage. A reciprocal component 360 receives a power stage input voltage and provides an inverse of the power stage input voltage as output. A multiplying component 365 multiplies an output of the reciprocal component 360 and an output of second saturation component 355, an output of the multiplying component 365 being the duty cycle. If the first and second saturation components 335, 355 and the minimum selecting component 340 are omitted from FIG. 10, the resulting figure shows and embodiment that provides a duty cycle determination according to the equation hereinabove. The feedback signal utilized in the state estimation is obtained from the output of the minimum selecting component 340.

[0097] Complete Digital Compensator

[0098] An embodiment of the complete digital compensator in shown in FIG. 11. Referring to FIG. 11, a state estimator component 370 receives as inputs load current values and output voltage values and a feedback signal (obtained from a duty cycle determination/feedback gain component 380) and provides as output a measured or estimated average output voltage (labeled vest) and state values. A current estimating component 375 receives as inputs a measured inductor voltage (labeled iext), the measured or estimated average output voltage obtained from the state estimator component 370 and an average switch voltage (obtained from the duty cycle determination/feedback gain component 380) and provides as output an average inductor current estimate (labeled lest). The duty cycle determination/feedback gain component receives as inputs the average output voltage (vest) and the state from the state estimator component 370 and the average inductor current estimate from the current estimating component 375 and provides as output a duty cycle, the feedback signal and the average switch voltage. The duty cycle signal is provided to the PWM (25, FIG. 1).

[0099] Examples of Operation

[0100] Exemplary embodiments are shown below. It should be noted that these teachings are not limited to the exemplary embodiments.

[0101] The simulations were performed using Matlab/Simulink with a complete model of a closed loop single phase buck converter.

[0102] FIGS. 12 and 13 shows an exemplary embodiment of the average current estimator operating. FIG. 12 is a Matlab/Simulink simulation and FIG. 13 is laboratory measurements made on operating hardware. Note the noise problem with the prior art RC filter inductor measurement method.

[0103] Current Limit

[0104] The duty cycle predictive current limit is shown in FIG. 14.

[0105] DC Error Canceling

[0106] The DC error canceling can be seen in FIGS. 15 and 16. Note the large output voltage error without DC error canceling.

[0107] Combined Current Estimator

[0108] FIG. 17 shows the adaptive current estimator converging.

[0109] FIG. 18 shows that the adaptive current estimator converged.

[0110] Although these teachings has been described with respect to various embodiments, it should be realized these teachings are also capable of a wide variety of further and other embodiments within the spirit and scope of the appended claims.