Switching mode power supply with burst mode and associated methods of control

[0001] The present application claims priority from Chinese Application No. 200910306434.3, filed Sep. 1, 2009, the disclosure of which is incorporated herein by reference in its entirety.

[0002] The present technology generally relates to a switching mode power supply with a burst-mode function, and to a control circuit that implements the burst-mode function.

[0003] Nowadays, switch mode power supply (“SMPS”) is becoming widely used for electronic devices. The semiconductor switch in the SMPS is turned on and turned off periodically to supply energy to a load with switching frequency generally over ten KHz. SMPS can be smaller, lighter and more efficient compared to a conventional linear power supply.

[0004] There are many circuit topologies for SMPS, such as buck, boost for the non-isolated type and half-bridge, flyback for the isolated type. Taking a SMPS based on flyback topology as an example, it has the following functional modules: an energy input module, an energy couple module, an energy output module, a feedback module and a controlling module. An alternative current (“AC”) voltage is input through the energy input module and transformed into a smooth direct current (“DC”) voltage, which is further transformed into a high frequency signal through periodically turning on and turning off the switch based on a feedback signal. The high frequency signal is coupled by a transformer and a steady DC voltage is output through the output module.

[0005] Besides normal operating mode, electronic devices can also operate under a reduced load or standby mode (generally referred to as “light load”). Under light load conditions, the load needs very low power output from the power supply. If the controlling module still uses the original frequency to drive the switch, the loss on the switch becomes significant and the efficiency becomes low. One solution is decreasing the frequency to a lower level. However, from an efficiency point of view, the light load condition requires switch frequencies below 20 KHz. Thus, the frequency is in the audible frequency range to cause noise issues.

[0006] Another solution is adopting a burst-mode function, which alternately modulates the switch based on a high frequency signal within a period of time (labeled with Mon), and in another period of time (labeled with Moff) the switch is kept off. Thus, the equivalent switching frequency is decreased to reduce the switching loss. However, the period of time Mon and Moff is typically automatically adjusted according to the power supplied to the load, which may cause the value of Mon and Moff to be uncertain, resulting in noise issues.

[0014] The present disclosure describes switch mode power supplies and associated methods of control. It will be appreciated that several of the details set forth below are provided to describe the following embodiments in a manner sufficient to enable a person skilled in the relevant art to make and use the disclosed embodiments. Several of the details and advantages described below, however, may not be necessary to practice certain embodiments of the invention. Additionally, the invention can include other embodiments that are within the scope of the claims but are not described in detail with respect to FIGS. 1-7.

[0015] FIG. 1 is a schematic circuit diagram of a power supply based on flyback topology according to several embodiments of the technology. It should be noted that several embodiments of the control method are also applicable to other topologies such as buck, boost for the non-isolated type and half-bridge, flyback for the isolated type, and/or other types of power supply.

[0016] In the illustrated embodiment, an input voltage Vin is regulated to supply power to a load. The input voltage Vin is coupled to the primary side of a transformer T1, and further coupled to the secondary side of the transformer T1 by periodically turning on and turning off a switch S1. The switch S1 is controlled by a signal 101. The voltage on the secondary side of the transformer T1 is rectified by a diode D1 and further filtered by a capacitor C1 to generate a constant signal Uo, which can be a voltage signal Vo or a current signal Io.

[0017] A control circuit module 105 has one input that is a switch current detecting signal 102, and another input that is a feedback signal 104. The current Is1 flowing through the switch S1 may be detected, for example, through detecting the voltage across a resistor and/or other suitable techniques. The feedback network 103 samples the constant signal Uo and outputs the feedback signal 104. The control circuit module 105 is responsive to the feedback signal 104 and the switch current detecting signal 102, outputting a signal 101 to turn on and turn off the switch S1. The control circuit module 105 can be made on an integrated circuit, on discrete components, or a combination of IC and some discrete components. The feedback signal 104 can be any type of signal which can reflect the status of a load, such as a voltage signal, a current signal, or a power signal. In one embodiment, the switch S1 is a MOSFET, Uo is a voltage signal Vo and the feedback signal 104 is a voltage signal. In other embodiments, the switch S1 can also include a JFET, a diode, and/or other suitable types of switching devices.

[0018] The switch of a SMPS may be driven based on a conventional pulse width modulation (“PWM”) control mode with fixed frequency pulse, which can be voltage mode or current mode, or a fixed on-time variable off-time control mode, or a quasi-resonant control mode. The pulse frequency for driving the switch is variable for the fixed on-time variable off-time control mode and the quasi-resonant control mode. For the PWM control mode, the output is regulated through controlling the time during which the switch is on (on time). For the fixed on-time variable off-time control mode, the on-time of the switch is constant, while the time during which the switch is off (off time) is controlled. For the quasi-resonant control mode, the on-time of the switch is controlled as that for the PWM control mode, and the switch is turned on when the voltage across the switch decreases to a minimum value.

[0019] FIG. 2 is a flow chart of a method of control according to the technology. In stage 202, the output power of a SMPS is detected. Then, a feedback signal based on the value of the output power is generated in stage 203. For a PWM control mode or a quasi-resonant control mode, the value of the feedback signal determines the value of on-time of the switch; for a fixed on-time variable off-time control mode, the value of the feedback signal determines the value of the driving signal frequency for the switch. In stage 204, the feedback signal is compared with a threshold signal. For a PWM control mode or a quasi-resonant control mode, the value of the threshold signal is related to the on-time of the switch. In one embodiment, the value of the threshold signal is set to be a value that the on-time of the switch, corresponding to the threshold signal, is 25% of the on-time value for the full load. For a fixed on-time variable off-time control mode, the value of the threshold signal is related to the value of the driving signal frequency for the switch. In one embodiment, the value of the threshold signal is set to be such a value that the frequency value, corresponding to the threshold signal, is 20% of the frequency value for the full load. In other embodiments, the threshold signal may have other suitable values.

[0020] If the comparison result in stage 204 indicates that the output power is higher than the threshold power, the process proceeds to stage 205, in which the SMPS operates under a normal load condition with a conventional PWM control mode, a quasi-resonant control mode, or a fixed on-time variable off-time control mode. If the comparison result in stage 204 indicates that the output power is lower than the threshold power, the process proceeds to stage 206, in which the SMPS operates under a light load condition with a burst-mode controller.

[0021] FIG. 3 is a schematic block diagram of a power supply according to several embodiments of the technology. The illustrated embodiment is based on a flyback topology with a fixed on-time variable off-time control mode though other topologies may also be used. When the SMPS operates under a normal load condition, the burst-mode controller 302 is inactive. A high frequency pulse signal generator 303 receives a feedback signal 104 and a switch current detecting signal 102, and outputs a signal to control the switching of the switch S1 with a fixed on-time variable off-time control mode. When the SMPS operates under a light load condition, the burst-mode controller 302 becomes active. The burst-mode controller 302 outputs a signal 305 to control the frequency of the output signal 307 from the high frequency pulse signal generator 303. The burst-mode controller 302 also outputs a low frequency modulation signal 306 to modulate the signal 307 via the AND gate 308. In one embodiment, the value of the current Is1 is detected through detecting the voltage across a resistor R1. In other embodiments, the value of the current Is1 may be detected through other suitable techniques.

[0022] FIG. 4 is a detailed schematic diagram for the power supply in the FIG. 3. As shown in FIG. 4, the high frequency pulse signal generator 303 comprises: a frequency setting module 401 for the high frequency pulse signal, a circuit selecting module 402, a third comparator 403, and a flip-flop 404. The module 401 is used to set the frequency of the signal 307, which is the output signal of the module 303. The frequency setting of the signal 307 can be realized by adjusting the value of a capacitor C2 and/or the value of a current source 12. The circuit selecting module 402 compares input signals, selecting one of them as an output signal based on the comparison result. For a normal load condition, the feedback signal 104 is selected as an output; for a light load condition, the signal 305 is selected as an output. The output terminal of the module 402 is connected to the inverting input of the comparator 403, the non-inverting input of the comparator 403 receives the output from the module 401. The flip-flop 404, with its SET terminal connected to the output terminal of the comparator 403, and its RESET terminal receiving the signal 102, outputs the signal 307. The signal 307 is coupled to the module 401 through a module Tpulse1 to discharge the capacitor C2. The signal 307 is also received by one terminal of a logic ADD gate 308, the other terminal of the ADD gate 308 receives the modulation signal 306, the output terminal of the ADD gate 308 is coupled to control the switching of switch S1.

[0023] The burst-mode controller 302 comprises: a modulation signal frequency setting module 410, a threshold setting module 411, a first subtracter 412, a second subtracter 413, a first comparator 414 and a second comparator 415. The module 410 is used to set the frequency of the modulation signal 306, which can be realized by adjusting the value of the voltage source V3 and/or the value of the capacitor C3 and/or the value of the resistor R3. The threshold setting module 411 outputs a signal 422, whose value determines the output power level when the SMPS transits from a normal load condition to a light load condition. The signal 422 is coupled to the input terminal of the second subtracter 413, and also to the inverting terminal of the comparator 415.

[0024] In one embodiment, the signal 422 is set to be a value such that when the output power decreases to a value that is 20% of the output power value at a full load, the SMPS transmits into a light load condition. The first subtracter 412 receives the feedback signal 104 as an input signal, and outputs a signal 421; the output terminal of the subtracter 412 is connected to the non-inverting terminal of the comparator 414. Vfb stands for the value of the feedback signal 104, Vref is a predetermined value, the function of the subtracter 412 can be described as Vsub1=Vref−Vfb (Vsub1 stands for the value of the output signal 421). The function of the subtracter 413 can be described as Vsub2=Vref−Vth, in which Vth stands for the value of the signal 422 and Vsub2 is the value of the signal 305. The non-inverting terminal of the comparator 414 is connected to the output terminal of the subtracter 412, the inverting terminal of the comparator 414 is connected to the output of the module 410, the output terminal of the comparator 414 is connected to the input terminal of the ADD gate 308, and the other input signal of the ADD gate 308 is the output signal 307 from the module 303. The non-inverting terminal of the comparator 415 is connected to the output signal of the module 410, the inverting terminal of the comparator 415 is connected to the output terminal of the module 411, and the output signal 420 of the comparator 415 is coupled to the module Tpulse2 to discharge the capacitor C3. The output signal 423 of the module 410 is a saw-tooth waveform, whose frequency is the same as that of the modulation signal 306.

[0025] FIG. 5A shows voltage waveforms of a power supply under a normal load condition, and FIG. 5B shows voltage waveforms of a power supply under a light load condition. In one embodiment, the value of the feedback signal 104 (Vfb) becomes bigger when the output power becomes lower. If Vfb is smaller than Vsub2, which is the value of the output signal 305 of the subtracter 413, the module 402 selects the feedback signal 104 as the input signal to the inverting terminal of the comparator 403, indicating a normal load condition. In FIG. 5A, Vc2 shows the voltage waveform across the capacitor C2; VR1 shows the voltage waveform across the resistor R1; VS shows the waveform of the input signal to the SET terminal of the flip-flop 404; VR shows the waveform of the input signal to the RESET terminal of the flip-flop 404; and Vn shows the waveform of the signal 307.

[0026] For a normal load condition, the switch driving signal 310 has a similar waveform as the signal 307. Taking the waveforms within a high frequency signal period (from Ts0 to Ts2) as an example, at the instant Ts0, the voltage across the capacitor C2 reaches Vfb, the output signal of the comparator 403 becomes high, which sets the flip-flop 404, the output voltage at the Q terminal becomes high. The switch S1 is closed, the current Is1 through the switch S1 increases and the voltage VR1 starts increasing. The Q terminal is coupled to the Tpulse1 module to generate a pulse signal with an interval of Tp1. The pulse signal is coupled to the module 401, discharging the voltage across the capacitor C2. After the interval Tp1, the capacitor C2 is charged again by a current source 12 until the beginning of the next period (at instant Ts2). From the instant Ts0 to the instant Ts1, the voltage VR1 increases continually. The voltage on the inverting terminal of the comparator 416 is Vimax, which is set by a voltage source Vsense. When VR1 reaches Vimax, the output of the comparator 416 becomes high, the flip-flop 404 is reset and the Q terminal becomes low. Switch S1 is opened and VR1 decreases to 0 volts. The switch S1 is kept opened until to the beginning of the next period. At the instant Ts2, Vc2 increases to Vfb again. Afterwards, the waveforms in FIG. 5A repeat as those from Ts0 to Ts2.

[0027] The period of Vc2 is Ts, and the period of Vn is also Ts. Ts comprises Tp1 and Tchrs-n, Tp1 is pre-determined by module Tpulse1, and Tchrs-n can be set by adjusting the value of the capacitor C2 and/or the value of the current source 12 and/or the value of the feedback signal 104. Cs stands for the value of the capacitor C2, Is stands for the value of the current source 12, and Tchrs-n can be described as

[0028] $T_{\mathrm{chrs}-n}=\frac{C_s{V}_{\mathrm{fb}}}{I_s}$

[0029] Thus, Tchrs-n can be changed in accordance with the change of the feedback signal 104, or by adjusting the value of the capacitor C2, or by adjusting the value of the current source 12. Since Tchrs-n is part of the period Ts, the frequency of the signal 310 can be changed accordingly. Under a normal load condition, the value of the feedback signal 104 (Vfb) becomes bigger if the output power become less, which means Tchrs-n becomes bigger and the frequency of the signal 310 becomes lower.

[0030] When Vfb is smaller than Vsub2, i.e., Vfb<Vref−Vth, which is equivalent to Vref−Vfb>Vth, the voltage of the output signal 306 from the comparator 414 is high, and the burst mode controller 302 is inactive. When Vfb is bigger than Vsub2, which is the value of the output signal 305 of the subtracter 413, the module 402 selects the output signal 305 as the input signal to the inverting terminal of the comparator 403, indicating a light load condition. As shown in FIG. 5B, Vc3 shows the voltage waveform across the capacitor C3. Taking the waveforms within a modulation signal period (from Tm0 to Tm2) as an example, at the instant Tm0, the voltage across the capacitor C3 reaches to a value of Vth, and the output signal 420 of the comparator 415 becomes high. The signal 420 is coupled to the module Tpulse2 to generate a pulse signal with an interval of Tp2, and the pulse signal is coupled to the module 410 to discharge the capacitor C3. After the time of Tp2, the capacitor C3 is charged again until it reaches the instant Tm2, at that time the voltage of the capacitor C3 reaches Vth again. The waveform labeled with Vb shows the waveform of the modulation signal 306. Afterwards, the waveforms in FIG. 5B are repeated as those from Tm0 to Tm2.

[0031] The period of the waveform Vc3 is Tm, and the period of the modulation signal 306 is Tm. The period of Tm comprises Tp2 and Tchrm. In the embodiment, Tp2 is determined by the module Tpulse2, Tchrm can be set by adjusting the value of the voltage source V3, and/or by adjusting the value of the capacitor C3, and/or by adjusting the resistor R3, and/or by adjusting the value of the signal 422. Vm stands for the value of the voltage source V3, Cm stands for the value of the capacitor C3, Rm stands for the value of the resistor R3, and Tchrm can be described as

[0032] $T_{\mathrm{chrm}}=-R_m{C}_m\ln \frac{V_m-V_{\mathrm{th}}}{V_m}$
Thus, Tchrm can be changed by adjusting the value of the voltage source V3, and/or by adjusting the value of the capacitor C3, and/or by adjusting the resistor R3, and/or by adjusting the value of Vth. Since Tchrm is part of the period Tm, the frequency of modulation signal 306 can be changed accordingly.

[0033] Under the light load condition, the circuit selecting module 402 selects the signal 305 as the input signal to the inverting input terminal of the comparator 403, the frequency of the signal 307 is not affected if load changes. Under the light load condition, the period of the signal 307 comprises Tp1 and Tchrs-b, where Tchrs-b is the time for the voltage across the capacitor C2 to increase from 0 volt to a value of Vref−Vth, and the function of Tchrs-b can be described as:

[0034] $T_{\mathrm{chrs}-b}=\frac{C_s\left(V_{\mathrm{ref}}-V_{\mathrm{th}}\right)}{I_s}$
Thus, Tchrs-b can be changed by adjusting the value of the signal 305, and/or by adjusting the value of the capacitor C2, and/or by adjusting the value of the current source 12. Accordingly, the period of the signal 307 can be changed.

[0035] For the light load condition, the relation can be expressed as Vfb<Vref−Vth, while for the normal load condition, the relation can be expressed as Vfb>Vref−Vth. With the change of Vfb, there exists a transition point when Vfb=Vref−Vth. At this point, Tchrs-n equals to Tchrs-b, indicating that the frequency of the output signal 307 from the high frequency pulse generator 303 does not undergo a sudden change.

[0036] FIG. 6 shows voltage waveforms of the switch driving signal corresponding to the embodiment in FIG. 4 under a light load condition. The waveform labeled with Vn is the waveform of the signal 307 with a period of Ts, which is the output signal of the high frequency pulse signal generator 303. The waveform labeled with Vb is the waveform of the signal 306 with a period of Tm, which is the output signal of the burst mode controller 302. The signal 307 is modulated by the signal 306 through the ADD gate 308 to generate the driving signal 310. The waveform of signal 310 is shown by the waveform labeled with Vg. Within the period Tm, there are fewer high frequency pulses for the signal 310 than for the signal 307, which can significantly reduce the power loss caused by the switching of the switch. For reducing the noise caused by the switching of the switch, Ts and Tm can be set to be within a specific range during the light load condition as what is explained in the specification.

[0037] When the SMPS transitions into the light load condition, if the load becomes even lighter, the value of the feedback signal 104 (Vfb) becomes bigger, the value of the signal 421 (Vsub1) becomes smaller, so the duty cycle of the modulation signal 306 is decreased. In the interval of Tm, the number of the high frequency pulses becomes fewer to decrease the power supply to the load.

[0038] FIG. 7 is a block diagram of a power supply according to additional embodiments of the technology. The illustrated embodiment is based on a peak current PWM control mode or a quasi-resonant control mode. If a peak current PWM control mode is used, the module 701 is a clock signal generator. If a quasi-resonant control mode is used, the module 701 is a voltage valley detecting module. The output signal 702 from the module 701 is input to the SET terminal of the flip-flop 404, the circuit selecting module 402 selects one signal as an input to the inverting terminal of the comparator 416 from the feedback signal 104 and the output signal 305. The output signal 703 of the comparator 416 is input to the RESET terminal of the flip-flop 404. The on time of the switch S1 is determined by the value of the signal 704. For the embodiment with a peak current PWM control mode, the clock signal generator sets the flip-flop 404 after each clock period. For the embodiment with a quasi-resonant control mode, the flip-flop is set when it is detected by the voltage valley detecting module that the drain-source voltage across the switch S1 decreases to a minimum value. The clock signal generator and the voltage valley detector are common in the art, so further detailed description is not needed. For a normal load condition, the burst-mode controller 302 is inactive, the feedback signal 104 is selected by the circuit selecting module 402 to output the signal 704 to the switch current detecting module 301. The output signal 703 of the switch current detecting module 301 is used to control the on-time of the switch S1.

[0039] In one embodiment, the value of the feedback signal 104 becomes smaller if the output power decreases. When the output power decreases to a value below the threshold value, the SMPS enters into the light load condition, the burst mode controller 302 becomes active. An output signal 305 form the burst mode controller 302 is selected by the circuit selecting module 402 as an input to the module 301, which makes the on-time of the switch S1 to be a fixed value. Another output signal 306 from the burst mode controller 302 is coupled to one input of an ADD gate 308, and another input of the ADD gate 308 receives the output signal 307 from the flip-flop 404. The output of the flip-flop 404 is coupled to the driving circuit 309 to generate a switch driving signal 310 to turn on and turn off the switch S1. For the light load condition, if a PWM control mode is applied, the frequency of the high frequency pulse signal is set by the clock signal generator; if a quasi-resonant control mode is applied, the frequency range of the high frequency pulse signal can be set by setting the threshold value for the light load condition. The control function of the frequency and duty cycle of the low frequency modulation signal is the same as what is explained in the embodiment shown in the FIG. 4.

[0040] From the foregoing, it will be appreciated that specific embodiments of the disclosure have been described herein for purposes of illustration, but that various modifications may be made without deviating from the disclosure. For example, many of the members of one embodiment may be combined with other embodiments in addition to or in lieu of the members of the other embodiments. Accordingly, the disclosure is not limited except as by the appended claims.