N-way Doherty distributed power amplifier with power tracking

[0001] This application claims the benefit of priority under 35 U.S.C. §119(e) to U.S. patent application Ser. No. 12/108,507, filed Apr. 23, 2008, and through it to U.S. provisional patent application Ser. No. 60/925,577, filed Apr. 23, 2007.

[0002] The present invention generally relates to high power communication systems. More specially, the present invention relates to high efficiency high power amplifiers for such systems.

[0003] In modern digital wireless communication systems, such as IS-95, PCS, WCDMA, OFDM and so on, the power amplifiers have advanced towards having a wide bandwidth and large number of carriers. Recently, orthogonal frequency division multiplexing (OFDM) modulation is an attractive technique for transmitting information efficiently within a limited bandwidth like WiBRO and WiMAX. However, since the OFDM signal consists of a number of independently modulated sub-carriers, it produces a higher peak-to-average power ratio (PAR) signal. A typical PAR for a 64-subcarrier OFDM signal is around 8-13 dB. When the number of sub-carriers is increased to 2048, the PAR also increases, typically from 11 to 16 dB. The power amplifiers designed to operate with these high PARs typically have significantly deteriorated efficiency.

[0004] The Doherty amplifier is known as a technique for improving the efficiency at high output back-off power. Its primary advantage is the ease of configuration when applied to high power amplifiers, unlike other efficiency enhancement amplifiers or techniques such as switching mode amplifiers, EER, LINC and so on. Recent results have been reported on its use as: a symmetric Doherty structure, an asymmetric Doherty structure with uneven power transistors, and a N-way Doherty structure using multi-paralleled transistors. In the case of the symmetric Doherty amplifier, the maximum efficiency point is obtained at 6 dB back-off power.

[0005] The asymmetric Doherty amplifier can obtain a high efficiency at various back-off powers using a combination of different power device sizes for the main and peaking amplifiers. Unfortunately, it is difficult to optimize the gain and output power of the asymmetric Doherty amplifier because of the different device matching circuits and the delay mismatch between the main amplifier and the peaking amplifier.

[0006] The conventional N-way Doherty amplifier has an efficiency enhancement over a conventional 2-way Doherty structure by using multiple parallel transistors of identical devices. Its one drawback is that the total gain will be reduced due to the loss of the N-way input power splitter. Under low gain situations this will increase the power dissipation of the driving amplifier.

[0007] Further, while the conventional N-way Doherty amplifier can offer improved efficiency at high output back-off power, the performance of conventional N-way Doherty amplifiers deteriorates as to both gain and efficiency for higher peak-to-average power ratio (PAPR) signals.

[0008] Hence, a need remains in the arts for a method of applying both circuit-level and system-level techniques simultaneously for improving the gain and efficiency performance of N-way Doherty amplifier at high output back-off power in the high power communication systems.

[0009] Accordingly, the present invention has been made in view of the above problems, and it is an object of the present invention to provide a method for improving the gain and efficiency performance of the Doherty amplifying structure at high output back-off power for high power communication system applications. To achieve the above objects, according to the present invention, the technique employs dual-feed distributed amplifying. The power splitter and combiner of the conventional N-way Doherty amplifier are replaced by hybrid couplers with transmission lines. Compared to the conventional N-way Doherty amplifier, the present invention is able to achieve good isolation at the input and output as well as high gain performance with high efficiency. In an embodiment, a power tracking adaptive bias supply technique is employed. The drain bias voltages and gate bias voltages are adaptively controlled by the input power level. Two alternative approaches as disclosed: 1) Envelope tracking 2) Average power tracking. The envelope tracking technique requires a fast switching power supply whereas the average power tracking technique adapts significantly slower. The power detection circuit can be implemented either using analog circuitry or using digital signal processing.

[0024] In general, the present invention, involves the use of a single-ended dual-feed distributed (SEDFD) amplifying method with an N-way Doherty amplifier structure, so as to achieve high gain and high efficiency performances at high output back-off power. In some embodiments, the gain and efficiency performance is also maximized by adjusting the gate bias of N-way peaking amplifiers and shunt capacitors at the end of the half-wave length gate and drain lines, respectively. Compared to conventional N-way Doherty amplifiers, therefore, the present invention achieves higher power added efficiency (PAE) and higher gain for the multiplexing modulated signals. The method and apparatus provided by the present invention is therefore referred as an N-way Doherty Distributed Power Amplifier (NWDPA) hereafter.

[0025] Various embodiments of the NWDPA according to the present invention will now be described in detail with reference to the accompanying drawings.

[0026] FIG. 1 is a schematic diagram showing an N-way Doherty amplifier using the SEDFD method of the present invention. The RF input signal 101 is provided as an input to main SEDFD amplifier 108 and peaking SEFDF amplifier 107 by means of a power splitter. Each SEDFD amplifier consists of two transmission lines 109, 110, 111, 112 and N multiple transistors 113, 114. All transistors 113, 114 in the SEDFD main amplifier 107 and peaking amplifier 108 are connected by both gate and drain lines 109, 110, 111, 112 with a half-wave length at the center frequency and operate identically. The input signal of the SEDFD amplifier 107, 108 is distributed along the gate line 109, 111 and the amplified output signal is combined along the drain line 110, 112. Since each transistor adds power in phase to the signal, the SEDFD amplifier 107, 108 is able to provide higher gain. A λ/4 microstrip line 103 is prior to the SEDFD peaking amplifier 107 in order to synchronize the phases between the SEDFD main amplifier 108 and the SEDFD peaking amplifier 107. The output signal of the SEDFD main amplifier 108 is passed through a microstrip λ/4 impedance transformer 104 and combined with the output signal of the SEDFD peaking amplifier 107 by the power combiner 105.

[0027] FIG. 2 is a graph showing efficiency characteristics of an NWDPA at various output back-off power. The efficiency of the NWDPA for the maximum power level is given by

[0028] $\eta =\frac{\pi }{4},$

• • [0029] and the efficiency for the medium power level is given by

[0030] $\eta =\frac{\pi }{4}·\frac{\left(\frac{P}{M}+1\right)·{\left(\frac{v_o}{v_{\max }}\right)}^2}{\left(\frac{P}{M}+2\right)·\left(\frac{v_o}{v_{\max }}\right)-1}$

• • [0031] where v_o and v_max are the output voltage and the maximum output voltage, respectively, M is the number of transistors for the main amplifier, and P the number of transistors for the peaking amplifier. Depending upon the embodiment, the main and peaking amplifiers can be either single transistors or multiple transistors, or other forms of amplifiers. In addition, the transistors can be discrete or integrated, again depending upon the embodiment.

[0032] For the low power level, the efficiency of the NWDPA is expressed as

[0033] $\eta =\frac{\pi }{4}·\left(\frac{P}{M}+1\right)·\frac{v_o}{v_{\max }}.$

[0034] The efficiency of the amplifier for various levels of output back-off power is calculated as a function of the number of the main and peaking amplifiers. The relationship between the extended back-off state X_BO and the number of main and peaking amplifiers is given by

[0035] $X_{\mathrm{BO}}=20·{\log }_{10}\left(\frac{P}{M}+1\right).$

[0036] FIG. 3 is a schematic diagram showing an embodiment of a 3-way Doherty SEDFD amplifier of the present invention. In order to provide high efficiency at a back-off power of 9.5 dB, the amplifier consists of one main amplifier 203 and two peaking amplifiers 204, 205 using the same type of transistors. The RF input signal 201 is passed through a 90° hybrid coupler 202 and divided to a main amplifier 203 and two peaking amplifiers 204, 205. Input impedance matching circuits 206, 207, 208 are connected between the coupler and the main amplifier 203 and the peaking amplifiers 204, 205, respectively. In at least some embodiments, the main amplifier 203 is biased as a Class-AB amplifier and the peaking amplifiers 204, 205 biased as Class-C amplifiers. If the main amplifier is generally biased in Class AB mode, it will have a gain compression characteristic. In contrast, if the peaking amplifier is generally biased in Class C mode, it will have a gain expansion characteristic. In at least some embodiments, the present invention takes advantage of the complimentary characteristics, so that the gain compression of the Class AB main amplifier will be compensated by the gain expansion of the Class C peaking amplifiers to create a more linear power amplifier.

[0037] In order to achieve optimized power, output impedance matching circuits 209, 210, 211 are connected to the outputs of the main amplifier 203 and the peaking amplifiers 204, 205. A shunt capacitor C_M 212 is connected to the output impedance matching circuit 209 of the main amplifier 203 so as to optimize the linearity of the NWDPA based on the linearity optimized Doherty amplifier method of U.S. provisional application No. 60/846,905 filed on November 2006, incorporated herein by reference. To obtain peak efficiency point at a desired output back-off power, compensation lines 213 are inserted between output impedance matching circuits 209, 210, 211 and λ/4 impedance transformers 214, 215. The peaking amplifiers 204, 205 are combined using the dual-feed distributed structure which has, in some embodiments, half-wave micro-strip lines 217, 218 at each gate and drain of the first peaking amplifier, shown as a FET for purposes of illustration and clarity. In FIG. 3, the peaking amplifier 1 is combined with the peaking amplifier 2 using a dual-feed distributed structure. The dual-feed distributed structure comprises the half wavelength and quarter wavelength lines and short-circuited quarter-wave length micro-strip lines 219, 220 at each gate and drain of the second peaking amplifier, respectively, connected through the associated input and output impedance matching circuits. The second peaking amplifier is shown in the illustrated embodiment as a single transistor for purposes of simplicity, but could be one or more transistors. The quarter wavelength transmission lines at the output could in some embodiments be replaced by a hybrid coupler.

[0038] The half-wave lines 217 and 218 are, in some embodiments, set at the center frequency of the operating power amplifier bandwidth. Shunt capacitors C_P 221, 222 are connected in some embodiments to both ends of the short-circuited quarter-wave length micro-strip lines 219, 220 for optimizing both gain and efficiency characteristics of the NWDPA. Offset line 213 can be included to prevent leakage power between the main amplifier 203 and the peaking amplifiers 204, 205. In some embodiments, the hybrid coupler 202 will cause some gain compression, and this can be compensated by the gain expansion of the peaking amplifiers. An additional hybrid coupler can be connected at the output in some embodiments. Further, those skilled in the art will appreciate that the main distributed amplifiers and peaking distributed amplifiers can be constructed either as separate miniature microwave integrated circuits or on one integrated MMIC.

[0039] An embodiment of an analog power tracking system in accordance with the invention is shown in FIG. 10 and comprises two primary blocks: Power detection circuitry 234 and Adaptive Bias Supply Circuit 233, together with the N-way Doherty Amplifier of FIG. 3. For simplicity and clarity, like elements from FIG. 3 are shown with like reference numerals. A directional coupler 232 is typically used at the input of the N-Way Doherty power amplifier. The directional coupler extracts a sampling of the input signal. The output of the Adaptive Bias Supply Circuit 233 is fed to the various gate and drain voltage terminals via an RF choke. The RF choke serves to supply DC bias to the active devices while not altering the RF performance. One possible embodiment of the Power detection circuit 234 is shown in FIG. 11 and comprises an attenuator 1100, logarithmic detector 1105, rectifier 1110 including capacitor 1115 and resistor 1120, and operational amplifiers 1125 and 1130. The value of the capacitor 1115 in the rectifier circuit implementation of FIG. 11 controls the averaging time constant. By setting this time constant much faster than the incoming modulation, the circuit of FIG. 11 performs envelope tracking. By setting this time constant much slower than the incoming modulation, the circuit of FIG. 11 performs average power tracking.

[0040] The digital power tracking system in FIG. 9 comprises baseband digital signal processing using DSP 230 to extract either the envelope or the average power of the incoming signal as well as an adaptive bias supply circuit 231. The input signal modulation is accessible at baseband using digital signal processing. Therefore, a power detection algorithm can be easily developed at baseband. The output of the DSP power detection algorithm is fed to a Digital to Analog converter which feeds the Adaptive Bias Supply circuit. FIG. 12 shows an embodiment of the average power tracking algorithm based on a digital signal processing implementation, and comprises a square law function 1200 followed by a low pass filter function 1210 and an averaging of the function X_i from 1 to N, as shown, at 1220. The value of N controls the time window for averaging the input power. FIG. 13 depicts an embodiment of an envelope tracking algorithm. The magnitude of the incoming modulation is processed and followed by a low pass filter. No averaging occurs in this implementation.

[0041] In examining the performance of NWDPA, a 42 dBm high power amplifier is designed and implemented by using LDMOS FET's with p1 dB of 150 W.

[0042] FIG. 4 is a graph showing simulation results of gain and PAE for a single tone signal at the frequency of 2140 MHz using a 3-way Doherty distributed amplifier such as shown in FIG. 3. The operating point of the Class AB biased main amplifier is: I_DQ=510 mA, V_GS=3.82 V and V_DS=27 V. The operating points of the Class C biased peaking amplifiers are: 1) Peaking amplifier 1; I_DQ=0 mA, V_GS=2.4 V and V_DS=27 V, 2) Peaking amplifier 2; I_DQ=0 mA, V_GS=2.6 V and V_DS=27 V. The output impedance of the combined peaking amplifier using a dual-feed distributed structure is 4.65+j2.1Ω. An offset line of approximately 0.25λ was inserted; this corresponds to an optimum output resistance of 521Ω. From the simulated results, 43% PAE was obtained at a peak envelope power (PEP) of around 200 W. Consequently, a 40% PAE at 9.5 dB back-off power from the peak efficiency point was achieved. This was an efficiency improvement of approximately 7% in comparison to that of the 2-way conventional Doherty amplifier at a 6 dB peaking point, also shown in FIG. 4. A gain of approximately 10.5 dB was obtained from 2130 to 2150 MHz.

[0043] FIG. 5 is a graph showing measurement results of gain and PAE of the 3-way Doherty distributed amplifier of the present invention. The main amplifier's operating point is: I_DQ=480 mA, V_GS=3.9 V. The operating points of the peaking amplifiers are: 1) Peaking amplifier 1; I_DQ=0 mA, V_GS=2.1 V; 2) Peaking amplifier 2; I_DQ=0 mA, V_GS=1.9 V. The shunt capacitors, C_P and C_M, of 15 pF and 0.5 pF are used, respectively. A 42.7% PAE at PEP of 131 W and 39.5% PAE at 9.5 dB back off are achieved, respectively. A gain of approximately 11 dB was obtained at 9.5 dB back off.

[0044] FIG. 6 is a graph showing measurement results of gain and PAE performance variation as a function of the shunt capacitor and bias voltage of peaking amplifiers for single-tone signal using the 3-way Doherty distributed amplifier of the present invention. Optimization of C_P and the bias point of the two-peaking amplifiers produced efficiency and gain improvement of approximately 8% and 2 dB at 9.5 dB back off, even though the PAE is reduced at PEP.

[0045] FIG. 7 is a graph showing measurement results of spectrum for a single WCDMA carrier using a 3-way Doherty distributed amplifier in accordance with the present invention. The operating points were V_GS=3.79 V (Main PA), V_GS=3.1 V (Peaking PA1) and V_GS=2.5V (Peaking PA2), respectively. The shunt capacitors, C_P and C_M, of 9.1 pF and 0.5 pF were used, respectively. In order to achieve high linearity, both memoryless and memory-based digital predistortion were applied. The ACLR performances of −51 dBc after memoryless and −54 dBc after memory compensation were obtained at 41 dBm output power and +2.5 MHz offset frequency.

[0046] In summary, the NWDPA of the present invention, compared to the conventional N-way Doherty amplifier, improves the gain performance more effectively since the NWDPA uses a SEDFD structure in conjunction with a Doherty amplifier. A hybrid mode power amplifier system in accordance with the invention is shown in FIG. 4, in which a modulated RF input signal 800 is provided to a digital predistortion controller 805, which in turn provides its output to a power amplifier 810 in accordance with the present invention. The RF output 815 is monitored, and a signal representative of the output is fed back to the controller 805 as a feedback signal 820.

[0047] Although the present invention has been described with reference to the preferred embodiments, it will be understood that the invention is not limited to the details described thereof. Various substitutions and modifications are disclosed in the foregoing description, and others will be apparent to those of ordinary skill in the art based on the teachings herein. Therefore, all such substitutions and modifications are intended to be embraced within the scope of the invention as defined in the appended claims.