Radio receiver having a multipath equalizer

[0001] Related subject matter is found in a copending patent application Ser. No. 12/570,760, filed concurrently herewith, entitled “Radio Receiver Having a Multipath Equalizer,” invented by Javier Elenes and assigned to the assignee hereof.

[0002] The present disclosure relates generally to radio frequency (RF) receivers, and more particularly to RF receivers for use in systems subject to reflection of transmitter signals.

[0003] Radio frequency (RF) receivers are used in a wide variety of applications such as radios, television receivers, cellular telephones, pagers, global positioning system (GPS) receivers, cable modems, cordless phones, and the like. As used herein, a “radio frequency” signal means an electrical signal conveying useful information and having a frequency from about 3 kilohertz (kHz) to hundreds of gigahertz (GHz), regardless of the medium through which such signal is conveyed. Thus an RF signal may be transmitted through air, free space, coaxial cable, fiber optic cable, etc. One of the problems with RF transmission systems is the problem of signal reflection. A receiver may receive multiple versions of the transmitted signal with different strengths and phase shifts because of signal reflection through the transmission medium. These phase shifted versions can destructively interfere with the main received signal and degrade it. The problem is worse for systems such as automobile radio receivers that constantly change position relative to a fixed antenna and that will occasionally be subject to relatively strong reflected signals.

[0016] The use of the same reference symbols in different drawings indicates similar or identical items.

[0017] FIG. 1 illustrates in block diagram form a radio transmission system 100 subject to multipath interference. In system 100, a signal source such as a terrestrial FM radio antenna 110 broadcasts a signal to a receiver in an automobile 120. The transmitted signal, labeled “Tx”, can reach the receiver by any of a number of paths. A path 130 is a direct or line-of-sight path and corresponds to the shortest line between transmitter 110 and the receiver in automobile 120. However the receiver also receives reflections of signal Tx over paths 140 and 150. These reflections interfere with the direct path signal, either constructively or destructively, and along with the direct path signal produce a multipath signal labeled “Rx”. FIG. 1 shows path 140 as a solid line and path 150 as a dashed line to indicate that the signal received via path 140 is stronger than the signal received via path 150. Signals 140 and 150 arrive with random phase with respect to direct path signal 130. Moreover when automobile 120 is moving relative to antenna 110, one or more reflected signals with significant energy will frequently destructively interfere with the direct path signal, resulting in low signal-to-noise ratio and generally poor received signal quality.

[0018] In order to avoid the destructive interference and poor Rx signal quality caused by reflected signals along paths 140 and 150, the radio receiver in automobile 120 includes a multipath equalizer that digitally filters signal Rx to improve signal-to-noise ratio and signal quality by adaptively removing out-of-phase interference. Generally, the radio receiver down converts the received radio signal to a low intermediate frequency (LIF) signal that can be efficiently processed using a digital signal processor (DSP). The radio receiver implements the multipath equalizer in the digital domain using the DSP.

[0019] As will be described more fully below, the multipath equalizer assumes that only the signals along direct path 130 and path 140 have significant energy. By ignoring the reflected signal along path 150 and other weaker reflected signals, the radio receiver is able to simplify the signal processing required to allow for implementation in a low cost integrated circuit.

[0020] The overall architecture of the radio receiver will now be described with reference to FIG. 2, which illustrates in partial block diagram and partial schematic form a radio receiver 200 with a multipath equalizer according to an embodiment of the present invention. Radio receiver 200 includes generally an antenna 210, an integrated circuit receiver 220, power amplifiers 260 and 262, and loudspeakers 270 and 272.

[0021] Integrated circuit receiver 220 generally includes a tracking bandpass filter 222, a low noise amplifier (LNA) 224, a quadrature mixer 230, programmable gain amplifiers 240 and 242, lowpass filters 244 and 246, analog-to-digital converters (ADCs) 248 and 250, a DSP 252, and digital-to-analog converters (DACs) 254 and 256. Tracking bandpass filter 222 has an input connected to antenna 210, a tuning input for receiving a tuning signal from an on-chip microcontroller (MCU) (not shown in FIG. 2), and an output. LNA 224 has an input connected to the output of tracking bandpass filter 222, and an output. Mixer 230 has an input connected to the output of LNA 224, a first output for providing an in-phase signal labeled “I”, and a second output for providing a quadrature signal labeled “Q”. PGA 240 has an input connected to the I output of mixer 230, and an output. PGA 242 has an input connected to the Q output of mixer 230, and an output. Lowpass filter 244 has an input connected to the output of PGA 240, and an output. Lowpass filter 246 has an input connected to the output of PGA 242, and an output. ADC 248 has an input connected to the output of lowpass filter 240, and an output for providing a multi-bit digital output signal. ADC 250 has an input connected to the output of lowpass filter 242, and an output providing a multi-bit digital output signal. DSP 252 has inputs connected to the outputs of ADCs 248 and 250, an input/output port for being connected over a serial bus, known as an “I²S” bus, to the MCU, and first and second outputs for providing multi-bit digital output signals labeled “L” and “R”, respectively. DAC 254 has an input connected to the first output of DSP 252 for receiving the L signal, and an output connected to an input of an off-chip power amplifier 260, whose output is provided to and drives loudspeaker 270. DAC 256 has an input connected to the second output of DSP 252 for receiving the R signal, and an output connected to an input of an off-chip power amplifier 262, whose output is provided to and drives loudspeaker 272.

[0022] More particularly mixer 230 includes a local oscillator 232, a multiplier 234, and a multiplier 236. Local oscillator 232 has an input for receiving a frequency control signal, and outputs for providing two local oscillator signals in quadrature with each other, one output providing an in-phase local oscillator signal and the other providing a quadrature local oscillator signal phase-shifted from the in-phase local oscillator signal by ninety degrees. Multiplier 234 has a first input connected to the output of LNA 224, a second input for receiving the in-phase local oscillator signal, and an output for providing the I signal. Multiplier 236 has a first input connected to the output of LNA 224, a second input for receiving the quadrature local oscillator signal, and an output for providing the Q signal.

[0023] Generally, receiver 220 receives stereo frequency modulated (FM) radio signals and converts them into demodulated signals capable of driving left and right loudspeakers 270 and 272, respectively. It implements a superheterodyne architecture in which the MCU controls the center frequency of tracking bandpass filter 222 and the frequency of local oscillator 232 according to a user-supplied tuning input. The MCU selects the frequency of local oscillator 232 to mix a desired channel to an LIF. Filters 244 and 246 reject undesired high frequency content of the down converted and amplified I and Q signals. ADCs 248 and 250 convert the filtered I and Q signals to the digital domain. DSP 252 further processes the digitized I and Q signals to produce digital signals to drive the left and right channels. The further processing includes down conversion to baseband, digital image rejection, FM demodulation, and multipath signal equalization.

[0024] Mathematically, the time domain output of the channel y(t) can be expressed as a function of the input of the channel x(t) as follows:
y(t)=x(t)·Σr_kδ(t−τ_k  [1]
in which x(t) is the input of the channel, in this case the complex transmitted signal, y(t) is the output of the channel, in this case the received multipath signal, r_k is the complex reflection coefficient for ray k, δ is the Dirac function, τ_k is the delay introduced by ray k, and the summing interval is over all values of k. The construction of the multipath equalizer can be simplified by assuming that only signals received via the line-of-sight path and a second reflection path will have significant energy. Such a multipath equalizer assumes a “2-ray” propagation channel model. Referring back to FIG. 1, a 2-ray multipath equalizer assumes that only paths 130 and 140 are significant, but that path 150 is not. Thus in a 2-ray model, equation [1] can be simplified as follows:
y(t)=x(t)·(1+rδ(t−τ))  [2]

[0025] In the discrete time domain, signal y(n) can be expressed as a function of transmitted signal x(n) as follows:
y(n)=x(n)+r·x(n−D)  [3]
in which r is the reflection coefficient, D is the delay coefficient, x(n) is the direct path component, and r·x(n−D) is the reflected component. In equation [3], x, y, and r are complex numbers. The equivalent expression in the z domain is:
y(z)=x(z)·(1+rz^−D)  [4]
The channel transfer function M(z) can be expressed as follows:

[0026] $\begin{array}{cc}M\left(z\right)=\frac{y\left(z\right)}{x\left(z\right)}=1+{\mathrm{rz}}^{-D}& \left[5\right]\end{array}$
Therefore to reconstruct the original transmitted signal from the received signal, the multipath equalizer must apply a transfer function H(z) as follows:

[0027] $\begin{array}{cc}H\left(z\right)=\frac{1}{1+{\mathrm{rz}}^{-D}}& \left[6\right]\end{array}$
which is a form of an infinite impulse response (IIR) filter.

[0028] Now the multipath equalizer in DSP 252 will be described with reference to FIG. 3, which illustrates in block diagram form a multipath equalizer 300 used in DSP 252 of FIG. 2. Multipath equalizer 300 includes a digital filter labeled “H(z)” 310, and a coefficient estimator 320. Digital filter 310 has a signal input for receiving a sampled received signal labeled “x(n)”, control inputs for receiving a reflection coefficient labeled “r” and a delay coefficient labeled “D”, and an output for providing a reconstructed signal labeled “y(n)”. Coefficient estimator 320 has a first input for receiving signal x(n), a second input for receiving signal y(n), and an output connected to the control inputs of digital filter 310 for providing coefficients r and D.

[0029] Generally multipath equalizer 300 is a “blind” equalizer because it does not use a training signal to reconstruct the transmitted signal from the received multipath signal. Rather it uses the property of constant modulo (CM) modulation systems that the amplitude is constant while the phase angle changes. CM modulation systems include frequency modulation (FM), phase modulation (PM), frequency shift keying (FSK) modulation, phase shift keying (PSK) modulation, etc., although FM is a very common one of those techniques. Coefficient estimator 320 adapts digital filter 310 to reconstruct the original signal by minimizing the deviation of the received signal magnitude from a normalized value.

Digital Filter

[0030] Digital filter 310 receives a multipath signal as an input signal x(n) and filters it using coefficients r and D according to transfer function H(z) to provide a reconstructed signal as output signal y(n). However r and D are functions of time and their values can change rapidly, especially when receiver 200 is used in a moving vehicle. Thus the accuracy of y(n) depends on the accuracy by which coefficient estimator 320 adapts r and D to changing conditions. As mentioned above, multipath equalizer 300 uses the property of CM signals that they have constant amplitudes to adapt r and D. In the example of FM signals, the amplitude is constant but the phase varies. Thus an FM signal can be viewed as points along a circle in the complex (I/Q) plane. Reflected signals distort the location of these points from being on the circle. Coefficient equalizer 320 adapts r and D to minimize the deviation of the magnitude of y(n) from this ideal circle. In particular, coefficient estimator 320 attempts to minimize the value of a mean squared error (MSE), which is a function of an error signal expressed as |y(n)²−1|, where 1 is a normalized value of the received signal.

[0031] As long as |r|<1 and D>0, then a digital filter constructed using equation [5] is stable. However frequently a reflected signal will arrive with more energy than the direct path signal. In this case, D<0 and digital filter 300 would become unstable.

[0032] H(z) can be expressed in an equivalent form by expanding the IIR expression:

[0033] $\begin{array}{cc}H\left(z\right)=\frac{1}{1+{\mathrm{rz}}^{-D}}=1-{\mathrm{rz}}^{-D}+r^2{z}^{-2D}-r^3{z}^{-3D}+r^4{z}^{-4D}\dots & \left[5\right]\end{array}$
While this form of H(z) is stable, it is an infinite series and cannot be completely evaluated. Kammeyer et al. in “A Modified Adaptive FIR Equalizer for Multipath Echo Cancellation in FM Transmission,” IEEE J. on Selected Areas in Communication, vol. SAC-5, no. 2, February 1987, pp. 226-237 disclose truncating this form of a digital filter to 64 terms. Such a filter is still too large for implementation in low-cost integrated circuits. However the inventor has discovered that the multipath equalizer can provide most of the benefits needed for broadcast FM radio systems if the infinite series of equation [5] is truncated to only the first eight terms.

[0034] Reference is now made to FIG. 4, which illustrates in block diagram form a possible realization 400 of digital filter 310 of FIG. 3. Digital filter 400 includes sample buffers and multipliers to implement digital filer 300 with eight terms, including representative sample buffers 410, 420, 430, and 440, representative multipliers 450, 460, 470, and 480, and a summing device 490. Sample buffer 410 has an input for receiving signal x(n), and an output. More particularly, sample buffer 410 includes further representative buffers 412, 414, and 416. Each buffer is serially connected and implements a single unit delay labeled “z⁻¹”. Sample buffer 420 has an input connected to the output of sample buffer 410, and an output. Sample buffer 430 has an input connected to the output of sample buffer 420, and an output connected to another sample buffer, not shown in FIG. 4. Sample buffer 440 has an input connected to the output of yet another sample buffer, not shown in FIG. 4, and an output. Multiplier 450 has an input connected to the output of sample buffer 410, and an output, and multiplies the input thereof by a factor of −r. Multiplier 460 has an input connected to the output of sample buffer 420, and an output, and multiplies the input thereof by a factor of r². Multiplier 470 has an input connected to the output of sample buffer 430, and an output, and an output, and multiplies the input thereof by a factor of −r³. Multiplier 480 has an input connected to the output of sample buffer 440, and an output, and multiplies the input thereof by a factor of −r⁷. Summing device 490 has a first input for receiving x(n), additional inputs connected to the outputs of seven multipliers including representative multipliers 450, 460, 470, and 480, and an output for providing signal y(n).

[0035] Digital filter 400 is useful in understanding the practical difficulties of constructing a digital filter in DSP circuitry. In the example shown in FIG. 4, equation [5] is truncated to only eight terms. However even an 8-term implementation of the digital filter is still computationally intensive because the DSP must perform (N−1)=7 multiplies, in which N is the number of terms and is equal to eight. Thus a conventional FIR filter truncated to a reasonable number of terms is still expensive in terms of circuit area and computational time.

[0036] In order to implement digital filter 310 less expensively while maintaining good fidelity for commercial FM transmission systems, the inventor has discovered not only that the IIR form of H(z) can be converted into an equivalent infinite series and truncated to eight terms, but also that this eight-term filter can then be evaluated using an algebraic simplification of equation [5] of only three terms:
H(z)=(1−rz^−D)×(1+r²z^−2D)×(1+r⁴z^−4D)  [6]
This form of H(z) requires only log₂N=3 multiplies.

[0037] An implementation of such a digital filter is shown in FIG. 5, which illustrates in block diagram form digital filter 310 used in multipath equalizer 300 of FIG. 3. Digital filter 310 generally includes a first term section 510, a second term section 520, and a third term section 530. First term section 510 includes a delay buffer 512, a multiplier 514, and a summing device 516. Delay buffer 512, labeled “z^−D”, has an input for receiving x(z), and an output, and applies a delay of D. Multiplier 514 has an input connected to the output of delay buffer 512, and an output, and multiplies the input thereof by a factor of −r. Summing device 516 has a first input for receiving signal x(n), a second input connected to the output of multiplier 514, and an output.

[0038] Second term section 520 includes a delay buffer 522, a multiplier 524, and a summing device 526. Delay buffer 522, labeled “z^−2D”, has an input connected to the output of summing device 516, and an output, and applies a delay of 2D. Multiplier 524 has an input connected to the output of delay buffer 522, and an output, and multiplies the input thereof by a factor of r². Summing device 526 has a first input the output of summing device 516, a second input connected to the output of multiplier 524, and an output.

[0039] Third term section 530 includes a delay buffer 532, a multiplier 532, and a summing device 536. Delay buffer 532, labeled “z^−4D”, has an input connected to the output of summing device 526, and an output, and applies a delay of 4D. Multiplier 534 has an input connected to the output of delay buffer 532, and an output, and multiplies the input thereof by a factor of r⁴. Summing device 536 has a first input the output of summing device 526, a second input connected to the output of multiplier 534, and an output for providing signal y(n).

[0040] Digital filter 310 evaluates H(z) not only by truncating the infinite series form of the IIR filter to eight terms, but also by using an algebraic simplification of this truncated estimation, resulting in a digital filter having only three terms and requiring only three multiplies. In general this algebraic simplification reduces the number of multiplies required from (N−1) to log₂N, in which N is the number of terms the truncated series. Thus the digital filter can be implemented more easily in a low-cost integrated circuit using DSP technology.

[0041] As noted above, multipath equalizer 300 assumes a 2-ray propagation channel model by assuming the presence of a line-of-sight signal and only one reflected signal with significant energy. However occasionally the line-of-sight will be partially obstructed such that the strongest received signal may actually arrive later than the line-of-sight signal. This condition is illustrated with respect to FIGS. 6 and 7. FIG. 6 illustrates a graph 600 of the reception of a multipath radio signal x(t) under line-of-sight conditions. In graph 600, the horizontal axis represents time between transmission and reception in seconds, and the vertical axis the amplitude of the absolute value of the received signal x(t) in volts. In the example shown in FIG. 6, a first received or line-of-sight signal 610 has greater amplitude than a later received signal 620. Thus, D is greater than 0. In contrast, FIG. 7 illustrates a graph 700 of the reception of a multipath radio signal under non line-of-sight conditions. In graph 700, the horizontal axis represents time between transmission and reception in seconds, and the vertical axis the absolute value of the received signal x(t) in volts. In the example shown in FIG. 7, a first received or line-of-sight signal 710 has smaller amplitude than a later received signal 720. Since the multipath equalizer uses the ray with the strongest signal as the primary ray, D is less than 0. While conventional digital filters operate in causal systems, they cannot accommodate non-causal systems. What is needed then is a digital filter that is able to accommodate both causal and non-causal conditions.

[0042] A portion of such a filter is shown in FIG. 8, which illustrates in block diagram form a delay line 800 for use in digital filter 310 of FIG. 3. Delay line 800 includes two sections including a set of delay elements 810, and a set of delay elements 830. Set 810 has K delay elements including representative delay elements 812, 814, and 816 all connected in series. First delay element 812 has an input for receiving and storing a sample x(n+K), and last delay element 816 has an output forming the output of set 810. The output of delay element 816 forms sample x(n). Set 830 has K delay elements including representative delay elements 832, 834, and 836 all connected in series with the input of first delay element 832 connected to the output of delay element 816, and last delay element 836 storing sample x(n−K).

[0043] Delay line 800 accommodates both causal (line-of-sight) and non-causal systems by a modest expansion of the size of the delay buffer by K elements. K is large enough to implement equation [6] for D=16. In a causal system with positive values of D, filter 310 uses current sample x(n) and samples from second set 830 as described above. In a non-causal system with negative values of D, however, filter 310 uses current sample x(n) and samples from first set 810.

[0044] In DSP implementations, delay buffer 800 does not actually include samples that shift every clock period. Rather the DSP stores the samples in sequential locations in a memory and adjusts pointers into the memory. For example if D is equal to 16, the DSP uses an indexed addressing mode to retrieve the samples from the buffer in strides of 16.

[0045] FIG. 9 illustrates in block diagram form a multipath equalizer 900 according to another embodiment of the present invention. Multipath equalizer 900 includes a normalizer 910, digital filter 310, and coefficient estimator 320. Normalizer 910 has an input for receiving signal x(n), and an output. Digital filter 310 has a signal input connected to the output of normalizer 910, control inputs for receiving coefficients r and D, and an output for providing signal y(n). Coefficient estimator 320 has a first input connected to the output of normalizer 910, a second input for receiving y(n), and an output connected to the control inputs of digital filter 310 for providing coefficients r and D.

[0046] In particular normalizer 910 includes an absolute value block 912, an averaging filter 914, a linear-log converter 916, a summing device 918, a log-linear converter 920, and a multiplier 922. Absolute value block 912 has an input for receiving signal x(n), and an output. IIR filter 914 has an input connected to the output of absolute value block 912, and an output. Linear-log converter 916 has an input connected to the output of IIR filter 914, and an output. Summing device 918 has a first input connected to the output of linear-log converter 916, a second input for receiving a reference level labeled “REF”, and an output. Log-linear converter 920 has an input connected to the output of summing device 918, and an output. Multiplier 922 has a first input for receiving x(n), a second input connected to the output of log-linear converter 920, and an output connected to the input of digital filter 310.

[0047] Normalizer 910 converts the amplitude of signal x(n) to a suitable level that becomes a known, normalized magnitude of the signal. This normalized magnitude can be used as a reference by coefficient estimator 320 to determine the error signal.

Coefficient Estimator

[0048] FIG. 10 illustrates in block diagram form a specific implementation 1000 of multipath equalizer 300 of FIG. 3. This implementation uses two important simplifications for the coefficient updates that reduces computation time and allows implementation in a low-cost integrated circuit. Multipath equalizer 1000 has elements corresponding to both digital filter 310 and coefficient estimator 320, and includes generally a digital filter portion 1020, a delay update portion 1040, an r update portion 1060, an error estimation portion 1080, and group delay elements 1091-1095.

[0049] Group delay element 1091 has an input for receiving signal x(n), and an output, and applies a delay of 4K. Digital filter portion 1020 includes a first term section 1021, a second term section 1025, and a third term section 1029. First term section 1021 includes a delay buffer 1022, a multiplier 1023, and a summing device 1024. Delay buffer 1022, labeled “z^−D”, has an input connected to the output of group delay element 1091, and an output, and applies a delay of D. Multiplier 1023 has an input connected to the output of delay buffer 1022, and an output, and multiplies the input thereof by a factor of −r. Summing device 1024 has a first input connected to the output of group delay element 1091, a second input connected to the output of multiplier 1023, and an output.

[0050] Group delay element 1092 has an input connected to the output of summing device 1024, and an output. Second term section 1025 includes a delay buffer 1026, a multiplier 1027, and a summing device 1028. Delay buffer 1026, labeled “z^−2D)”, has an input connected to the output of group delay element 1092, and an output, and applies a delay of 2D. Multiplier 1027 has an input connected to the output of delay buffer 1026, and an output, and multiplies the input thereof by a factor of r². Summing device 1028 has a first input connected to the output of group delay element 1092, a second input connected to the output of multiplier 1027, and an output.

[0051] Group delay element 1093 has an input connected to the output of summing device 1028, and an output. Third term section 1029 includes a delay buffer 1030, a multiplier 1031, and a summing device 1032. Delay buffer 1030, labeled “z^−4D”, has an input connected to the output of group delay element 1093, and an output, and applies a delay of 4D. Multiplier 1031 has an input connected to the output of group delay element 1030, and an output, and multiplies the input thereof by a factor of r⁴. Summing device 1031 has a first input connected to the output of group delay element 1093, a second input connected to the output of multiplier 1031, and an output for providing signal y(n).

[0052] Delay update portion 1040 includes a partial derivative block 1041, a multiplier 1042, a delay element 1043, a complex conjugate operator block 1044, a multiplier 1045, a real operator block 1046, a multiplier 1047, and a multiplier 1048. Derivative block 1051 has an input connected to the output of group delay element 1091, and an output. Multiplier 1042 has an input connected to the output of partial derivative block 1041, and an output, and multiplies the input thereof by a factor of −r. Delay element 1043, labeled “z^−D”, has an input connected to the output of multiplier 1042, and an output, and provides a delay of D. Group delay element 1094 has an input connected to the output of delay element 1043, and an output, and provides a delay of 6K. Complex conjugate operator block 1044 has an input for receiving signal y(n), and an output. Multiplier 1045 has a first input connected to the output of group delay element 1094, a second input connected to the output of complex conjugate operator block 1044, and an output. Real operator block 1046 has an input connected to the output of multiplier 1045, and an output. Multiplier 1047 has an input connected for receiving an error signal labeled “e”, and an output, and multiplies the input thereof by a factor of μ_k. Multiplier 1048 has a first input connected to the output of real operator bock 1046, a second input connected to the output of multiplier 1047, and an output for providing a signal labeled “DELAY UPDATE”.

[0053] r update section 1060 includes a delay element 1061, a multiplier 1062, a summing device 1063, a delay element 1064, a multiplier 1065, a summing device 1066, a delay element 1067, a multiplier 1068, a summing device 1069, a complex conjugate block 1070, a multiplier 1071, a multiplier 1072, and a multiplier 1073. Delay element 1061, labeled “z^−2D, has an input connected to the output of group delay element 1091, and an output, and applies a delay of 2D. Multiplier 1062 has an input connected to the output of delay element 1061, and an output, and multiplies the input thereof by a factor of 2r. Summing device 1063 has a first input connected to the output of delay element 1022 in digital filter portion 1020, a second input connected to the output of multiplier 1062, and an output. Delay element 1064, labeled “z^−3D, has an input connected to the output of group delay element 1091, and an output, and applies a delay of 3D. Multiplier 1065 has an input connected to the output of delay element 1064, and an output, and multiplies the input thereof by a factor of 3r². Summing device 1066 has a first input connected to the output of summing device 1063, a second input connected to the output of multiplier 1065, and an output. Delay element 1067, labeled “z^−4D, has an input connected to the output of delay element 1091, and an output, and applies a delay of 4D. Multiplier 1068 has an input connected to the output of delay element 1067, and an output, and multiplies the input thereof by a factor of 4r³. Summing device 1069 has a first input connected to the output of summing device 1066, a second input connected to the output of multiplier 1068, and an output. Group delay element 1095, labeled “z^−6K, has an input connected to the output of summing device 1069, and an output, and applies a delay of 6K. Complex conjugate block 1070 has an input connected to the output of group delay element 1095, and an output. Multiplier 1071 has a first input connected to the output of complex conjugate block 1070, a second input for receiving signal y(n), and an output. Multiplier 1072 has an input for receiving signal e, and an output, and multiplies the input thereof by a factor of μ_r. Multiplier 1073 has a first input connected to the output of multiplier 1072, a second input connected to the output of multiplier 1071, and an output for providing an output signal labeled “r UPDATE”.

[0054] Error estimation portion 1080 includes an absolute value block 1081, an averaging filter 1082, a summing device 1083, a square block 1084, and an expected value 1085. Absolute value block 1081 has an input for receiving signal y(n), and an output, and outputs a square of an absolute value of an input thereof. Averaging filter 1082 has an input connected to the output of absolute value block 1081, and an output, and applies a transfer function of

[0055] $\frac{1-a}{1-{\mathrm{az}}^{-1}}$
thereto. Summing device 1083 has a positive input connected to the output of absolute value block 1081, a negative input connected to the output of smoothing filter 1082, and an output for providing signal e. Square block 1084 has an input connected to the output of summing device 1083, and an output. Expected value block 1085 has an input connected to the output of square block 1084, and an output for providing a mean-squared-error output signal labeled “MSE”.

[0056] Digital filter portion 1020 implements the digital filtering function H(z) as disclosed above and thus y(n) is equal to the input sample x(n) multiplied by H(z) as expressed in equation [6] above. Group delay elements 1091-1093 ensure that the outputs of digital filter portion 1020 correspond in time to the outputs of D update portion 1040 and r update portion 1060.

[0057] Error estimation portion 1080 calculates error signal e used by both delay update portion 1040 and r update portion 1060, and mean-squared-error signal MSE for use by DSP 252 in performing r and D acquisition and updating. Note that averaging filter 1082 determines an average level of the reconstructed signal. However in embodiments in which normalizer 910 is used, summing device 1083 would receive the square of REF at its negative input and averaging filter 1082 would be eliminated.

[0058] In general, the output y can be expressed in the sampling domain as a product of a transposed matrix X^T and a matrix of coefficients h, or
y=X^T·h  [7]
in which X is a matrix of samples of the received signal sampled at intervals of length D:
X=[x(n)x(n−D)x(n−2D)x(n−3D) . . . ]  [8]
and h is equal to a matrix of filter coefficients:
h=[h0h1h2h3 . . . ]  [9]
or more particularly:
h=[1−r r²−r³ . . . ]  [10]
The delay update is expressed as:

[0059] $\begin{array}{cc}D\left(i+1\right)=D\left(i\right)-{\mu }_D·e\left(i\right)·\mathrm{Re}\left\{y^{*}\left(i\right)·h^T\left(i\right)·\frac{\partial x\left(i\right)}{\partial D\left(i\right)}\right\}& \left[11\right]\end{array}$
in which D(i+1) is the updated value of D, D(i) is the current value of D, μ_D is a smoothing coefficient, e(i) is the current error signal, y*(i) is the complex conjugate of the current filtered output y(i), and

[0060] $\frac{\partial x\left(i\right)}{\partial D\left(i\right)}$
is the partial derivative of x(i) with respect to D(i).

[0061] x(i) is a matrix of values of infinite length. However the inventor has discovered that the partial derivative

[0062] $\frac{\partial x\left(i\right)}{\partial D\left(i\right)}$
can be estimated as

[0063] $\frac{\partial [\begin{array}{cc}x\left(n\right)& x\left(n-D\right)]\end{array}}{\partial D\left(i\right)}$
and still provide relatively fast convergence. Moreover

[0064] $\frac{\partial [\begin{array}{cc}x\left(n\right)& x\left(n-D\right)]\end{array}}{\partial D\left(i\right)}$
is equal to

[0065] $\frac{\partial \left[x\left(n-D\right)\right]}{\partial D\left(i\right)}$
since

[0066] $\frac{\partial x\left(n\right)}{\partial D\left(i\right)}$
is equal to 0. Thus the partial derivative can be approximated by evaluating a single partial derivative term. Partial derivative block 1041 performs this evaluation, and multiplies the result by corresponding coefficient −r in multiplier 1042. The remainder of equation [11] is performed by elements 1044-1048 to yield D(i+1). Thus the estimation of the partial derivative expression using two terms allows the multipath equalizer to be implemented in a low-cost integrated circuit.

[0067] The r update is expressed as:

[0068] $\begin{array}{cc}r\left(i+1\right)=r\left(i\right)-{\mu }_r·e\left(i\right)·{y\left(i\right)\left[X^T·\frac{\partial h\left(i\right)}{\partial r\left(i\right)}\right]}^{*}& \left[12\right]\end{array}$
in which r(i+1) is the updated value of r, r(i) is the current value of r, μ_r is a smoothing coefficient, e(i) is the prior error signal, y(i) is the prior output signal, X^T is the transposed matrix of input samples, and

[0069] $\frac{\partial h\left(i\right)}{\partial r\left(i\right)}$
is the partial derivative of h(i) with respect to r(i). As with equation [11], evaluation of the partial derivative term is problematical since h(i) is a matrix of values of infinite length. The inventor has discovered that the partial derivative

[0070] $\frac{\partial x\left(i\right)}{\partial D\left(i\right)}$
can be estimated as −rx(n−D)+2rx(n−2D)+3r²x(n−3D)+4r³x(n−4D) and still provide relatively fast convergence. It can be seen that this approximation represents the partial derivative of each coefficient with respect to r, truncated to four terms. r update portion 1060 used elements 1061-1069 to evaluate the expression, and advantageously uses the output of delay element 1022 already generates a needed value for filter portion 1020. The remainder of equation [12] is performed by elements 1070-1073 to yield the new value of r, i.e. r(i+1).

[0071] FIG. 11 illustrates a flow diagram 1100 of an acquisition of a reflection coefficient r and a delay coefficient D by coefficient estimator 320 of FIG. 3. The method starts at step 1102. Coefficient estimator 320 acquires an initial value of r labeled “r_INIT” at step 1104. Coefficient estimator 320 performs the r acquisition by searching for the lowest MSE as r varies, and selecting the value of r at the minimum MSE as r_INIT.

[0072] The inventor has discovered that the algorithm for acquiring r_INIT converges well to its approximate global minimum. Likewise coefficient estimator 320 performs the D acquisition by searching for the lowest MSE as D varies. However the algorithm does not converge well to its approximate global minimum because there are frequently multiple local minimums of the MSE as D varies. In order to overcome this problem, receiver 220 acquires an initial value of D by searching for a global minimum. The global minimum is a lowest one of the local minimums. Coefficient estimator 320 determines each local minimum by using a different starting values of D. The initial acquired value of D is thus a value of D at the global minimum. The remainder of flow chart 1100 details the D acquisition process.

[0073] Coefficient estimator 320, at step 1106, sets an initial value of index i to 0, and an initial value of D to D(i)=D(0). Then at step 1108 it finds a minimum MSE, designated “MSE(i)”, using adaptation techniques. Thus MSE(i) may be a local minimum or the global minimum. At step 1110, it determines whether the current MSE, i.e. MSE(i), is less than a previous lowest MSE labeled “MSE_MIN”. If so, then it sets MSE_MIN to MSE(i), but if not it keeps MSE_MIN at its previous value. If D=D(0), then it sets MSE_MIN to MSE(0). At step 1114 it increments the index variable i, and then sets D to be equal to the next starting value of D, D(i+1). At step 1116 it determines whether the last starting value of D has been tried. If not, it repeats steps 1108-1114. Once the last starting value of D has been tried, then at step 1118 it sets D_INIT as the value of D at MSE_MIN, and the acquisition ends at step 1120.

[0074] In the contemplated embodiment, D assumes integer values between −16 and +15. Method 1100 uses starting values of D of −12, −9, −6, −3, 0, 3, 6, 9, and 12 as i varies from 0 to 7.

[0075] During operation after D_INIT has been acquired, D is simply adapted from the current value of D using equation [11] so long as the MSE value in any one period is not too big compared to the previous MSE value. However if the MSE suddenly becomes large, i.e. when MSE(i+1)>k·MSE(i) in which k is a coefficient greater than 1, coefficient estimator 320 reacquires it using flow 1100.

[0076] Thus coefficient estimator 320 is able to estimate values of r and D efficiently using DSPs with a reasonable amount of circuit area, allowing a multipath equalizer to be implemented in a low cost integrated circuit. This efficient implementation is due to estimating partial derivative expressions using a limited number of terms. In the case of the D update, it requires just a single term. In the case of the r update, it requires only four terms. Moreover the most appropriate value of D is acquired even though the algorithm may not converge to the best value using normal binary searching techniques.

[0077] Note that DSP 342 is a DSP that is capable of executing a stored program using available instructions from its instruction repertoire. Thus the implementation of either digital filter 310 or coefficient estimator 320 is performed by a combination of DSP 252 and software or firmware. However in other embodiments, these functions could be performed by different combinations of hardware and software. Thus the FIGs. are to be understood as covering their respective functions regardless of which mechanism is chosen to perform this function.

[0078] Therefore the above-disclosed subject matter is to be considered illustrative, and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments that fall within the true scope of the claims. Thus, to the maximum extent allowed by law, the scope of the present invention is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.