Motherboard used in server computer

[0001] 1. Technical Field

[0002] The disclosure relates to computer devices and, particularly, to a motherboard used in a sever computer.

[0003] 2. Description of Related Art

[0004] A typical rack-type server computer or a tower-type server computer often includes a first central processing unit (CPU), a second CPU and an activating chip. The first CPU is directly connected to the activating chip. The second CPU is connected to the activating chip via the first CPU. The activating chip can activate the first CPU directly, or activate the first and second CPUs to work at the same time because of the connection between the first CPU and the second CPU. However, when the server is required to activate only the second CPU and not activate the first CPU, a very complicated change, such as changing the layout of the motherboard, is needed. This increases the cost of mass production of the server computer.

[0005] Therefore, it is desirable to provide a motherboard which can overcome the problems described above.

[0008] Referring to FIGS. 1 and 2, a motherboard 100 used in a server computer, according to an exemplary embodiment, includes a substrate 10, a first CPU socket 20 receiving a first CPU 21, a second CPU socket 30 receiving a second CPU 31, a switching circuit 40, a quick path interconnect (QPI) bus 50, an activating chip 60, a number of direct media interface (DMI) buses 70, a number of first peripheral component interconnect express (PCI-e) interfaces 80, a number of second PCI-e interfaces 90, a number of first wires 110, and a number of second wires 120.

[0009] The substrate 10 is typically a printed circuit board (PCB). The first CPU socket 20, the second CPU socket 30, the first PCI-e interfaces 80, the second PCI-e interfaces 90, the switching circuit 40, the QPI buses 50, the first wires 110, the second wires 120, and the activating chip 60 are all disposed on the substrate 10.

[0010] The first CPU socket 20 and the second CPU socket 30 are disposed on a same surface of the substrate 10 and are substantially parallel to each other. The activating chip 60 is disposed on one side of the first CPU socket 20. The first PCI-e interfaces 80 and the second PCI-e interfaces 90 are arranged parallel to each other. The first and second PCI-e interfaces 80, 90 are arranged at one side of the substrate 10, and the first and second CPU sockets 20, 30 are arranged at an opposite side of the substrate 10. The first CPU socket 20 is opposite to the first PCI-e interfaces 80, and the second CPU socket 30 is approximately opposite to the second PCI-e interfaces 90.

[0011] The QPI bus 50 electrically connects the first CPU socket 20 to the second CPU socket 30, and is configured for transmitting information between the first CPU 21 and the second CPU 31. The first CPU 21 is connected to the first PCI-e interfaces 80 via the first wires 110 and the first CPU socket 20. The second CPU 31 is connected to the second PCI-e interfaces 90 via the second CPU socket 30 and the second wires 120. In the present embodiment, the first PCI-e interfaces 80 include three 8-channel PCI-e interfaces 80a and four 4-channel PCI-e interfaces 80b. The second PCI-e interfaces 90 include a 24-channel PCI-e interface 90a and a 16-channel PCI-e interface 90b.

[0012] The activating chip 60 is connected to both of the first CPU 21 and the second CPU 31 via the switching circuit 40, and is configured for starting (i.e., activating) a peripheral device such as a Platform Controller Hub (PCH, not shown) connected to one of the first PCI-e interfaces 80 or one of the second PCI-e interfaces 90.

[0013] The switching circuit 40 is connected to the first CPU 21, the second CPU 31, and the activating chip 60 via three DMI buses 70. In the present embodiment, DMI v.2.0 buses are used. The switching circuit 40 includes a first transmission channel 41 and a second transmission channel 43. The second transmission channel 43 has a reversed state relative to the first transmission channel 41. That is, when the first transmission channel 41 is in an on-state, the second transmission channel 43 is in an off-state; and vice versa. The first transmission channel 41 is connected between the activating chip 60 and the first CPU 21. The second transmission channel 43 is connected between the activating chip 60 and the second CPU 31. It is understood that, in other embodiments, the switching circuit 40 may use a single-pole double-throw switch.

[0014] When the motherboard 100 serves as a rack-type server, the first transmission channel 41 connects the activating chip 60 to the first CPU 21 via a resister 45 disposed in the switch circuit 40. Thereby, the activating chip 60 starts the peripheral device connected to, e.g., one of the first PCI-e interfaces 80. When the motherboard 100 serves as a tower-type server, the second transmission channel 43 connects the activating chip 60 to the second CPU 31 via another resister 47 disposed in the switch circuit 40. Thereby, the activating chip 60 starts the peripheral device connected to the second PCI-e interfaces 90. Therefore the motherboard 100 can utilize the different first and second CPUs 21, 31 correspondingly and appropriately, according to the state of the switch circuit 40.

[0015] While various exemplary and preferred embodiments have been described, it is to be understood that the disclosure is not limited thereto. To the contrary, various modifications and similar arrangements (as would be apparent to those skilled in the art) are intended to also be covered. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and equivalents thereof.