US 8,247,276 B2Grant
Thin film transistor, method for manufacturing the same, and semiconductor device
Issue Date:2012-08-21
•20 Claims
•18 Drawing Sheets
Abstract
In a thin film transistor, an increase in off current or negative shift of the threshold voltage is prevented. In the thin film transistor, a buffer layer is provided between an oxide semiconductor layer and each of a source electrode layer and a drain electrode layer. The buffer layer includes a metal oxide layer which is an insulator or a semiconductor over a middle portion of the oxide semiconductor layer. The metal oxide layer functions as a protective layer for suppressing incorporation of impurities into the oxide semiconductor layer. Therefore, in the thin film transistor, an increase in off current or negative shift of the threshold voltage can be prevented.
Metadata
Assignee
- Semiconductor Energy Laboratory Co., Ltd.
Inventors
- Toshikazu Kondo
- Hideyuki Kishida
Application Information
Application Number:US 12/699,080
Filing Date:2010-02-03
Priority Date:2009-02-20
Art Unit:2893
Classifications
IPC:
H01L21/00
Patent Drawings (18 sheets)
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a thin film transistor formed using an oxide semiconductor layer, and a method for manufacturing the thin film transistor. In addition, the present invention relates to a semiconductor device manufactured using the thin film transistor.
[0003] Note that a semiconductor device in this specification indicates all the devices that can operate by using semiconductor characteristics, and electro-optical devices, semiconductor circuits, and electronic appliances are all included in the category of the semiconductor devices.
[0004] 2. Description of the Related Art
[0005] A wide variety of metal oxides exist and are used for various applications. Indium oxide is a well-known material and is used as a transparent electrode material needed for a liquid crystal display and the like.
[0006] Some metal oxides exhibit semiconductor characteristics. As metal oxides exhibiting semiconductor characteristics, for example, tungsten oxide, tin oxide, indium oxide, zinc oxide, and the like can be given. References disclose a thin film transistor in which such a metal oxide exhibiting semiconductor characteristics is used for a channel formation region (Patent Documents 1 to 4, and Non-Patent Document 1).
[0007] As metal oxides, multi-component oxides as well as single-component oxides are known. For example, InGaO3(ZnO)m (m is a natural number) belonging to homologous series has been known as a multi-component oxide semiconductor including In, Ga, and Zn (Non-Patent Documents 2 to 4).
[0008] In addition, it has been confirmed that an oxide semiconductor including such an In—Ga—Zn-based oxide can be used as a channel layer of a thin film transistor (Patent Document 5, and Non-Patent Documents 5 and 6).
REFERENCE
Patent Document
- [0009] [Patent Document 1] Japanese Published Patent Application No. S60-198861
- [0010] [Patent Document 2] Japanese Published Patent Application No. H8-264794
- [0011] [Patent Document 3] Japanese Translation of PCT International Application No. H11-505377
- [0012] [Patent Document 4] Japanese Published Patent Application No. 2000-150900
- [0013] [Patent Document 5] Japanese Published Patent Application No. 2004-103957
Non-Patent Document
- [0014] [Non-Patent Document 1] M. W. Prins, K. O. Grosse-Holz, G. Muller, J. F. M. Cillessen, J. B. Giesbers, R. P. Weening, and R. M. Wolf, “A ferroelectric transparent thin-film transistor”, Appl. Phys. Lett., 17 Jun. 1996, Vol. 68, pp. 3650-3652
- [0015] [Non-Patent Document 2] M. Nakamura, N. Kimizuka, and T. Mohri, “The Phase Relations in the In2O3—Ga2ZnO4—ZnO System at 1350° C.”, J. Solid State Chem., 1991, Vol. 93, pp. 298-315
- [0016] [Non-Patent Document 3] N. Kimizuka, M. Isobe, and M. Nakamura, “Syntheses and Single-Crystal Data of Homologous Compounds, In2O3(ZnO)m (m=3, 4, and 5), InGaO3(ZnO)3, and Ga2O3(ZnO)m (m=7, 8, 9, and 16) in the In2O3—ZnGa2O4—ZnO System”, J. Solid State Chem., 1995, Vol. 116, pp. 170-178
- [0017] [Non-Patent Document 4] M. Nakamura, N. Kimizuka, T. Mohri, and M. Isobe, “Syntheses and crystal structures of new homologous compounds, indium iron zinc oxides (InFeO3(ZnO)m) (m: natural number) and related compounds”, KOTAI BUTSURI (SOLID STATE PHYSICS), 1993, Vol. 28, No. 5, pp. 317-327
- [0018] [Non-Patent Document 5] K. Nomura, H. Ohta, K. Ueda, T. Kamiya, M. Hirano, and H. Hosono, “Thin-film transistor fabricated in single-crystalline transparent oxide semiconductor”, SCIENCE, 2003, Vol. 300, pp. 1269-1272
- [0019] [Non-Patent Document 6] K. Nomura, H. Ohta, A. Takagi, T. Kamiya, M. Hirano, and H. Hosono, “Room-temperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors”, NATURE, 2004, Vol. 432, pp. 488-492
SUMMARY OF THE INVENTION
[0020] An object of an embodiment of the present invention is to prevent, in a thin film transistor, an increase in off current or negative shift of the threshold voltage.
[0021] An object of an embodiment of the present invention is to realize ohmic contact between an oxide semiconductor layer and each of a source electrode layer and a drain electrode layer of a thin film transistor.
[0022] An object of an embodiment of the present invention is to efficiently manufacture a high-performance thin film transistor in which an increase in off current or negative shift of the threshold voltage is prevented.
[0023] An object of an embodiment of the present invention is to efficiently manufacture a high-performance thin film transistor in which an increase in off current or negative shift of the threshold voltage is prevented and which has ohmic contact between an oxide semiconductor layer and each of a source electrode layer and a drain electrode layer.
[0024] An object of an embodiment of the present invention is to provide a semiconductor device with high performance or high reliability.
[0025] An embodiment of the present invention is an inverted staggered thin film transistor in which a buffer layer is provided over an oxide semiconductor layer and a source electrode layer and a drain electrode layer are provided over the buffer layer. Note that the buffer layer includes a pair of conductive layers provided over opposite end portions of the oxide semiconductor layer, and a metal oxide layer which is provided over a middle portion of the oxide semiconductor layer, has the same metal element as the pair of conductive layers, has higher oxygen concentration than the pair of conductive layers, and is an insulator or a semiconductor provided between the pair of conductive layers.
[0026] Another embodiment of the present invention is a thin film transistor which has the above structure and in which the buffer layer includes a pair of oxide semiconductor layers whose oxygen concentration is lowered and which are provided over opposite end portions of the oxide semiconductor layer, and a pair of conductive layers containing oxygen at high concentration and provided over the pair of oxide semiconductor layers whose oxygen concentration is lowered.
[0027] Note that in this specification, the term “insulator” means a substance whose electrical resistivity is greater than or equal to 106 (Ω·m), the term “semiconductor” means a substance whose electrical resistivity is greater than or equal to 10−3 (Ω·m) and less than 106 (Ω·m), and the term “conductor” means a substance whose electrical resistivity is less than 10−3 (Ω·m).
[0028] Another embodiment of the present invention is a method for manufacturing a thin film transistor in which a metal oxide layer is formed by performing oxidation treatment on a conductive layer formed in the same step as an oxide semiconductor layer. Note that in the oxidation treatment, a resist used for forming a source electrode layer and a drain electrode layer is used as a mask. Therefore, opposite end portions of the conductive layer remain without being oxidized by the oxidation treatment. As a result, through the oxidation treatment, a pair of conductive layers and a metal oxide layer provided between the pair of conductive layers are formed.
[0029] Another embodiment of the present invention is a method for manufacturing a thin film transistor in which a metal oxide layer is formed by performing oxidation treatment on a conductive layer formed in the same step as an oxide semiconductor layer, and then, a pair of conductive layers containing oxygen at high concentration and a pair of oxide semiconductor layers whose oxygen concentration is lowered are formed by diffusing oxygen through thermal treatment.
[0030] Another embodiment of the present invention is a method for manufacturing a thin film transistor in which a metal oxide layer, a pair of conductive layers containing oxygen at high concentration, and a pair of oxide semiconductor layers whose oxygen concentration is lowered are formed through thermal oxidation treatment.
[0031] Another embodiment of the present invention is a method for manufacturing a thin film transistor in which a metal oxide layer, a pair of conductive layers containing oxygen at high concentration, and a pair of oxide semiconductor layers whose oxygen concentration is lowered are formed through oxidation treatment and thermal oxidation treatment.
[0032] Another embodiment of the present invention is a semiconductor device including the thin film transistor, and an interlayer insulating layer provided over the thin film transistor.
[0033] An embodiment of the present invention is an inverted staggered thin film transistor including a metal oxide layer which is an insulator or a semiconductor over a middle portion of an oxide semiconductor layer. The metal oxide layer functions as a protective layer for suppressing incorporation of impurities (such as hydrogen and moisture) into the oxide semiconductor layer. Therefore, in the thin film transistor, an increase in off current or negative shift of the threshold voltage can be prevented.
[0034] Another embodiment of the present invention is an inverted staggered thin film transistor including a pair of conductive layers containing oxygen at high concentration and a pair of oxide semiconductor layers whose oxygen concentration is lowered, between opposite end portions of an oxide semiconductor layer and a pair of conductive layers provided over the opposite end portions of the oxide semiconductor layer. The pair of oxide semiconductor layers whose oxygen concentration is lowered has lower resistance than the oxide semiconductor layer. Therefore, ohmic contact between the oxide semiconductor layer and each of a source electrode layer and a drain electrode layer can be obtained.
[0035] In another embodiment of the present invention, the metal oxide layer is formed on the basis of a conductive layer which is formed in the same step as the oxide semiconductor layer. Therefore, a high-performance thin film transistor can be efficiently formed.
[0036] In another embodiment of the present invention, the metal oxide layer is formed on the basis of a conductive layer which is formed in the same step as the oxide semiconductor layer, and the pair of oxide semiconductor layers whose oxygen concentration is lowered is formed by diffusing oxygen into the conductive layer. Therefore, a high-performance thin film transistor can be efficiently formed.
[0037] In another embodiment of the present invention, a thin film transistor including a protective layer for suppressing incorporation of impurities (such as hydrogen and moisture) into an oxide semiconductor layer is applied to a thin film transistor included in a semiconductor device. Accordingly, a material and a manufacturing method of an interlayer insulating layer provided over the thin film transistor can be selected depending on the purpose. That is, a semiconductor device with high performance or high reliability can be provided.
BRIEF DESCRIPTION OF THE DRAWINGS
[0038] FIGS. 1A and 1B are cross-sectional views each illustrating a thin film transistor described in Embodiment 1.
[0039] FIGS. 2A to 2D are cross-sectional views illustrating a manufacturing process of a thin film transistor described in Embodiment 2.
[0040] FIGS. 3A to 3D are cross-sectional views illustrating a manufacturing process of a thin film transistor described in Embodiment 2.
[0041] FIG. 4 is a top view illustrating a pixel of a liquid crystal display device described in Embodiment 3.
[0042] FIG. 5 is a cross-sectional view illustrating a pixel of a liquid crystal display device described in Embodiment 3.
[0043] FIG. 6 is an equivalent circuit diagram illustrating a pixel of a liquid crystal display device described in Embodiment 3.
[0044] FIG. 7 is a top view illustrating a pixel of a light-emitting display device described in Embodiment 4.
[0045] FIG. 8 is a cross-sectional view illustrating a pixel of a light-emitting display device described in Embodiment 4.
[0046] FIG. 9 is an equivalent circuit diagram illustrating a pixel of a light-emitting display device described in Embodiment 4.
[0047] FIG. 10 is a cross-sectional view illustrating an electronic paper described in Embodiment 5.
[0048] FIGS. 11A to 11C are graphs each showing density of a state obtained by calculation described in Example 1.
[0049] FIGS. 12A to 12C are graphs each showing density of a state obtained by calculation described in Example 1.
[0050] FIGS. 13A and 13B are graphs each showing density of a state obtained by calculation described in Example 1.
[0051] FIGS. 14A and 14B are diagrams showing atomic arrangement before and after thermal treatment at a bonding interface between a titanium layer and an In—Ga—Zn—O-based oxide semiconductor layer, which are obtained by calculation described in Example 1.
[0052] FIG. 15 is a graph showing titanium concentration and oxygen concentration before and after thermal treatment at a bonding interface between a titanium layer and an In—Ga—Zn—O-based oxide semiconductor layer, which are obtained by calculation described in Example 1.
[0053] FIGS. 16A and 16B are diagrams showing atomic arrangement before and after thermal treatment at a bonding interface between a titanium oxide layer and an In—Ga—Zn—O-based oxide semiconductor layer, which are obtained by calculation described in Example 1.
[0054] FIG. 17 is a graph showing titanium concentration and oxygen concentration before and after thermal treatment at a bonding interface between a titanium oxide layer and an In—Ga—Zn—O-based oxide semiconductor layer, which are obtained by calculation described in Example 1.
DETAILED DESCRIPTION OF THE INVENTION
[0055] Embodiments and an example of the present invention will be hereinafter described in detail with reference to the accompanying drawings. However, the present invention is not limited to the description below, and those skilled in the art will appreciate that a variety of modifications can be made to the modes and details without departing from the spirit and scope of the present invention. Therefore, the present invention is not construed as being limited to description of embodiments and an example below.
[0056] Note that the size, the thickness of a layer, or a region of each structure illustrated in drawings or the like in embodiments is exaggerated for simplicity in some cases. Therefore, the scale is not necessarily limited to that illustrated in the drawings or the like. Further, in this specification, ordinal numbers such as “first”, “second”, and “third” are used in order to avoid confusion among components, and the terms do not limit the components numerically.
Embodiment 1
[0057] In this embodiment, a structure of a thin film transistor which is one embodiment of the present invention will be described with reference to FIGS. 1A and 1B . Next, characteristics of the thin film transistor will be described.
[0058] FIG. 1A illustrates a cross-sectional view of a thin film transistor 150 formed over a substrate 100. The thin film transistor 150 includes a gate electrode layer 101 provided over the substrate 100, a gate insulating layer 102 provided over the gate electrode layer 101, an oxide semiconductor layer 103 provided over the gate insulating layer 102, a buffer layer 106 provided over the oxide semiconductor layer 103 and including a pair of conductive layers 104a and 104b which are conductors and a metal oxide layer 105 which is an insulator or a semiconductor, a source electrode layer 107a provided over the conductive layer 104a (one of the pair of conductive layers 104a and 104b), and a drain electrode layer 107b provided over the conductive layer 104b (the other of the pair of conductive layers 104a and 104b). Note that the pair of conductive layers 104a and 104b is provided over opposite end portions of the oxide semiconductor layer 103, and the metal oxide layer 105 is provided over a middle portion of the oxide semiconductor layer 103.
[0059] In other words, the thin film transistor 150 in FIG. 1A is an inverted staggered thin film transistor including the buffer layer 106 which includes the pair of conductive layers 104a and 104b and the metal oxide layer 105 and is provided between the oxide semiconductor layer 103 and each of the source electrode layer 107a and the drain electrode layer 107b.
[0060] FIG. 1B illustrates a cross-sectional view of a thin film transistor 151 formed over a substrate. The thin film transistor 151 has a structure of the thin film transistor 150 in FIG. 1A . In addition, the thin film transistor 151 includes a pair of oxide semiconductor layers 108a and 108b whose oxygen concentration is lowered and which are provided over the opposite end portions of the oxide semiconductor layer 103, and a pair of conductive layers 109a and 109b containing oxygen at high concentration and provided over the pair of oxide semiconductor layers 108a and 108b whose oxygen concentration is lowered.
[0061] In other words, the thin film transistor 151 in FIG. 1B is an inverted staggered thin film transistor including a buffer layer 110 which is provided between the oxide semiconductor layer 103 and each of the source electrode layer 107a and the drain electrode layer 107b. The buffer layer 110 includes the pair of conductive layers 104a and 104b, the metal oxide layer 105, the pair of oxide semiconductor layers 108a and 108b whose oxygen concentration is lowered, and the pair of conductive layers 109a and 109b containing oxygen at high concentration.
[0062] As the substrate 100, a glass substrate such as barium borosilicate glass or aluminoborosilicate glass or the like can be used.
[0063] As the gate electrode layer 101, an element selected from aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc), an alloy containing any of these elements, or a nitride containing any of these elements can be used. A stacked structure of these materials can also be used.
[0064] As the gate insulating layer 102, an insulator such as silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, or tantalum oxide can be used. Alternatively, a stacked structure of these insulators can be used. Note that silicon oxynitride refers to a substance which contains more oxygen than nitrogen and contains oxygen, nitrogen, silicon, and hydrogen at given concentrations ranging from 55 atomic % to 65 atomic %, 1 atomic % to 20 atomic %, 25 atomic % to 35 atomic %, and 0.1 atomic % to 10 atomic %, respectively, where the total percentage of atoms is 100 atomic %. Further, silicon nitride oxide refers to a substance which contains more nitrogen than oxygen and contains oxygen, nitrogen, silicon, and hydrogen at given concentrations ranging from 15 atomic % to 30 atomic %, 20 atomic % to 35 atomic %, 25 atomic % to 35 atomic %, and 15 atomic % to 25 atomic %, respectively, where the total percentage of atoms is 100 atomic %.
[0065] As the oxide semiconductor layer 103, an oxide semiconductor such as an In—Ga—Zn—O-based oxide semiconductor, an In—Sn—Zn—O-based oxide semiconductor, an In—Zn—O-based oxide semiconductor, a Sn—Zn—O-based oxide semiconductor, an In—Sn—O-based oxide semiconductor, a Ga—Zn—O-based oxide semiconductor, or a Zn—O-based oxide semiconductor can be used. Alternatively, an oxide semiconductor formed by adding nitrogen (N) or silicon (Si) to any of the above oxide semiconductors can be used. A stacked structure of these materials can also be used.
[0066] As the pair of conductive layers 104a and 104b, titanium (Ti), copper (Cu), zinc (Zn), aluminum (Al), or the like can be used. Alternatively, an alloy containing any of these metal elements can be used. A stacked structure of these materials can also be used.
[0067] As the metal oxide layer 105, the same material as the pair of conductive layers 104a and 104b can be used. Note that the metal oxide layer 105 has higher oxygen concentration than the pair of conductive layers 104a and 104b. That is, the metal oxide layer 105 contains the same metal element as the pair of conductive layers 104a and 104b, and has higher oxygen concentration than the pair of conductive layers 104a and 104b.
[0068] As the source electrode layer 107a and the drain electrode layer 107b, an element selected from aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc), an alloy containing any of these elements, or a nitride containing any of these elements can be used. A stacked structure of these materials can also be used.
[0069] As the pair of oxide semiconductor layers 108a and 108b whose oxygen concentration is lowered, the same material as the oxide semiconductor layer 103 can be used. Note that the pair of oxide semiconductor layers 108a and 108b whose oxygen concentration is lowered has lower oxygen concentration than the oxide semiconductor layer 103. That is, the pair of oxide semiconductor layers 108a and 108b whose oxygen concentration is lowered contains the same metal element as the oxide semiconductor layer 103, and has lower oxygen concentration than the oxide semiconductor layer 103.
[0070] As the pair of conductive layers 109a and 109b containing oxygen at high concentration, the same material as the pair of conductive layers 104a and 104b and the metal oxide layer 105 can be used. Note that the pair of conductive layers 109a and 109b containing oxygen at high concentration has higher oxygen concentration than the pair of conductive layers 104a and 104b, and has lower oxygen concentration than the metal oxide layer 105. That is, the pair of conductive layers 109a and 109b containing oxygen at high concentration contains the same metal element as the pair of conductive layers 104a and 104b and the metal oxide layer 105, and has higher oxygen concentration than the pair of conductive layers 104a and 104b and lower oxygen concentration than the metal oxide layer 105.
[0071] The thin film transistor 150 in FIG. 1A includes the buffer layer 106 between the oxide semiconductor layer 103 and each of the source electrode layer 107a and the drain electrode layer 107b. The buffer layer 106 includes the metal oxide layer 105, which is the insulator or the semiconductor, over the middle portion of the oxide semiconductor layer 103. The metal oxide layer 105 functions as a protective layer for suppressing incorporation of impurities (such as hydrogen and moisture) into the oxide semiconductor layer 103. Therefore, in the thin film transistor 150, an increase in off current or negative shift of the threshold voltage can be prevented.
[0072] The buffer layer 110 of the thin film transistor 151 in FIG. 1B includes the metal oxide layer 105 for preventing an increase in off current or negative shift of the threshold voltage, and the pair of oxide semiconductor layers 108a and 108b whose oxygen concentration is lowered and which are provided over the opposite end portions of the oxide semiconductor layer 103. The pair of oxide semiconductor layers 108a and 108b whose oxygen concentration is lowered has lower resistance than the oxide semiconductor layer 103. Therefore, ohmic contact between the oxide semiconductor layer 103 and each of the source electrode layer 107a and the drain electrode layer 107b can be obtained.
Embodiment 2
[0073] In this embodiment, one example of a method for manufacturing the thin film transistor described in Embodiment 1 will be described with reference to FIGS. 2A to 2D and FIGS. 3A to 3D .
[0074] Note that in this embodiment, the term “film” means something which is formed over the entire surface of a substrate and is to be processed into a desired shape in a subsequent photolithography step or the like, and something before the processing. The term “layer” means something obtained by processing and shaping a “film” into a desired shape by a photolithography step or the like, or something to be formed over the entire surface of a substrate.
[0075] A first conductive film 201 is formed over a substrate 200. The first conductive film 201 can be formed by a thin film deposition method typified by a sputtering method, a vacuum evaporation method, a pulsed laser deposition method, an ion plating method, a metal organic chemical vapor deposition method, or the like. Next, a first resist 202 is formed over the first conductive film 201. FIG. 2A is a cross-sectional view after the above steps are completed.
[0076] Next, with use of the first resist 202 as a mask, the first conductive film 201 is selectively etched to form a gate electrode layer 203. Note that the materials described in Embodiment 1 can be used for the substrate 200 and the first conductive film 201 (the gate electrode layer 203); therefore, here, the above description is to be referred to. The first resist 202 is removed after the gate electrode layer 203 is formed. FIG. 2B is a cross-sectional view after the above steps are completed.
[0077] Next, a gate insulating layer 204 is formed over the substrate 200 and the gate electrode layer 203. The gate insulating layer 204 can be formed by a thin film deposition method typified by a sputtering method, a vacuum evaporation method, a pulsed laser deposition method, an ion plating method, a metal organic chemical vapor deposition method, a plasma CVD method, or the like.
[0078] Next, an oxide semiconductor film 205 is formed. The oxide semiconductor film 205 can be formed by a thin film deposition method typified by a sputtering method, a vacuum evaporation method, a pulsed laser deposition method, an ion plating method, a metal organic chemical vapor deposition method, or the like. In the case where an In—Ga—Zn—O-based oxide semiconductor film is formed by a sputtering method, it is preferable to use a target made by sintering In2O3, Ga2O3, and ZnO. As a sputtering gas, a rare gas typified by argon is used. One example of the formation conditions by sputtering is as follows: a target made by mixing and sintering In2O3, Ga2O3, and ZnO (1:1:1) is used; the pressure is 0.4 Pa; the direct current (DC) power source is 500 W; the flow rate of an argon gas is 30 sccm; and the flow rate of an oxygen gas is 15 sccm. After the oxide semiconductor film 205 is formed, thermal treatment is preferably performed at 100° C. to 600° C., typically 200° C. to 400° C. Through this thermal treatment, rearrangement at the atomic level occurs in the oxide semiconductor film. The thermal treatment (including optical annealing) is important because strain energy which inhibits carrier movement in the oxide semiconductor film 205 is released by the thermal treatment.
[0079] Next, a second conductive film 206 is formed over the oxide semiconductor film 205. The second conductive film 206 can be formed by a thin film deposition method typified by a sputtering method, a vacuum evaporation method, a pulsed laser deposition method, an ion plating method, a metal organic chemical vapor deposition method, or the like. As a material for the second conductive film 206, titanium (Ti), copper (Cu), zinc (Zn), aluminum (Al), or the like can be used. Alternatively, an alloy containing any of these metal elements can be used. A stacked structure of these materials can also be used. Next, a second resist 207 is formed over the second conductive film 206. FIG. 2C is a cross-sectional view after the above steps are completed.
[0080] Next, with use of the second resist 207 as a mask, the oxide semiconductor film 205 and the second conductive film 206 are selectively etched to form an oxide semiconductor layer 208 and a conductive layer 209. Note that the materials described in Embodiment 1 can be used for the gate insulating layer 204 and the oxide semiconductor film 205 (the oxide semiconductor layer 208); therefore, here, the above description is to be referred to. The second resist 207 is removed after the oxide semiconductor layer 208 and the conductive layer 209 are formed. FIG. 2D is a cross-sectional view after the above steps are completed.
[0081] Next, a third conductive film 210 is formed over the gate insulating layer 204 and the conductive layer 209. The third conductive film 210 can be formed by a thin film deposition method typified by a sputtering method, a vacuum evaporation method, a pulsed laser deposition method, an ion plating method, a metal organic chemical vapor deposition method, or the like. Next, third resists 211a and 211b are formed over the third conductive film 210. FIG. 3A is a cross-sectional view after the above steps are completed.
[0082] Next, with use of the third resists 211a and 211b as masks, the third conductive film 210 is selectively etched to form a source electrode layer 212a and a drain electrode layer 212b. Note that through this etching step, a region (an exposed portion) of the conductive layer 209, which does not overlap with the source electrode layer 212a or the drain electrode layer 212b, is partly etched, whereby a conductive layer 213 having a recessed portion in the region (the exposed portion), which does not overlap with the source electrode layer 212a or the drain electrode layer 212b, is formed. Note that the materials described in Embodiment 1 can be used for the third conductive film 210 (the source electrode layer 212a and the drain electrode layer 212b); therefore, here, the above description is to be referred to. FIG. 3B is a cross-sectional view after the above steps are completed.
[0083] Next, with use of the third resists 211a and 211b as masks, oxidation treatment is performed. As the oxidation treatment, thermal oxidation treatment in an oxidizing atmosphere, plasma oxidation treatment, oxygen ion implantation, or the like can be used. It is possible to perform plural kinds of such treatment in combination; for example, thermal oxidation treatment in an oxidizing atmosphere is performed, and then, plasma oxidation treatment is performed. Note that as the oxidizing atmosphere in which the thermal oxidation treatment is performed, a dried oxygen atmosphere, a mixed atmosphere of oxygen and a rare gas, an atmospheric atmosphere, or the like can be used. Through the oxidation treatment, a middle portion (an exposed portion) of the conductive layer 213 provided over the oxide semiconductor layer 208 is oxidized to form a metal oxide layer 214 which is an insulator or a semiconductor. Further, at the same time as the formation of the metal oxide layer 214, a pair of conductive layers 215a and 215b is formed over opposite end portions of the oxide semiconductor layer 208. Specifically, by the source electrode layer 212a, the drain electrode layer 212b, and the third resists 211a and 211b, a region (a non-exposed portion) of the conductive layer 213, which overlaps with the source electrode layer 212a or the drain electrode layer 212b, is prevented from being oxidized. As a result, the pair of conductive layers 215a and 215b remains. Note that the volume of the region oxidized through the oxidation treatment is increased. That is, the volume of the metal oxide layer 214 is larger than that of the middle portion of the conductive layer 213 before being oxidized. FIG. 3C is a cross-sectional view after the above steps are completed. Through the steps described above, the thin film transistor 150 illustrated in FIG. 1A is completed.
[0084] Note that the thin film transistor of this embodiment is not limited to have the structure of FIG. 1A or FIG. 3C . Specifically, the thin film transistor having such a structure that only the region (the middle portion) of the conductive layer 213, which does not overlap with the source electrode layer 212a or the drain electrode layer 212b, is oxidized through the oxidation treatment to form the metal oxide layer 214 is illustrated in FIG. 1A and FIG. 3C ; however, a thin film transistor in which another region is also oxidized is also included in the category of the thin film transistor of this embodiment. For example, a thin film transistor having such a structure that side portions of the source electrode layer 212a and the drain electrode layer 212b, which are not covered with the third resists 211a and 211b, respectively, are oxidized through the oxidation treatment is also included in the category of the thin film transistor of this embodiment. Note that in the case where the side portions of the source electrode layer 212a and the drain electrode layer 212b are oxidized, the oxidation is performed on only surfaces of the side portions of the source electrode layer 212a and the drain electrode layer 212b, whereby the source electrode layer 212a and the drain electrode layer 212b can function as electrodes. Similarly, a thin film transistor having such a structure that the region (the non-exposed portion) of the conductive layer 213, which overlaps with the source electrode layer 212a or the drain electrode layer 212b, is partly internally oxidized is also included in the category of the thin film transistor of this embodiment.
[0085] The thin film transistor in which the thickness of the metal oxide layer 214 formed through the oxidation treatment is larger than that of the pair of conductive layers 215a and 215b is illustrated in FIG. 1A and FIG. 3C ; however, a thin film transistor in which the thickness of the metal oxide layer 214 is smaller than that of the pair of conductive layers 215a and 215b is also included in the category of the thin film transistor of this embodiment. Note that the metal oxide layer 214 is formed by performing oxidation treatment on the conductive layer 213 having the recessed portion. The recessed portion is formed in the etching step for forming the source electrode layer 212a and the drain electrode layer 212b. That is, the condition of the etching step for forming the source electrode layer 212a and the drain electrode layer 212b is adjusted, whereby the thickness of the metal oxide layer 214 can be adjusted. Specifically, the time of overetching for forming the source electrode layer 212a and the drain electrode layer 212b is prolonged, whereby the recessed portion can be deepened. Accordingly, the thickness of the metal oxide layer 214 can be smaller than that of the pair of conductive layers 215a and 215b.
[0086] In the case where the thin film transistor 151 in FIG. 1B is manufactured, thermal treatment at 100° C. to 600° C., typically 200° C. to 400° C. is performed in a subsequent step. Through the thermal treatment, oxygen in the oxide semiconductor layer 208 is diffused into the pair of conductive layers 215a and 215b. Note that when diffusion of oxygen into the pair of conductive layers 215a and 215b is compared with diffusion of oxygen into the metal oxide layer 214, the amount of oxygen diffused into the pair of conductive layers 215a and 215b is larger than that into the metal oxide layer 214. Therefore, a pair of oxide semiconductor layers 216a and 216b whose oxygen concentration is lowered is formed over the opposite end portions of the oxide semiconductor layer 208, and a pair of conductive layers 217a and 217b containing oxygen at high concentration is formed over the pair of oxide semiconductor layers 216a and 216b whose oxygen concentration is lowered. After that, the third resists 211a and 211b are removed. FIG. 3D is a cross-sectional view after the above steps are completed.
[0087] Here, the manufacturing step in which thermal treatment performed in the case where the thin film transistor 151 in FIG. 1B is manufactured is performed after oxidation treatment is described; however, the timing of the thermal treatment is not particularly limited as long as it is after formation of the second conductive film 206. This thermal treatment also allows rearrangement at the atomic level in the oxide semiconductor layer 208.
[0088] In terms of characteristics of a thin film transistor to be formed, thermal treatment is preferably performed after oxidation treatment. This is because when thermal treatment is performed before oxidation treatment (before formation of the metal oxide layer 214), oxide semiconductor layers whose oxygen concentration is lowered are formed not only in upper portions of the opposite end portions of the oxide semiconductor layer 208 but also over the entire area of the oxide semiconductor layer 208; thus, off current of a thin film transistor to be formed is increased.
[0089] In addition, in terms of a manufacturing process, as the oxidation treatment, thermal oxidation treatment is preferably performed in an oxidizing atmosphere at a temperature at which the pair of oxide semiconductor layers 216a and 216b whose oxygen concentration is lowered and the pair of conductive layers 217a and 217b containing oxygen at high concentration are formed. This is because the metal oxide layer 214, the pair of oxide semiconductor layers 216a and 216b whose oxygen concentration is lowered, and the pair of conductive layers 217a and 217b containing oxygen at high concentration can be formed in the same step. One example of conditions for treatment serving as the oxidation treatment and the thermal treatment is thermal oxidation treatment at 350° C. for one hour in a dried oxygen atmosphere.
[0090] Further, in terms of reliability of a thin film transistor to be formed, thermal oxidation treatment and oxidation treatment are preferably performed in combination. When the thickness of the metal oxide layer 214 is made larger, a function as a protective layer for suppressing incorporation of impurities (such as hydrogen and moisture) into the oxide semiconductor layer 208 can be improved.
[0091] In the thin film transistor 150, the metal oxide layer 214 having a function of preventing an increase in off current or negative shift of the threshold voltage is formed on the basis of the conductive layer 209 (the conductive layer 213) which is formed in the same step as the oxide semiconductor layer 208; therefore, a high-performance thin film transistor can be efficiently formed. In a similar manner, in the thin film transistor 151, the metal oxide layer 214 having a function of preventing an increase in off current or negative shift of the threshold voltage is formed on the basis of the conductive layer 209 (the conductive layer 213) which is formed in the same step as the oxide semiconductor layer 208, and the pair of oxide semiconductor layers 216a and 216b whose oxygen concentration is lowered and which have a function of realizing ohmic contact between the oxide semiconductor layer 208 and each of the source electrode layer 212a and the drain electrode layer 212b is formed by diffusing oxygen into the pair of conductive layers 215a and 215b; therefore, a high-performance thin film transistor can be efficiently formed.
Embodiment 3
[0092] In this embodiment, one example of a semiconductor device in which the thin film transistor described in Embodiment 1 is used will be described. Specifically, a liquid crystal display device in which the thin film transistor is used as a thin film transistor provided in a pixel portion of an active matrix substrate will be described with reference to FIG. 4 , FIG. 5 , and FIG. 6 . Next, the liquid crystal display device will be described.
[0093] Note that in a semiconductor device, since a source and a drain of a thin film transistor are switched with each other depending on the operating condition or the like, it is difficult to determine which is the source or the drain. Therefore, in this embodiment and the following embodiments, one of a source electrode layer and a drain electrode layer is referred to as a first electrode layer and the other thereof is referred to as a second electrode layer for distinction.
[0094] FIG. 4 is a top view illustrating one pixel of an active matrix substrate. Three sub-pixels are included in a pixel of a liquid crystal display device of this embodiment. Each sub-pixel is provided with a thin film transistor 300 and a pixel electrode 301 for applying voltage to a liquid crystal layer. The thin film transistor described in Embodiment 1 can be applied to the thin film transistor 300 in FIG. 4 . In a pixel portion, a plurality of pixels described above are provided. In addition, a plurality of gate wirings 302, a plurality of source wirings 303, and a plurality of capacitor wirings 304 are provided.
[0095] FIG. 5 is a cross-sectional view taken along line A-B of FIG. 4 . A thin film transistor 450 in FIG. 5 is the thin film transistor in FIG. 1A . That is, the thin film transistor 450 includes a gate electrode layer 401 provided over a substrate 400, a gate insulating layer 402 provided over the gate electrode layer 401, an oxide semiconductor layer 403 provided over the gate insulating layer 402, a buffer layer 406 including a pair of conductive layers 404a and 404b and a metal oxide layer 405 and provided over the oxide semiconductor layer 403, a first electrode layer 407a provided over the conductive layer 404a, and a second electrode layer 407b provided over the conductive layer 404b.
[0096] The materials described in Embodiment 1 and the manufacturing method described in Embodiment 2 can be applied to the substrate 400, the gate electrode layer 401, the gate insulating layer 402, the oxide semiconductor layer 403, the conductive layer 404a, the conductive layer 404b, the metal oxide layer 405, the buffer layer 406, the first electrode layer 407a, and the second electrode layer 407b; therefore, here, the above description is to be referred to.
[0097] The sub-pixel includes a capacitor 451. The capacitor 451 includes a capacitor wiring 408 formed from the same material as the gate electrode layer 401 of the thin film transistor 450, the gate insulating layer 402, and the second electrode layer 407b of the thin film transistor 450, which extends to the sub-pixel.
[0098] An interlayer insulating layer 409 is provided over the thin film transistor 450 and the capacitor 451. The thin film transistor 450 in FIG. 5 is provided with the metal oxide layer 405 for suppressing incorporation of impurities (such as hydrogen and moisture) into the oxide semiconductor layer 403; therefore, various materials and manufacturing methods can be used for the interlayer insulating layer 409. For example, as the interlayer insulating layer 409, a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer, a silicon nitride oxide layer, or the like can be formed by a plasma CVD method or a sputtering method. Further, the interlayer insulating layer 409 can also be formed by an application method such as a spin coating method, using an organic material such as polyimide, polyamide, polyvinylphenol, benzocyclobutene, acrylic, or epoxy; a siloxane material such as a siloxane resin; an oxazole resin; or the like. Note that a siloxane material corresponds to a material having a Si—O—Si bond. Siloxane has a skeleton structure with a bond of silicon (Si) and oxygen (O). As a substituent, an organic group (e.g., an alkyl group or aromatic hydrocarbon) or a fluoro group may be used. The organic group may include a fluoro group. The second electrode layer 407b in the thin film transistor 450 is electrically connected to a pixel electrode 411 through a contact hole 410 provided in the interlayer insulating layer 409.
[0099] FIG. 6 is an equivalent circuit diagram corresponding to the sub-pixel in FIG. 4 . A gate electrode of a thin film transistor 500 is electrically connected to a gate wiring 501, and a first electrode of the thin film transistor 500 is electrically connected to a source wiring 502. One electrode of a capacitor 503 is electrically connected to a second electrode of the thin film transistor 500, and the other electrode of the capacitor 503 is electrically connected to a capacitor wiring 504. A liquid crystal layer 505 to which voltage is applied through a pixel electrode is electrically connected to the second electrode of the thin film transistor 500 and to one electrode of the capacitor 503.
[0100] A liquid crystal display device includes a liquid crystal layer provided between an active matrix substrate and a counter substrate provided with a counter electrode on its surface. Alignment of liquid crystal molecules included in the liquid crystal layer is controlled by voltage applied between a pixel electrode of the active matrix substrate and the counter electrode of the counter substrate. The liquid crystal molecules of the liquid crystal layer are aligned to transmit or block light emitted from a backlight, whereby the liquid crystal display device can display images. In the liquid crystal display device, a thin film transistor in a pixel portion of the active matrix substrate is a switching element which controls voltage applied to the liquid crystal layer.
[0101] In the liquid crystal display device of this embodiment, the thin film transistor 450 in which the metal oxide layer 405 is provided over the oxide semiconductor layer 403 is used as a thin film transistor in a pixel portion of an active matrix substrate. The metal oxide layer 405 functions as a protective layer for suppressing incorporation of impurities (such as hydrogen and moisture) into the oxide semiconductor layer 403. Therefore, the material and manufacturing method of the interlayer insulating layer 409 can be selected depending on the purpose. As a result, a liquid crystal display device with high performance or high reliability can be provided. Note that the liquid crystal display device to which the thin film transistor in FIG. 1A is applied is described here; however, the same effect can be obtained also in the case where the thin film transistor in FIG. 1B is applied.
Embodiment 4
[0102] In this embodiment, one example of a semiconductor device in which the thin film transistor described in Embodiment 1 is used will be described. Specifically, a light-emitting display device in which the thin film transistor is applied to a thin film transistor provided in a pixel portion of an active matrix substrate will be described with reference to FIG. 7 , FIG. 8 , and FIG. 9 . Next, a light-emitting display device of this embodiment will be described. Note that as a display element included in the light-emitting display device of this embodiment, a light-emitting element utilizing electroluminescence is described here. Light-emitting elements utilizing electroluminescence are classified according to whether a light-emitting material is an organic compound or an inorganic compound. In general, the former is referred to as organic EL elements and the latter as inorganic EL elements.
[0103] In an organic EL element, by application of voltage to a light-emitting element, electrons and holes are separately injected from a pair of electrodes into a layer containing a light-emitting organic compound, and current flows. Then, recombination of these carriers (the electrons and holes) causes the light-emitting organic compound to form an excited state and to emit light when it returns from the excited state to a ground state. Due to such a mechanism, such a light-emitting element is referred to as a current-excitation light-emitting element.
[0104] Inorganic EL elements are classified into a dispersion type inorganic EL element and a thin-film type inorganic EL element, depending on their element structures. A dispersion type inorganic EL element has a light-emitting layer where particles of a light-emitting material are dispersed in a binder, and its light emission mechanism is donor-acceptor recombination type light emission that utilizes a donor level and an acceptor level. A thin-film type inorganic EL element has a structure where a light-emitting layer is sandwiched between dielectric layers, which are further sandwiched between electrodes, and its light emission mechanism is localized type light emission that utilizes inner-shell electron transition of metal ions. Note that description is made here using an organic EL element as a light-emitting element.
[0105] FIG. 7 is a top view illustrating one pixel of an active matrix substrate. Three sub-pixels are included in a pixel of a light-emitting display device of this embodiment. Each sub-pixel is provided with thin film transistors 600 and 601 and a pixel electrode 602 for applying voltage to a light-emitting element (part of the pixel electrode 602 is not illustrated for convenience). The thin film transistor described in Embodiment 1 can be applied to the thin film transistors 600 and 601 in FIG. 6 . A plurality of pixels described above are provided in a pixel portion. In addition, a plurality of gate wirings 603, a plurality of source wirings 604, and a plurality of power supply lines 605 are provided. Note that the power supply line 605 is set to have a high power supply potential VDD.
[0106] FIG. 8 is a cross-sectional view taken along lines C-D and E-F of FIG. 7 . Thin film transistors 750 and 751 each correspond to the thin film transistor in FIG. 1A . That is, the thin film transistors 750 and 751 each include a gate electrode layer 701 provided over a substrate 700, a gate insulating layer 702 provided over the gate electrode layer 701, an oxide semiconductor layer 703 provided over the gate insulating layer 702, a buffer layer 706 including conductive layers 704a and 704b and a metal oxide layer 705 and provided over the oxide semiconductor layer 703, a first electrode layer 707a provided over the conductive layer 704a, and a second electrode layer 707b provided over the conductive layer 704b.
[0107] The materials described in Embodiment 1 and the manufacturing method described in Embodiment 2 can be applied to the substrate 700, the gate electrode layer 701, the gate insulating layer 702, the oxide semiconductor layer 703, the conductive layer 704a, the conductive layer 704b, the metal oxide layer 705, the buffer layer 706, the first electrode layer 707a, and the second electrode layer 707b; therefore, here, the above description is to be referred to.
[0108] The sub-pixel includes a capacitor 752. The capacitor 752 includes a capacitor wiring 708 formed from the same material as the gate electrode layer 701 of the thin film transistors 750 and 751, the gate insulating layer 702, and the first electrode layer 707a of the thin film transistor 751, which extends to the sub-pixel.
[0109] An interlayer insulating layer 709 is provided over the thin film transistors 750 and 751 and the capacitor 752. Each of the thin film transistors 750 and 751 in FIG. 8 is provided with the metal oxide layer 705 for suppressing incorporation of impurities (such as hydrogen and moisture) into the oxide semiconductor layer 703; therefore, various materials and manufacturing methods can be used for the interlayer insulating layer 709. For example, as the interlayer insulating layer 709, a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer, a silicon nitride oxide layer, or the like can be formed by a plasma CVD method or a sputtering method. Further, the interlayer insulating layer 709 can also be formed by an application method such as a spin coating method, using an organic material such as polyimide, polyamide, polyvinylphenol, benzocyclobutene, acrylic, or epoxy; a siloxane material such as a siloxane resin; an oxazole resin; or the like. Note that a siloxane material corresponds to a material having a Si—O—Si bond. Siloxane has a skeleton structure with a bond of silicon (Si) and oxygen (O). As a substituent, an organic group (e.g., an alkyl group or aromatic hydrocarbon) or a fluoro group may be used. The organic group may include a fluoro group. Contact holes 710a, 710b, and 710c are provided in the interlayer insulating layer 709. The second electrode layer 707b of the thin film transistor 751 is electrically connected to a pixel electrode 711 through the contact hole 710c.
[0110] FIG. 9 is an equivalent circuit diagram corresponding to the sub-pixel in FIG. 7 . A gate electrode of a thin film transistor 800 is electrically connected to a gate wiring 801, and a first electrode of the thin film transistor 800 is electrically connected to a source wiring 802. One electrode of a capacitor 803 is electrically connected to a second electrode of the thin film transistor 800, and the other electrode of the capacitor 803 is electrically connected to a power supply line 804. A gate electrode of a thin film transistor 805 is electrically connected to the second electrode of the thin film transistor 800, and a first electrode of the thin film transistor 805 is electrically connected to the power supply line 804 and the other electrode of the capacitor 803. An organic EL element 806 to which voltage is applied through a pixel electrode is electrically connected to a second electrode of the thin film transistor 805.
[0111] A light-emitting display device includes an organic EL element provided over a pixel electrode of an active matrix substrate, and a common electrode provided over the organic EL element. Note that the common electrode is set to have a low power supply potential VSS. When voltage corresponding to a potential difference between the high power supply potential VDD supplied to the pixel electrode through the thin film transistor and the low power supply potential VSS supplied to the common electrode is applied to the organic EL element, current flows to the organic EL element so that the organic EL element emits light. In the light-emitting display device, a thin film transistor in a pixel portion of the active matrix substrate is a switching element which controls current flowing in the organic EL element.
[0112] In the light-emitting display device of this embodiment, the thin film transistors 750 and 751 in each of which the metal oxide layer 705 is provided over the oxide semiconductor layer 703 are used as thin film transistors in the pixel portion of the active matrix substrate. The metal oxide layer 705 functions as a protective layer for suppressing incorporation of impurities (such as hydrogen and moisture) into the oxide semiconductor layer 703. Therefore, the material and manufacturing method of the interlayer insulating layer 709 can be selected depending on the purpose. As a result, a light-emitting display device with high performance or high reliability can be provided. Note that here, the light-emitting display device to which the thin film transistor in FIG. 1A is applied is described; however, the same effect can be obtained also in the case where the thin film transistor in FIG. 1B is applied.
Embodiment 5
[0113] In this embodiment, one example of a semiconductor device in which the thin film transistor described in Embodiment 1 is used will be described. Specifically, an electronic paper in which the thin film transistor is applied to a thin film transistor provided for an active matrix substrate will be described with reference to FIG. 10 . Next, an electronic paper of this embodiment will be described.
[0114] FIG. 10 is a cross-sectional view of an active matrix electronic paper. A thin film transistor 950 provided over a first substrate (an active matrix substrate) 900 is the thin film transistor in FIG. 1A . That is, the thin film transistor 950 includes a gate electrode layer 901 provided over the first substrate 900, a gate insulating layer 902 provided over the gate electrode layer 901, an oxide semiconductor layer 903 provided over the gate insulating layer 902, a buffer layer 906 including a pair of conductive layers 904a and 904b and a metal oxide layer 905 and provided over the oxide semiconductor layer 903, a first electrode layer 907a provided over the conductive layer 904a, and a second electrode layer 907b provided over the conductive layer 904b.
[0115] The materials described in Embodiment 1 and the manufacturing method described in Embodiment 2 can be applied to the first substrate 900, the gate electrode layer 901, the gate insulating layer 902, the oxide semiconductor layer 903, the conductive layer 904a, the conductive layer 904b, the metal oxide layer 905, the buffer layer 906, the first electrode layer 907a, and the second electrode layer 907b; therefore, here, the above description is to be referred to.
[0116] An interlayer insulating layer 908 is provided over the thin film transistor 950. The thin film transistor 950 in FIG. 10 is provided with the metal oxide layer 905 for suppressing incorporation of impurities (such as hydrogen and moisture) into the oxide semiconductor layer 903; therefore, various materials and manufacturing methods can be used for the interlayer insulating layer 908. For example, as the interlayer insulating layer 908, a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer, a silicon nitride oxide layer, or the like can be formed by a plasma CVD method or a sputtering method. Further, the interlayer insulating layer 908 can also be formed by an application method such as a spin coating method, using an organic material such as polyimide, polyamide, polyvinylphenol, benzocyclobutene, acrylic, or epoxy; a siloxane material such as a siloxane resin; an oxazole resin; or the like. Note that a siloxane material corresponds to a material having a Si—O—Si bond. Siloxane has a skeleton structure with a bond of silicon (Si) and oxygen (O). As a substituent, an organic group (e.g., an alkyl group or aromatic hydrocarbon) or a fluoro group may be used. The organic group may include a fluoro group. A contact hole 909 is provided in the interlayer insulating layer 908. The second electrode layer 907b of the thin film transistor 950 is electrically connected to a pixel electrode 910 through the contact hole 909.
[0117] Between the pixel electrode 910 and a common electrode 912 which is provided for the second substrate 911, twisting balls 915 each having a black region 913a, a white region 913b, and a cavity 914 around the regions which is filled with liquid are provided. A space around the twisting balls 915 is filled with a filler 916 such as a resin.
[0118] An electronic paper in this embodiment employs a twisting ball display method. Twisting balls each colored in black or white are provided between a pixel electrode and a common electrode in the electronic paper. The twisting balls perform display in such a manner that the orientation is controlled by voltage application between the pixel electrode provided for the first substrate and the common electrode provided for the second substrate. In the electronic paper, a thin film transistor provided for an active matrix substrate is a switching element controlling voltage which is applied to twisting balls.
[0119] In the light-emitting display device of this embodiment, the thin film transistor 950 in which the metal oxide layer 905 is provided over the oxide semiconductor layer 903 is used as a thin film transistor provided for the active matrix substrate. The metal oxide layer 905 functions as a protective layer for suppressing incorporation of impurities (such as hydrogen and moisture) into the oxide semiconductor layer 903. Therefore, the material and manufacturing method of the interlayer insulating layer 908 can be selected depending on the purpose. As a result, an electronic paper with high performance or high reliability can be provided. Note that the electronic paper to which the thin film transistor in FIG. 1A is applied is described here; however, the same effect can be obtained also in the case where the thin film transistor in FIG. 1B is applied.
Example 1
[0120] Here, calculation results of change in electron states of titanium and titanium oxide depending on the difference in the content of oxygen, change in an electron state of an oxide semiconductor layer in accordance with oxygen deficiency, behavior of oxygen in the vicinity of a bonding interface between a titanium layer and an oxide semiconductor layer under thermal treatment, and behavior of oxygen in the vicinity of a bonding interface between a titanium oxide layer and an oxide semiconductor layer under thermal treatment are described. Next, the thin film transistor which is described in Embodiment 1 and in which titanium is applied to a composition material of the buffer layer is examined.
[0121] First, change in electron states of titanium and titanium oxide depending on the difference in the content of oxygen is examined. Here, results of obtaining the energy state density of crystal structures of titanium and a plurality of titanium oxides by structure optimization by the first-principle calculation using a plane wave-pseudopotential method based on density functional theory (DFT) are described. Specifically, graphs show the state density of Ti, TiO (NaCl type), Ti2O3 (Al2O3 type), TiO2 (Anatase type), TiO2 (Rutile type), and TiO2 (Brookite type) after structures thereof are optimized. Note that CASTEP was used for a calculation program, and GGA-PBE was used for an exchange-correlation function.
[0122] FIGS. 11A , 11B, and 11C show the state density of Ti, TiO (NaCl type), and Ti2O3 (Al2O3 type), respectively. In FIGS. 11A to 11C , there is no band gap. That is, Ti, TiO (NaCl type), and Ti2O3 (Al2O3 type) are conductors.
[0123] FIGS. 12A , 12B, and 12C show the state density of TiO2 (Anatase type), TiO2 (Rutile type), and TiO2 (Brookite type), respectively. In FIGS. 12A to 12C , Fermi level (0 eV) is located in an upper end of the valence band, and there is a band gap. That is, each of TiO2 (Anatase type), TiO2 (Rutile type), and TiO2 (Brookite type) is an insulator or a semiconductor.
[0124] It is confirmed from FIGS. 11A to 11C and FIGS. 12A to 12C that titanium keeps a property of a conductor when a predetermined amount of oxygen or less is included therein, and titanium comes to have a property of an insulator or a property of a semiconductor when a predetermined amount of oxygen or more is included therein.
[0125] Next, change in an electron state of an oxide semiconductor layer in accordance with oxygen deficiency is examined. Here, calculation is performed in the case where an In—Ga—Zn—O-based oxide semiconductor material (In:Ga:Zn:O=1:1:1:4) is used for an oxide semiconductor layer.
[0126] First, an amorphous structure of the In—Ga—Zn—O-based oxide semiconductor was formed by a melt-quench method using classical molecular dynamics simulation. Note that the amorphous structure formed here is as follows: the total number of atoms is 84; and the density is 5.9 g/cm3. Born-Mayer-Huggins potential was used for the interatomic potential between metal and oxygen and between oxygen and oxygen, and Lennard-Jones potential was used for the interatomic potential between metal and metal. NTV ensemble was used for calculation. Materials Explorer was used as a calculation program.
[0127] After that, annealing by first-principle molecular dynamics (hereinafter also referred to as first-principle MD) using a plane wave-pseudopotential method based on density functional theory (DFT) was performed at a room temperature (298 K) on the structure obtained by the above calculation in order to optimize the structure. Then, the state density was calculated. In addition, first-principle MD calculation was used for calculation, optimization of the structure was performed on a structure in which one of oxygen atoms was removed randomly (a structure with oxygen deficiency), and the state density was calculated. Note that CASTEP was used as a calculation program; and GGA-PBE, an exchange-correlation function. First-principle MD was used for calculation by using NTV ensemble.
[0128] FIGS. 13A and 13B each show the state density of the In—Ga—Zn—O-based oxide semiconductor obtained by the above calculation. FIG. 13A shows the state density of a structure without oxygen deficiency, and FIG. 13B shows the state density of a structure with oxygen deficiency. In FIG. 13A , Fermi level (0 eV) is located in an upper end of the valence band and there is a band gap, while in FIG. 13B , Fermi level (0 eV) is located in the conduction band. That is, it is confirmed that the structure with oxygen deficiency has lower resistance than the structure without oxygen deficiency.
[0129] Next, behavior of oxygen in the vicinity of a bonding interface between a titanium layer and an oxide semiconductor layer under thermal treatment is examined. Here, titanium was deposited over the amorphous structure of the In—Ga—Zn—O-based oxide semiconductor obtained by the above first-principle calculation, and optimization of the structure was performed. Then, first-principle MD was used for calculation by using NTV ensemble. CASTEP was used as a calculation program; and GGA-PBE, an exchange-correlation function. The temperature was set at 350° C. (623 K).
[0130] FIGS. 14A and 14B show the structures before and after first-principle MD. FIG. 14A shows the structure before first-principle MD, and FIG. 14B shows the structure after first-principle MD. Further, FIG. 15 shows the density of titanium and oxygen in the c-axis direction before and after first-principle MD. FIG. 15 shows the density distribution obtained by assigning each atom in FIGS. 14A and 14B Gaussian distribution density and summing all the atoms. In FIG. 15 , the horizontal axis represents the atom density, and the vertical axis represents the c-axis. Curves in FIG. 15 represent the density of titanium before first-principle MD (Ti_before), the density of titanium after first-principle MD (Ti_after), the density of oxygen before first-principle MD (O_before), and the density of oxygen after first-principle (O_after). It is found from FIG. 15 that O_after is shifted toward the positive direction of the c-axis as compared with O_before, and the concentration of oxygen contained in titanium after first-principle MD is increased as compared with that before first-principle MD. That is, it is found that through the thermal treatment at 350° C. (623 K), oxygen in the oxide semiconductor layer is diffused into the titanium layer.
[0131] Next, behavior of oxygen in the vicinity of a bonding interface between the titanium oxide (here, TiO2 (Rutile type) was used) layer and the oxide semiconductor layer under thermal treatment is examined. Here, TiO2 (Rutile type) was deposited over the amorphous structure of the In—Ga—Zn—O-based oxide semiconductor obtained by the first-principle calculation, and optimization of the structure was performed, and then, first-principle MD was used for calculation by using NTV ensemble. CASTEP was used as a calculation program; and GGA-PBE, an exchange-correlation function. The temperature was set at 700° C. (973 K).
[0132] FIGS. 16A and 16B show the structures before and after first-principle MD. FIG. 16A shows the structure before first-principle MD, and FIG. 16B shows the structure after first-principle MD. Further, FIG. 17 shows the density of titanium and oxygen in the c-axis direction before and after first-principle MD. FIG. 17 shows the density distribution obtained by assigning each atom in FIGS. 16A and 16B Gaussian distribution density and summing all the atoms. In FIG. 17 , the horizontal axis represents the atom density, and the vertical axis represents the c-axis. Curves in FIG. 17 represent the density of titanium before first-principle MD (Ti_before), the density of titanium after first-principle MD (Ti_after), the density of oxygen before first-principle MD (O_before), and the density of oxygen after first-principle MD (O_after). Unlike in FIG. 15 , there is not a large difference between O_after and O_before in FIG. 17 . That is, it is found that even when the thermal treatment at 700° C. (973 K) is performed, diffusion of oxygen between the oxide semiconductor layer and the TiO2 (Rutile type) layer is not actively performed as compared with diffusion of oxygen between the oxide semiconductor layer and the titanium layer at 350° C.
[0133] Calculation results performed in this example are summarized below.
[0134] It is found from FIGS. 11A to 11C and FIGS. 12A to 12C that a plurality of titanium oxides have different electron states, and when the oxygen concentration is increased, the titanium oxide comes to have a property of an insulator or a property of a semiconductor. Specifically, it is found that TiO (NaCl type) and Ti2O3 (Al2O3 type) are conductors, and each of TiO2 (Anatase type), TiO2 (Rutile type), and TiO2 (Brookite type) is an insulator or a semiconductor. That is, it is found that a titanium oxide comes to have a property of an insulator or a property of a semiconductor when the content of oxygen is large, and its electron density is changed depending on the ratio of oxygen.
[0135] It is found from FIGS. 13A and 13B that, when the In—Ga—Zn—O-based oxide semiconductor has the structure with oxygen deficiency, the electron state is changed and the resistance is lowered. Note that in FIGS. 13A and 13B , the amorphous structure whose total number of atoms is 84 (In:Ga:Zn:O=1:1:1:4) is compared with the structure in which one of oxygen atoms is removed from the amorphous structure. In other words, the structure whose oxygen concentration is about 57.1 atomic % (48 (the number of oxygen atoms)/84 (the number of total atoms)) is compared with the structure whose oxygen concentration is about 56.6 atomic % (47 (the number of oxygen atoms)/83 (the number of total atoms)). Accordingly, the In—Ga—Zn—O-based oxide semiconductor is a material whose change in oxygen concentration greatly affects the electron state as compared with titanium described above.
[0136] It is found from FIGS. 14A and 14B and FIG. 15 that oxygen in the In—Ga—Zn—O-based oxide semiconductor layer is diffused into the titanium layer when the thermal treatment at 350° C. is performed on the titanium layer and the In—Ga—Zn—O-based oxide semiconductor layer. In other words, it is found that the titanium layer containing oxygen at higher concentration than the titanium layer before the thermal treatment and the oxide semiconductor layer whose oxygen concentration is lower than the oxide semiconductor before the thermal treatment are formed through the thermal treatment. It is thought that, when considering an effect of change in the oxygen concentration of the titanium layer and the In—Ga—Zn—O-based oxide semiconductor layer on the electron states thereof, the resistance of the titanium layer containing oxygen at high concentration is not increased so much as compared with that of the titanium layer, and the resistance of the oxide semiconductor layer whose oxygen concentration is lowered is reduced as compared with that of the oxide semiconductor layer.
[0137] It is found from FIGS. 16A and 16B and FIG. 17 that even when the thermal treatment at a temperature as high as 700° C. is performed on a stack of the TiO2 (Rutile type) layer and the In—Ga—Zn—O-based oxide semiconductor layer, diffusion of oxygen from the oxide semiconductor layer to the titanium layer is not actively performed as compared with diffusion of oxygen from the oxide semiconductor layer to the titanium layer at 350° C. In other words, it is found that the oxide semiconductor layer whose oxygen concentration is lower than that of the stack of the oxide semiconductor layer and the titanium layer is not easily formed even when the thermal treatment is performed.
[0138] Next, the case where titanium is applied to the buffer layer in the thin film transistor described in Embodiment 1 is examined. By performing oxidation treatment on the titanium layer, a titanium oxide such as TiO2 (Anatase type), TiO2 (Rutile type), or TiO2 (Brookite type) which is an insulator or a semiconductor is formed to be used as a metal oxide layer included in the buffer layer. By performing thermal treatment at 350° C., oxygen in the oxide semiconductor layer is diffused into the titanium layer, whereby a titanium layer containing oxygen at high concentration and an oxide semiconductor layer whose oxygen concentration is lowered are formed. Therefore, the resistance of the oxide semiconductor layer can be effectively reduced, and ohmic contact between the oxide semiconductor layer and each of the source electrode layer and the drain electrode layer can be obtained through the buffer layer. In addition, diffusion of oxygen does not easily occur at an interface between the oxide semiconductor layer and the metal oxide layer, as compared with at an interface between an oxide semiconductor layer and a conductive layer. Accordingly, the oxide semiconductor layer whose oxygen concentration is lowered and whose resistance is reduced is not easily formed at the interface between the oxide semiconductor layer and the metal oxide layer, whereby an increase in off current of the thin film transistor can be suppressed.
[0139] From the above, it is confirmed that titanium is preferably used as a material applied to the buffer layer in the thin film transistor described in Embodiment 1.
[0140] This application is based on Japanese Patent Application serial No. 2009-037912 filed with Japan Patent Office on Feb. 20, 2009, the entire contents of which are hereby incorporated by reference.
Claims
What is claimed is:
1. A method for manufacturing a transistor, comprising:
forming a first conductive film over a substrate;
forming a first resist over the first conductive film;
selectively etching the first conductive film using the first resist as a mask to form a gate electrode layer;
forming a gate insulating layer over the substrate and the gate electrode layer;
forming an oxide semiconductor film over the gate insulating layer;
forming a second conductive film over the oxide semiconductor film;
forming a second resist over the second conductive film;
selectively etching the oxide semiconductor film and the second conductive film using the second resist as a mask to form an oxide semiconductor layer and a conductive layer;
forming a third conductive film over the gate insulating layer and the conductive layer;
forming a third resist over the third conductive film;
selectively etching the third conductive film using the third resist as a mask to form a source electrode layer and a drain electrode layer; and
performing an oxidation treatment using the third resist as a mask to form a pair of conductive layers between the oxide semiconductor layer and each of the source electrode layer and the drain electrode layer, and to form a metal oxide layer over the oxide semiconductor layer.
2. The method for manufacturing a transistor according to claim 1, wherein the metal oxide layer is an insulator.
3. The method for manufacturing a transistor according to claim 1, wherein the metal oxide layer is a semiconductor.
4. The method for manufacturing a transistor according to claim 1, wherein the pair of conductive layers is selected from titanium, copper, zinc, aluminum, or an alloy containing at least one of titanium, copper, zinc, and aluminum.
5. The method for manufacturing a transistor according to claim 1, further comprising a step of forming an interlayer insulating layer over the source electrode layer and the drain electrode layer.
6. A method for manufacturing a transistor, comprising:
forming a first conductive film over a substrate;
forming a first resist over the first conductive film;
selectively etching the first conductive film using the first resist as a mask to form a gate electrode layer;
forming a gate insulating layer over the substrate and the gate electrode layer;
forming an oxide semiconductor film over the gate insulating layer;
forming a second conductive film over the oxide semiconductor film;
forming a second resist over the second conductive film;
selectively etching the oxide semiconductor film and the second conductive film using the second resist as a mask to form an oxide semiconductor layer and a conductive layer;
forming a third conductive film over the gate insulating layer and the conductive layer;
forming a third resist over the third conductive film;
selectively etching the third conductive film using the third resist as a mask to form a source electrode layer and a drain electrode layer;
performing an oxidation treatment using the third resist as a mask to form a pair of conductive layers between the oxide semiconductor layer and each of the source electrode layer and the drain electrode layer, and to form a metal oxide layer over the oxide semiconductor layer; and
performing a thermal treatment to form a pair of oxide semiconductor layers whose oxygen concentration is lowered and a pair of conductive layers containing oxygen at high concentration, between the oxide semiconductor layer and each of the pair of conductive layers.
7. The method for manufacturing a transistor according to claim 6, wherein the metal oxide layer is an insulator.
8. The method for manufacturing a transistor according to claim 6, wherein the metal oxide layer is a semiconductor.
9. The method for manufacturing a transistor according, to claim 6, wherein the pair of conductive layers is selected from titanium, copper, zinc, aluminum, or an alloy containing at least one of titanium, copper, zinc, and aluminum.
10. The method for manufacturing a transistor according to claim 6, further comprising a step of forming an interlayer insulating layer over the source electrode layer and the drain electrode layer.
11. A method for manufacturing a transistor, comprising:
forming a first conductive film over a substrate;
forming a first resist over the first conductive film;
selectively etching the first conductive film using the first resist as a mask to form a gate electrode layer;
forming a gate insulating layer over the substrate and the gate electrode layer;
forming an oxide semiconductor film over the gate insulating layer;
forming a second conductive film over the oxide semiconductor film;
forming a second resist over the second conductive film;
selectively etching the oxide semiconductor film and the second conductive film using the second resist as a mask to form an oxide semiconductor layer and a conductive layer;
forming a third conductive film over the gate insulating layer and the conductive layer;
forming a third resist over the third conductive film;
selectively etching the third conductive film using the third resist as a mask to form a source electrode layer and a drain electrode layer; and
performing a thermal oxidation treatment using the third resist as a mask to form a pair of conductive layers between the oxide semiconductor layer and each of the source electrode layer and the drain electrode layer, to form a metal oxide layer over the oxide semiconductor layer, and to form a pair of oxide semiconductor layers whose oxygen concentration is lowered, and a pair of conductive layers containing oxygen at high concentration between the oxide semiconductor layer and each of the pair of conductive layers.
12. The method for manufacturing a transistor according to claim 11, wherein the metal oxide layer is an insulator.
13. The method for manufacturing a transistor according to claim 11, wherein the metal oxide layer is a semiconductor.
14. The method for manufacturing a transistor according to claim 11, wherein the pair of conductive layers is selected from titanium, copper, zinc, aluminum, or an alloy containing at least one of titanium, copper, zinc, and aluminum.
15. The method for manufacturing a transistor according to claim 11, further comprising a step of forming an interlayer insulating layer over the source electrode layer and the drain electrode layer.
16. A method for manufacturing a transistor, comprising:
forming a first conductive film over a substrate;
forming a first resist over the first conductive film;
selectively etching the first conductive film using the first resist as a mask to form a gate electrode layer;
forming a gate insulating layer over the substrate and the gate electrode layer;
forming an oxide semiconductor film over the gate insulating layer;
forming a second conductive film over the oxide semiconductor film;
forming a second resist over the second conductive film;
selectively etching the oxide semiconductor film and the second conductive film using the second resist as a mask to form an oxide semiconductor layer and a conductive layer;
forming a third conductive film over the gate insulating layer and the conductive layer;
forming a third resist over the third conductive film;
selectively etching the third conductive film using the third resist as a mask to form a source electrode layer and a drain electrode layer; and
performing an oxidation treatment and a thermal oxidation treatment using the third resist as a mask to form a pair of conductive layers between the oxide semiconductor layer and each of the source electrode layer and the drain electrode layer, to form a metal oxide layer over the oxide semiconductor layer, and to form a pair of oxide semiconductor layers whose oxygen concentration is lowered, and a pair of conductive layers containing oxygen at high concentration between the oxide semiconductor layer and each of the pair of conductive layers.
17. The method for manufacturing a transistor according to claim 16, wherein the metal oxide layer is an insulator.
18. The method for manufacturing a transistor according to claim 16, wherein the metal oxide layer is a semiconductor.
19. The method for manufacturing a transistor according to claim 16, wherein the pair of conductive layers is selected from titanium, copper, zinc, aluminum, or an alloy containing at least one of titanium, copper, zinc, and aluminum.
20. The method for manufacturing a transistor according to claim 16, further comprising a step of forming an interlayer insulating layer over the source electrode layer and the drain electrode layer.
Patent Citations (153)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US5731856(A) | 1998-03-01 | Kim et al. | Applicant |
| US5744864(A) | 1998-04-01 | Cillessen et al. | Applicant |
| US5847410(A) | 1998-12-01 | Nakajima | Applicant |
| US6294274(B1) | 2001-09-01 | Kawazoe et al. | Applicant |
| US6563174(B2) | 2003-05-01 | Kawasaki et al. | Applicant |
| US6586346(B1) | 2003-07-01 | Yamazaki et al. | Applicant |
| US6727522(B1) | 2004-04-01 | Kawasaki et al. | Applicant |
| US6960812(B2) | 2005-11-01 | Yamazaki et al. | Applicant |
| US7049190(B2) | 2006-05-01 | Takeda et al. | Applicant |
| US7061014(B2) | 2006-06-01 | Hosono et al. | Applicant |
| US7064346(B2) | 2006-06-01 | Kawasaki et al. | Applicant |
| US7105868(B2) | 2006-09-01 | Nause et al. | Applicant |
| US7211825(B2) | 2007-05-01 | Shih et al | Applicant |
| US7282782(B2) | 2007-10-01 | Hoffman et al. | Applicant |
| US7297977(B2) | 2007-11-01 | Hoffman et al. | Applicant |
| US7301211(B2) | 2007-11-01 | Yamazaki et al. | Applicant |
| US7323356(B2) | 2008-01-01 | Hosono et al. | Applicant |
| US7385224(B2) | 2008-06-01 | Ishii et al. | Applicant |
| US7402506(B2) | 2008-07-01 | Levy et al. | Applicant |
| US7411209(B2) | 2008-08-01 | Endo et al. | Applicant |
| US7453065(B2) | 2008-11-01 | Saito et al. | Applicant |
| US7453087(B2) | 2008-11-01 | Iwasaki | Applicant |
| US7462862(B2) | 2008-12-01 | Hoffman et al. | Applicant |
| US7468304(B2) | 2008-12-01 | Kaji et al. | Applicant |
| US7501293(B2) | 2009-03-01 | Ito et al. | Applicant |
| US7564058(B2) | 2009-07-01 | Yamazaki et al. | Examiner |
| US7674650(B2) | 2010-03-01 | Akimoto et al. | Applicant |
| US7732819(B2) | 2010-06-01 | Akimoto et al. | Applicant |
| US7768009(B2) | 2010-08-01 | Kobayashi et al. | Examiner |
| US7791075(B2) | 2010-09-01 | Kobayashi et al. | Examiner |
| US2001/0046027(A1) | 2001-11-01 | Tai et al. | Applicant |
| US2002/0056838(A1) | 2002-05-01 | Ogawa | Applicant |
| US2002/0132454(A1) | 2002-09-01 | Ohtsu et al. | Applicant |
| US2003/0189401(A1) | 2003-10-01 | Kido et al. | Applicant |
| US2003/0218222(A1) | 2003-11-01 | Wager et al. | Applicant |
| US2004/0038446(A1) | 2004-02-01 | Takeda et al. | Applicant |
| US2004/0127038(A1) | 2004-07-01 | Carcia et al. | Applicant |
| US2005/0017302(A1) | 2005-01-01 | Hoffman | Applicant |
| US2005/0199959(A1) | 2005-09-01 | Chiang et al. | Applicant |
| US2006/0035452(A1) | 2006-02-01 | Carcia et al. | Applicant |
| US2006/0043377(A1) | 2006-03-01 | Hoffman et al. | Applicant |
| US2006/0091793(A1) | 2006-05-01 | Baude et al. | Applicant |
| US2006/0108529(A1) | 2006-05-01 | Saito et al. | Applicant |
| US2006/0108636(A1) | 2006-05-01 | Sano et al. | Applicant |
| US2006/0110867(A1) | 2006-05-01 | Yabuta et al. | Applicant |
| US2006/0113536(A1) | 2006-06-01 | Kumomi et al. | Applicant |
| US2006/0113539(A1) | 2006-06-01 | Sano et al. | Applicant |
| US2006/0113549(A1) | 2006-06-01 | Den et al. | Applicant |
| US2006/0113565(A1) | 2006-06-01 | Abe et al. | Applicant |
| US2006/0169973(A1) | 2006-08-01 | Isa et al. | Applicant |
| US2006/0170111(A1) | 2006-08-01 | Isa et al. | Applicant |
| US2006/0197092(A1) | 2006-09-01 | Hoffman et al. | Applicant |
| US2006/0208977(A1) | 2006-09-01 | Kimura | Applicant |
| US2006/0228974(A1) | 2006-10-01 | Thelss et al. | Applicant |
| US2006/0231882(A1) | 2006-10-01 | Kim et al. | Applicant |
| US2006/0238135(A1) | 2006-10-01 | Kimura | Applicant |
| US2006/0244107(A1) | 2006-11-01 | Sugihara et al. | Applicant |
| US2006/0284171(A1) | 2006-12-01 | Levy et al. | Applicant |
| US2006/0284172(A1) | 2006-12-01 | Ishii | Applicant |
| US2006/0292777(A1) | 2006-12-01 | Dunbar | Applicant |
| US2007/0024187(A1) | 2007-02-01 | Shin et al. | Applicant |
| US2007/0046191(A1) | 2007-03-01 | Saito | Applicant |
| US2007/0052025(A1) | 2007-03-01 | Yabuta | Applicant |
| US2007/0054507(A1) | 2007-03-01 | Kaji et al. | Applicant |
| US2007/0072439(A1) | 2007-03-01 | Akimoto et al. | Applicant |
| US2007/0090365(A1) | 2007-04-01 | Hayashi et al. | Applicant |
| US2007/0108446(A1) | 2007-05-01 | Akimoto | Applicant |
| US2007/0152217(A1) | 2007-07-01 | Lai et al. | Applicant |
| US2007/0172591(A1) | 2007-07-01 | Seo et al. | Applicant |
| US2007/0187678(A1) | 2007-08-01 | Hirao et al. | Applicant |
| US2007/0187760(A1) | 2007-08-01 | Furuta et al. | Applicant |
| US2007/0194379(A1) | 2007-08-01 | Hosono et al. | Applicant |
| US2007/0252928(A1) | 2007-11-01 | Ito et al. | Applicant |
| US2007/0272922(A1) | 2007-11-01 | Kim et al. | Applicant |
| US2007/0287296(A1) | 2007-12-01 | Chang | Applicant |
| US2008/0006877(A1) | 2008-01-01 | Mardilovich et al. | Applicant |
| US2008/0038882(A1) | 2008-02-01 | Takechi et al. | Applicant |
| US2008/0038929(A1) | 2008-02-01 | Chang | Applicant |
| US2008/0050595(A1) | 2008-02-01 | Nakagawara et al. | Applicant |
| US2008/0073653(A1) | 2008-03-01 | Iwasaki | Applicant |
| US2008/0083950(A1) | 2008-04-01 | Pan et al. | Applicant |
| US2008/0106191(A1) | 2008-05-01 | Kawase | Applicant |
| US2008/0128689(A1) | 2008-06-01 | Lee et al. | Applicant |
| US2008/0129195(A1) | 2008-06-01 | Ishizaki et al. | Applicant |
| US2008/0166834(A1) | 2008-07-01 | Kim et al. | Applicant |
| US2008/0182358(A1) | 2008-07-01 | Cowdery-Corvan et al. | Applicant |
| US2008/0203387(A1) | 2008-08-01 | Kang et al. | Applicant |
| US2008/0224133(A1) | 2008-09-01 | Park et al. | Applicant |
| US2008/0254569(A1) | 2008-10-01 | Hoffman et al. | Applicant |
| US2008/0258139(A1) | 2008-10-01 | Ito et al. | Applicant |
| US2008/0258140(A1) | 2008-10-01 | Lee et al. | Applicant |
| US2008/0258141(A1) | 2008-10-01 | Park et al. | Applicant |
| US2008/0258143(A1) | 2008-10-01 | Kim et al. | Applicant |
| US2008/0296568(A1) | 2008-12-01 | Ryu et al. | Applicant |
| US2008/0308796(A1) | 2008-12-01 | Akimoto et al. | Applicant |
| US2008/0308797(A1) | 2008-12-01 | Akimoto et al. | Applicant |
| US2008/0308804(A1) | 2008-12-01 | Akimoto et al. | Applicant |
| US2008/0308805(A1) | 2008-12-01 | Akimoto et al. | Applicant |
| US2008/0308806(A1) | 2008-12-01 | Akimoto et al. | Applicant |
| US2009/0008639(A1) | 2009-01-01 | Akimoto et al. | Applicant |
| US2009/0065771(A1) | 2009-03-01 | Iwasaki et al. | Applicant |
| US2009/0068773(A1) | 2009-03-01 | Lai et al. | Applicant |
| US2009/0073325(A1) | 2009-03-01 | Kuwabara et al. | Applicant |
| US2009/0114910(A1) | 2009-05-01 | Chang | Applicant |
| US2009/0134399(A1) | 2009-05-01 | Sakakura et al. | Applicant |
| US2009/0152506(A1) | 2009-06-01 | Umeda et al. | Applicant |
| US2009/0152541(A1) | 2009-06-01 | Maekawa et al. | Applicant |
| US2009/0278122(A1) | 2009-11-01 | Hosono et al. | Applicant |
| US2009/0280600(A1) | 2009-11-01 | Hosono et al. | Applicant |
| US2010/0025678(A1) | 2010-02-01 | Yamazaki et al. | Applicant |
| US2010/0133530(A1) | 2010-06-01 | Akimoto et al. | Examiner |
| US2010/0140612(A1) | 2010-06-01 | Omura et al. | Applicant |
| US2010/0163868(A1) | 2010-07-01 | Yamazaki et al. | Examiner |
| US2010/0193783(A1) | 2010-08-01 | Yamazaki et al. | Examiner |
| US2010/0244034(A1) | 2010-09-01 | Miyairi | Examiner |
| US2010/0285624(A1) | 2010-11-01 | Kobayashi et al. | Examiner |
| US2010/0301326(A1) | 2010-12-01 | Miyairi et al. | Examiner |
| US2010/0304515(A1) | 2010-12-01 | Kobayashi et al. | Examiner |
| US2011/0108833(A1) | 2011-05-01 | Yamazaki et al. | Examiner |
| US2011/0114942(A1) | 2011-05-01 | Akimoto et al. | Examiner |
| US2011/0212571(A1) | 2011-09-01 | Yamazaki et al. | Examiner |
| US2011/0215318(A1) | 2011-09-01 | Yamazaki et al. | Examiner |
| US2011/0215319(A1) | 2011-09-01 | Yamazaki et al. | Examiner |
| US2011/0291089(A1) | 2011-12-01 | Akimoto et al. | Examiner |
| EP1737044(A) | 2006-12-01 | Applicant | |
| EP2226847(A) | 2010-09-01 | Applicant | |
| JP60-198861 | 1985-10-01 | Applicant | |
| JP60-198861(A) | 1985-10-01 | Applicant | |
| JP63-210022(A) | 1988-08-01 | Applicant | |
| JP63-210023(A) | 1988-08-01 | Applicant | |
| JP63-210024(A) | 1988-08-01 | Applicant | |
| JP63-215519(A) | 1988-09-01 | Applicant | |
| JP63-239117(A) | 1988-10-01 | Applicant | |
| JP63-265818(A) | 1988-11-01 | Applicant | |
| JP3-231472(A) | 1991-10-01 | Applicant | |
| JP5-251705(A) | 1993-09-01 | Applicant | |
| JP8-264794 | 1996-10-01 | Applicant | |
| JP8-264794(A) | 1996-10-01 | Applicant | |
| JP11-505377 | 1999-05-01 | Applicant | |
| JP2000-044236(A) | 2000-02-01 | Applicant | |
| JP2000-150900 | 2000-05-01 | Applicant | |
| JP2002-076356(A) | 2002-03-01 | Applicant | |
| JP2002-289859(A) | 2002-10-01 | Applicant | |
| JP2003-086000(A) | 2003-03-01 | Applicant | |
| JP2003-086808(A) | 2003-03-01 | Applicant | |
| JP2004-103957 | 2004-04-01 | Applicant | |
| JP2004-273614(A) | 2004-09-01 | Applicant | |
| JP2004-273732(A) | 2004-09-01 | Applicant | |
| JP2007-096055(A) | 2007-04-01 | Applicant | |
| JP2007-123861(A) | 2007-05-01 | Applicant | |
| JP2007-250983(A) | 2007-09-01 | Applicant | |
| WO-2004/114391 | 2004-12-01 | Applicant | |
| WO-2007/119386 | 2007-10-01 | Applicant |
Non-Patent Literature (71)
- Prins et al., “A Ferroelectric Transparent Thin-Film Transistor,” Appl. Phys. Lett. (Applied Physics Letters), vol. 68, No. 25, pp. 3650-3652, Jun. 17, 1996.Applicant
- Nakamura et al., “The Phase Relations in the In2O3-Ga2ZnO4-ZnO System at 1350°C,” Journal of Solid State Chemistry, Aug. 1, 1991, vol. 93, pp. 298-315.Applicant
- Kimizuka et al., “Syntheses and Single-Crystal Data of Homologous Compounds, In2O3(ZnO)m (m=3, 4, and 5), InGaO3(ZnO)3, and Ga2O3(ZnO)m (m=7, 8, 9, and 16) in the In2O3-ZnGa2O4-ZnO System,” Journal of Solid State Chemistry, Apr. 1, 1995, vol. 116, pp. 170-178.Applicant
- Nakamura et al., “Syntheses and crystal structures of new homologous compounds, indium iron zinc oxides (InFeO3(ZnO)m) (m: natural number) and related compounds,” Kotai Butsuri (Solid State Physics), 1993, vol. 28, No. 5, pp. 317-327.Applicant
- Nomura et al., “Thin-Film Transistor Fabricated in Single-Crystalline Transparent Oxide Semiconductor,” Science, May 23, 2003, vol. 300, pp. 1269-1272.Applicant
- Nomura et al., “Room-Temperature Fabrication of Transparent Flexible Thin-Film Transistors Using Amorphous Oxide Semiconductors,” Nature, Nov. 25, 2004, vol. 432, pp. 488-492.Applicant
- Dembo.H et al., “RFCPUS on Glass and Plastic Substrates Fabricated by TFT Transfer Technology,”, IEDM 05: Technical Digest of International Electron Devices Meetting, Dec. 5, 2005, pp. 1067-1069.Applicant
- Ikeda.T et al., “Full-Functional System Liquid Crystal Display Using CG-Silicon Technology,”, SID Digest '04 : SID International Symposium Digest of Technical Papers, 2004, vol. 35, pp. 860-863.Applicant
- Takahashi.M et al., “Theoretical Analysis of IGZO Transparent Amorphous Oxide Semiconductor,”, IDW '08 : Proceedings of the 15th International Display Workshops, Dec. 3, 2008, pp. 1637-1640.Applicant
- Osada.T et al., “15.2: Development of Driver-Integrated Panel using Amorphous In-Ga-Oxide TFT,”, SID Digest '09 : SID International Symposium Digest of Technical Papers, May 31, 2009, pp. 184-187.Applicant
- Li.C et al., “Modulated Structures of Homologous Compounds InMO3(ZnO)m (M=In,Ga; m=Integer) Described by Four-Dimensional Superspace Group,”, Journal of Solid State Chemistry, 1998, vol. 139, pp. 347-355.Applicant
- Lee.J et al., “World'S Largest (15-Inch) XGA AMLCD Panel Using IGZO Oxide TFT,”, SID Digest '08 : SID International Symposium Digest of Technical Papers, May 20, 2008, vol. 39, pp. 625-628.Applicant
- Nowatari.H et al., “60.2: Intermediate Connector With Suppressed Voltage Loss for White Tandem OLEDS,”, SID Digest '09 : SID International Symposium Digest of Technical Papers, May 31, 2009, pp. 899-902.Applicant
- Kanno.H et al., “White Stacked Electrophosphorecent Organic Light-Emitting Device Employing MoO3 as a Change-Generation Layer,”, Adv. Mater. (Advanced Materials), 2006, vol. 18, No. 3, pp. 339-342.Applicant
- Tsuda.K et al., “Ultra Low Power Consumption Technologies for Mobile TFT-LCDs ,”, IDW '02 : Proceedings of the 9th International Display Workshops, Dec. 4, 2002, pp. 295-298.Applicant
- Jeong.J et al., “3.1: Distinguished Paper: 12.1-Inch WXGA Amoled Display Driven by Indium-Gallium-Zinc Oxide TFTs Array,”, SID DIGEST '08 : SID International Symposium Digest of Technical Papers, May 20, 2008, vol. 39, No. 1, pp. 1-4.Applicant
- Park.J et al., “High performance amorphous oxide thin film transistors with self-aligned top-gate structure,”, IEDM 09: Technical Digest of International Electron Devices Meeting, Dec. 7, 2009, pp. 191-194.Applicant
- Kurokawa.Y et al., “UHF RFCPUS on Flexible and Glass Substrates for Secure RFID Systems,”, Journal of Solid-State Circuits , 2008, vol. 43, No. 1, pp. 292-299.Applicant
- Ohara.H et al., “Amorphous In-Ga-Zn-Oxide TFTs with Suppressed Variation for 4.0 inch QVGA Amoled Display,”, AM-FPD '09 Digest of Technical Papers, Jul. 1, 2009, pp. 227-230, The Japan Society of Applied Physics.Applicant
- Coates.D et al., “Optical Studies of the Amorphous Liquid-Cholesteric Liquid Crystal Transition:The “Blue Phase”,”, Physics Letters, Sep. 10, 1073, vol. 45A, No. 2, pp. 115-116.Applicant
- Cho.D et al., “21.2:AL and SN-Doped Zinc Indium Oxide Thin Film Transistors for Amoled Back-Plane,”, SID Digest '09 : SID International Symposium Digest of Technical Papers, May 31, 2009, pp. 280-283.Applicant
- Lee.M et al., “15.4:Excellent Performance of Indium-Oxide-Based Thin-Film Transistors by DC Sputtering,”, SID Digest '09 : SID International Symposium Digest of Technical Papers, May 31, 2009, pp. 191-193.Applicant
- Jin.D et al., “65.2:Distinguished Paper:World-Largest (6.5″) Flexible Full Color Top Emission Amoled Display on Plastic Film and its Bending Properties,”, SID Digest '09 : SID International Symposium Digest of Technical Papers, May 31, 2009, pp. 983-985.Applicant
- Sakata.J et al., “Development of 4.0-In. Amoled Display With Driver Circuit Using Amorphous In-Ga-Zn-Oxide TFTS,”, IDW '09 : Proceedings of the 16th International Display Workshops, 2009, pp. 689-692.Applicant
- Park.J et al., “Amorphous Indium-Gallium-Zinc Oxide TFTS and Their Application for Large Size Amoled,”, AM-FPD '08 Digest of Technical Papers, Jul. 2, 2008, pp. 275-277.Applicant
- Park.S et al., “Challenge to Future Displays: Transparent AM-Oled Driven by Peald Grown ZNO TFT,”, IMID '07 Digest, 2007, pp. 1249-1252.Applicant
- Godo.H et al., “Temperature Dependence of Characteristics and Electronic Structure for Amorphous In-Ga-Zn-Oxide TFT,”, AM-FPD '09 Digest of Technical Papers, Jul. 1, 2009, pp. 41-44.Applicant
- Osada.T at al., “Development of Driver-Integrated Panel Using Amorphous In-Ga-Zn-Oxide TFT,”, AM-FPD '09 Digest of Technical Papers, Jul. 1, 2009, pp. 33-36.Applicant
- Hirao.T et al., “Novel Top-Gate Zinc Oxide Thin-Film Transistors (ZNO TFTS) for AMLCDS,”, Journal of the SID , 2007, vol. 15, No. 1, pp. 17-22.Applicant
- Hosono.H, “68.3:Invited Paper:Transparent Amorphous Oxide Semiconductors for High Performance TFT,”, SID Digest '07 : SID International Symposium Digest of Technical Papers, 2007, vol. 38, pp. 1830-1833.Applicant
- Godo.H et al., “P-9:Numerical Analysis on Temperature Dependence of Characteristics of Amorphous In-Ga-Zn-Oxide TFT,”, SID Digest '09 : SID International Symposium Digest of Technical Papers, May 31, 2009, pp. 1110-1112.Applicant
- Ohara.H et al., “21.3:4.0 In. QVGA Amoled Display Using In-Ga-Zn-Oxide TFTS With a Novel Passivation Layer,”, SID Digest '09 : SID International Symposium Digest of Technical Papers, May 31, 2009, pp. 284-287.Applicant
- Miyasaka.M, “58.2 Invited Paper : Suftla Flexible Microelectronics on Their Way to Business,”, SID Digest '07 : SID International Symposium Digest of Technical Papers, 2007, vol. 38, pp. 1673-1676.Applicant
- Chern.H at al., “An Analytical Model for the Above-Threshold Characteristics of Polysilicon Thin-Film Transistors,”, IEEE Transactions on Electron Devices, Jul. 1, 1995, vol. 42, No. 7, pp. 1240-1246.Applicant
- Kikuchi.H et al., “39.1:Invited Paper:Optically Isotropic Nano-Structured Liquid Crystal Composites for Display Applications,”, SID Digest '09 : SID International Symposium Digest of Technical Papers, May 31, 2009, pp. 578-581.Applicant
- Asaoka.Y et al., “29.1: Polarizer-Free Reflective LCD Combined With Ultra Low-Power Driving Technology,”, SID Digest '09 : SID International Symposium Digest of Technical Papers, 2009, pp. 395-398.Applicant
- Lee.H et al., “Current Status of, Challenges to, and Perspective View of Am-OLED ,”, IDW '06 : Proceedings of the 13th International Display Workshops, Dec. 7, 2006, pp. 663-666.Applicant
- Kikuchi.H et al., “62.2:Invited Paper:Fast Electro-Optical Switching in Polymer-Stabilized Liquid Crystalline Blue Phases for Display Application,”, SID Digest '07 : SID International Symposium Digest of Technical Papers, 2007, vol. 38, pp. 1737-1740.Applicant
- Kikuchi.H et al., “Polymer-Stabilized Liquid Crystal Blue Phases,”, Nature Materials, Sep. 2, 2002, vol. 1, pp. 64-68.Applicant
- Kimizuka.N. et al., “Spinel,YbFe2O4, and Yb2Fe3O7 Types of Structures for Compounds in the In2O3 and Sc2O3-A2O3-BO Systems [A: Fe, Ga, or Al; B: Mg, Mn, Fe, Ni, Cu, or Zn] at Temperatures over 1000° C,”, Journal of Solid State Chemistry, 1985, vol. 60, pp. 382-384.Applicant
- Kitzerow.H et al., “Observation of Blue Phases in Chiral Networks,”, Liquid Crystals, 1993, vol. 14, No. 3, pp. 911-916.Applicant
- Costello.M et al., “Electron Microscopy of a Cholesteric Liquid Crystal and Its Blue Phase,”, Phys. Rev. A (Physical Review A), May 1, 1984, vol. 29, No. 5, pp. 2957-2959.Applicant
- Meiboom.S et al., “Theory of the Blue Phase of Cholesteric Liquid Crystals,”, Phys. Rev. Lett. (Physical Review Letters), May 4, 1981, vol. 46, No. 18, pp. 1216-1219.Applicant
- Fortunato.E et al., “Wide-Bandgap High-Mobility ZNO Thin-Film Transistors Produced at Room Temperature,”, Appl. Phys. Lett. (Applied Physics Letters) , Sep. 27, 2004, vol. 85, No. 13, pp. 2541-2543.Applicant
- Park.J et al., “Improvements in the Device Characteristics of Amorphous Indium Gallium Zinc Oxide Thin-Film Transistors by Ar Plasma Treatment,”, Appl. Phys. Lett. (Applied Physics Letters) , Jun. 26, 2007, vol. 90, No. 26, pp. 262106-1-262106-3.Applicant
- Hayashi.R et al., “42.1: Invited Paper: Improved Amorphous In-Ga-Zn-O TFTS,”, SID Digest '08 : SID International Symposium Digest of Technical Papers, May 20, 2008, vol. 39, pp. 621-624.Applicant
- Masuda.S et al., “Transparent thin film transistors using ZnO as an active channel layer and their electrical properties,”, J. Appl. Phys. (Journal of Applied Physics) , Feb. 1, 2003, vol. 93, No. 3, pp. 1624-1630.Applicant
- Asakuma.N. at al., “Crystallization and Reduction of Sol-Gel-Derived Zinc Oxide Films by Irradiation With Ultraviolet Lamp,”, Journal of Sol-Gel Science and Technology, 2003, vol. 26, pp. 181-184.Applicant
- Nomura.K et al., “Carrier transport in transparent oxide semiconductor with intrinsic structural randomness probed using single-crystalline InGaO3(ZnO)5 films,”, Appl. Phys. Lett. (Applied Physics Letters) , Sep. 13, 2004, vol. 85, No. 11, pp. 1993-1995.Applicant
- Son.K et al., “42.4L: Late-News Paper: 4 Inch QVGA Amoled Driven by the Threshold Voltage Controlled Amorphous GIZO (Ga2O3-In2O3-ZnO) TFT,”, SID Digest '08 : SID International Symposium Digest of Technical Papers, May 20, 2008, vol. 39, pp. 633-636.Applicant
- Van De Walle.C, “Hydrogen as a Cause of Doping in Zinc Oxide,”, Phys. Rev. Lett. (Physical Review Letters), Jul. 31, 2000, vol. 85, No. 5, pp. 1012-1015.Applicant
- Fung.T et al., “2-D Numerical Simulation of High Performance Amorphous In-Ga-Zn-O TFTs for Flat Panel Displays,”, AM-FPD '08 Digest of Technical Papers, Jul. 2, 2008, pp. 251-252, The Japan Society of Applied Physics.Applicant
- Nakamura, “Synthesis of Homologous Compound with New Long-Period Structure,”, NIRIM Newsletter, Mar. 1, 1995, vol. 150, pp. 1-4.Applicant
- Park.Sang-Hee et al., “42.3: Transparent ZnO Thin Film Transistor for the Application of High Aperture Ratio Bottom Emission AM-OLED Display,”, SID Digest '08 : SID International Symposium Digest of Technical Papers, May 20, 2008, vol. 39, pp. 629-632.Applicant
- Orita.M et al., “Mechanism of Electrical Conductivity of Transparent InGaZnO4,”, Phys. Rev. B (Physical Review. B), Jan. 15, 2000, vol. 61, No. 3, pp. 1811-1816.Applicant
- Nomura.K et al., “Amorphous Oxide Semiconductors for High-Performance Flexible Thin-Film Transistors,”, Jpn. J. Appl. Phys. (Japanese Journal of Applied Physics) , 2006, vol. 45, No. 5B, pp. 4303-4308.Applicant
- Janotti.A et al., “Native Point Defects in ZnO,”, Phys. Rev. B (Physical Review. B), 2007, vol. 76, pp. 165202-1-165202-22.Applicant
- Park.J et al., “Electronic Transport Properties of Amorphous Indium-Gallium-Zinc Oxide Semiconductor Upon Exposure to Water,”, Appl. Phys. Lett. (Applied Physics Letters) , 2008, vol. 92, pp. 072104-1-072104-3.Applicant
- Hsieh.H et al., “P-29:Modeling of Amorphous Oxide Semiconductor Thin Film Transistors and Subgap Density of States,”, SID Digest '08 : SID International Symposium Digest of Technical Papers, 2008, vol. 39, pp. 1277-1280.Applicant
- Janotti.A et al., “Oxygen Vacancies In ZnO,”, Appl. Phys. Lett. (Applied Physics Letters) , 2005, vol. 87, pp. 122102-1-122102-3.Applicant
- Oba.F et al., “Defect energetics in ZnO: A hybrid Hartree-Fock density functional study,”, Phys. Rev. B (Physical Review. B), 2008, vol. 77, pp. 245202-1-245202-6.Applicant
- Orita.M et al., “Amorphous transparent conductive oxide InGaO3(ZnO)m (m<4):a Zn4s conductor,”, Philosophical Magazine, 2001, vol. 81, No. 5, pp. 501-515.Applicant
- Hosono.H et al., “Working hypothesis to explore novel wide band gap electrically conducting amorphous oxides and examples,”, J. Non-Cryst. Solids (Journal of Non-Crystalline Solids), 1996, vol. 198-200, pp. 165-169.Applicant
- Mo.Y et al., “Amorphous Oxide TFT Backplanes for Large Size AMOLED Displays,”, IDW '08 : Proceedings of the 6th International Display Workshops, Dec. 3, 2008, pp. 581-584.Applicant
- Kim.S et al., “High-Performance oxide thin film transistors passivated by various gas plasmas,”, 214th ECS Meeting, 2008, No. 2317.Applicant
- Clark.S et al., “First Principles Methods Using CASTEP,”, Zeitschrift fur Kristallographie, 2005, vol. 220, pp. 567-570.Applicant
- Lany.S et al., “Dopability, Intrinsic Conductivity, and Nonstoichiometry of Transparent Conducting Oxides,”, Phys. Rev. Lett. (Physical Review Letters), Jan. 26, 2007, vol. 98, pp. 045501-1-045501-4.Applicant
- Park,J et al., “Dry etching of ZnO films and plasma-induced damage to optical properties,”, J. Vac. Sci. Technol. B (Journal of Vacuum Science & Technology B), Mar. 1, 2003, vol. 21, No. 2, pp. 800-803.Applicant
- Oh.M et al., “Improving the Gate Stability of Zno Thin-Film Transistors With Aluminum Oxide Dielectric Layers,”, J. Electrochem. Soc. (Journal of the Electrochemical Society), 2008, vol. 155, No. 12, pp. H1009-H1014.Applicant
- Ueno.K et al., “Field-Effect Transistor on SrTiO3 With Sputtered Al2O3 Gate Insulator,”, Appl. Phys. Lett. (Applied Physics Letters) , Sep. 1, 2003, vol. 83, No. 9, pp. 1755-1757.Applicant
- Park.J et al., “Amorphous Indium-Gallium-Zinc Oxide TFTS and Their Application for Large Size AMOLED,”, AM-FPD '08 Digest of Technical Papers, Jul. 2, 2008, pp. 275-278.Applicant