US 8,237,289 B2Grant
System in package device
Issue Date:2012-08-07
•13 Claims
•22 Drawing Sheets
Abstract
A system in package device according to an example of the present invention includes a package substrate, an external terminal which is arranged on one face side or the other face side of the package substrate, a first chip which is arranged on the other face side of the package substrate, a second chip which is arranged on the first chip, and bumps which are arranged between the first chip and the second chip. A signal to be input into the external terminal is input into the first chip via the second chip.
Metadata
Assignee
- Kabushiki Kaisha Toshiba
Inventor
- Yukihiro Urakawa
Application Information
Application Number:US 12/020,190
Filing Date:2008-01-25
Priority Date:2007-01-30
Art Unit:2818
Classifications
IPC:
H01L23/48
Patent Drawings (22 sheets)
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is based upon and claims the benefit of priority from prior Japanese Patent Applications No. 2007-020012, filed Jan. 30, 2007; and No. 2007-020013, filed Jan. 30, 2007, the entire contents of both of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to a system in package device.
[0004] 2. Description of the Related Art
[0005] (1) Problem of First System-in-Package Device
[0006] In recent years, in order to combine high performance and low cost of systems, techniques such as SoC (system on chip) where a system is formed on one chip and SIP (system in package) where a system is formed in one package have been developed (for example, see Jpn. Pat. Appln. KOKAI Publication Nos. 7-176684 and 2002-270759).
[0007] In the case of SoC, function blocks are formed on one chip.
[0008] It is, however, difficult to form the function blocks according to a common process. For example, in high-speed systems having a logic circuit and an interface circuit, the logic circuit is formed by a thin film CMOS process, and the interface circuit is formed by a thick film CMOS process.
[0009] For this reason, it is necessary to optimize the process and repress an increase in cost, but this becomes more difficult as the process generations roll by.
[0010] On the contrary, in SIP, a problem of the cost in the SoC does not arise.
[0011] In the case of SIP, since chips are formed in one package, a logic circuit and an interface circuit can be formed on different chips.
[0012] When the performance of systems becomes highly sophisticated, however, the number of chip terminals increases. For this reason, it is difficult to connect chips by wire bonding.
[0013] A technique for connecting chips using a bump is, therefore, proposed.
[0014] According to this technique, two chips having different functions are stacked via a bump. For example, a memory chip is arranged on a logic chip and both of them are connected to each other via a bump.
[0015] In this case, the upper chip is smaller than the lower chip and is flip-chip bonded to the lower chip. For this reason, the front face of the upper chip (the face on which an element is formed; the same applies to the following) faces the front face of the lower chip, and thus a signal terminal of the upper chip is not directly connected to an external terminal of the package.
[0016] That is, the upper chip transmits and receives a signal (except for a power-supply voltage) only to/from an element or a circuit formed in the lower chip.
[0017] In order to structure high-performance systems, however, the signal terminal of the upper chip is occasionally preferably connected directly to the external terminal of the package without an element or a circuit in the lower chip.
[0018] (2) Problem of Second System-in-Package Device
[0019] In recent years, in order to combine the high performance and the low cost of the systems, SIP (system in package) where a system is formed in one package has been developed (for example, see Jpn. Pat. Appln. KOKAI Publication No. 2001-24150).
[0020] In the case of SIP, since chips are formed in one package, a wiring technique for connecting the chips is important.
[0021] SIP includes a parallel type SIP in which chips are arranged in parallel and these chips are connected by a bonding wire, and stacking type SIP in which chips are stacked and these chips are connected by a bump.
[0022] In the case of the parallel type SIP, when the number of chip terminals increases according to the heightening of the performance of the systems, the chips cannot be connected to each other in the package.
[0023] On the contrary, in the case of the stacking type SIP, a micro-bump having a diameter of 100 μm or less is used so that even if the number of chip terminals increases, the connection of the chips can be sufficiently secured.
[0024] In the stacking type SIP, however, it is difficult to add a heat spreader to the package due to its structure.
BRIEF SUMMARY OF THE INVENTION
[0025] (1) First System-in-Package Device
[0026] This system in package device comprises a package substrate an external terminal which is arranged on one face side or the other face side of the package substrate, a first chip which is arranged on the other face side of the package substrate, a second chip which is arranged on the first chip, and bumps which are arranged between the first chip and the second chip. A signal to be input into the external terminal is input into the first chip via the second chip.
[0027] This system in package device comprises a package substrate, an external terminal which is arranged on one face side or the other face side of the package substrate, a first chip which is arranged on the other face side of the package substrate, a second chip which is arranged on the first chip and the package substrate so as to straddle them, a first bump which is arranged between the first chip and the second chip, and a second bump which is arranged between the package substrate and the second chip. A signal to be input into the external terminal is input into the first chip via the second chip.
[0028] (2) Second System-in-Package Device
[0029] This system in package device comprises a package substrate, an external terminal which is arranged on one face side of the package substrate, first and second chips which are arranged side by side on the other face side of the package substrate, a third chip which is arranged to straddle the first and second chips and covers only some portions of the front faces of the first and second chips, and a bump which is arranged between the first and second chips and the third chip. The first and second chips transmit and receive a signal via the third chip.
[0030] This system in package device comprises a heat spreader, a package substrate which is arranged along an edge of one face side of the heat spreader, an external terminal which is arranged on the package substrate, first and second chips which are arranged side by side on a center of the one face side of the heat spreader, a third chip which is arranged to straddle the first and second chips, and covers only some portions of front faces of the first and second chips, and a bump which is arranged between the first and second chips and the third chip. The first and second chips transmit and receive a signal via the third chip.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING
[0031] FIG. 1 is a plan view illustrating a first SIP according to a first example;
[0032] FIG. 2 is a cross-sectional view taken along a line II-II of FIG. 1 ;
[0033] FIG. 3 is a plan view illustrating a modified example of the first example;
[0034] FIG. 4 is a cross-sectional view taken along a line IV-IV of FIG. 3 ;
[0035] FIG. 5 is a plan view illustrating the first SIP according to a second example;
[0036] FIG. 6 is a cross-sectional view taken along a line VI-VI of FIG. 5 ;
[0037] FIG. 7 is a plan view illustrating a modified example of the second example;
[0038] FIG. 8 is a cross-sectional view taken along a line VIII-VIII of FIG. 7 ;
[0039] FIG. 9 is a plan view illustrating the first SIP according to a third example;
[0040] FIG. 10 is a cross-sectional view taken along a line X-X of FIG. 9 ;
[0041] FIG. 11 is a plan view illustrating a first modified example of the third example;
[0042] FIG. 12 is a cross-sectional view taken along a line XII-XII of FIG. 11 ;
[0043] FIG. 13 is a plan view illustrating a second modified example of the third example;
[0044] FIG. 14 is a plan view illustrating a second SIP according to a first example;
[0045] FIG. 15 is a cross-sectional view taken along a line XV-XV of FIG. 14 ;
[0046] FIG. 16 is a plan view illustrating a modified example of the first example;
[0047] FIG. 17 is a plan view illustrating the second SIP according to a second example;
[0048] FIG. 18 is a cross-sectional view taken along a line XVIII-XVIII of FIG. 17 ;
[0049] FIG. 19 is a plan view illustrating a modified example of the second example;
[0050] FIG. 20 is a cross-sectional view illustrating an applied example of the second SIP;
[0051] FIG. 21 is a cross-sectional view illustrating an applied example of the second SIP;
[0052] FIG. 22 is a cross-sectional view illustrating an applied example of the second SIP; and
[0053] FIG. 23 is a cross-sectional view illustrating an applied example of the second SIP.
DETAILED DESCRIPTION OF THE INVENTION
[0054] A system in package device of an aspect of the present invention will be described below in detail with reference to the accompanying drawings.
[A] First System-in-Package Device
1. Outline
[0055] (1) The present invention is directed to a system in package device which has two chips (first and second chips) stacked on each other via a bump. A constitution of such a system in package device, in which a signal to be input into an external terminal of the package is input into a lower chip (first chip) via an upper chip (second chip), is proposed.
[0056] Specifically, firstly, a signal to be input into the external terminal of the package is input into a logic circuit in the upper chip via a conductive layer in the lower chip, and is transferred from the upper chip to the lower chip. That is, the conductive layer as a lead to the upper chip is provided in the lower chip, so that the above constitution is realized.
[0057] Secondly, a through hole which pierces the upper chip is formed in the upper chip, and a conductive layer is formed on a rear face of the upper chip (the face on which an element is not formed; the same applies also to the following description). A signal to be input into the external terminal of the package is input into the logic circuit in the second chip via the conductive layer and the through hole, so that the above constitution is realized.
[0058] Thirdly, the upper chip is arranged so as to straddle the lower chip and a package substrate (convex portion). That is, a constitution where the upper chip is connected to both of the lower chip and the package substrate via a bump is adopted, so that the above constitution is realized.
[0059] The signal means data, and does not include a power-supply voltage.
[0060] According to such a constitution, the performance of the system in package device having the two chips stacked on each other via the bump can be heightened.
2. Examples
[0061] Some examples which seem to be the best will be described below.
(1) First Example
A. Constitution
[0062] FIG. 1 illustrates a system in package device according to a first example. FIG. 2 is a cross-sectional view taken along a line II-II of FIG. 1 .
[0063] External terminals 12 of an array pattern are arranged on one face side of a package substrate 11. In this example, the external terminals 12 are bumps, but the external terminals are not limited to them and thus may be pins, pads or the like.
[0064] A lower chip 13 is arranged on the other face side of the package substrate 11. The lower chip 13 is, for example, a logic chip. The rear face of the lower chip 13 is jointed to the other face of the package substrate 11 by adhesive.
[0065] An upper chip 14 is arranged on the lower chip 13. The upper chip 14 is a chip having a function different from the lower chip 13, such as an interface chip.
[0066] Bumps of array pattern (for example, micro-bumps having diameter of 100 μm or less) 15 are arranged between the lower chip 13 and the upper chip 14.
[0067] Since the upper chip 14 is flip-chip bonded to the lower chip 13, the front face of the lower chip 13 is opposed to the front face of the upper chip 14.
[0068] Since a size of the upper chip 14 is smaller than a size of the lower chip 13, the front face of the upper chip 14 is completely hidden when viewed from above the package substrate 11.
[0069] One of the external terminals 12 is a signal terminal.
[0070] In this example, a signal to be input into the signal terminal is input into the lower chip 13 via the upper chip 14. The signal is transmitted to the signal terminal from the lower chip 13 via the upper chip 14, so as to be output to the outside of the package.
[0071] That is, the lower chip 13 has conductive layers 16 as leads to the upper chip 14. The package substrate 11 has conductive layers 18, and a conductive line 19 which connects one of the external terminals 12 to the conductive layer 18. A bonding wire 17 connects the conductive layers 16 and 18.
[0072] As a result, the external terminal 12 as the signal terminal is connected to the upper chip 14 via the bump 15, the conductive layer 16, the bonding wire 17, the conductive layer 18 and the conductive line 19.
B. Modified Example
[0073] FIG. 3 illustrates a system in package device according to a modified example of the first example. FIG. 4 is a cross-sectional view taken along a line IV-IV of FIG. 3 .
[0074] The feature of this modified example is that the external terminals 12 of the array pattern are arranged on the other face side of the package substrate 11. Accordingly, the constitution in FIGS. 1 and 2 is partially changed.
[0075] A heat spreader 31 is arranged on one face side of the package substrate 11. This modified example has an advantage that the large heat spreader 31 can be arranged on one face side of the package substrate 11.
[0076] A convex portion (package substrate) 20 is arranged along an edge of the other face side of the package substrate 11. The convex portion 20 is jointed to the package substrate 11 by adhesive.
[0077] The external terminals 12 of the array pattern are arranged on the convex portion 20.
[0078] The lower chip 13 is arranged on a center of the other face side of the package substrate 11. The rear face of the lower chip 13 is jointed to the other face of the package substrate 11 by adhesive.
[0079] The upper chip 14 is arranged on the lower chip 13. The upper chip 14 is a chip which has a function different from that of the lower chip 13.
[0080] The bumps 15 of the array pattern are arranged between the lower chip 13 and the upper chip 14.
[0081] Since the upper chip 14 is flip-chip bonded to the lower chip 13, similarly to the constitution in FIGS. 1 and 2 , the front face of the lower chip 13 is opposed to the front face of the upper chip 14.
[0082] Since the size of the upper chip 14 is smaller than the size of the lower chip 13, the front face of the upper chip 14 is completely hidden when viewed from above the package substrate 11.
[0083] Similarly to the constitution in FIGS. 1 and 2 , a signal to be input into the external terminal 12 is input into the lower chip 13 via the upper chip 14. The signal is transmitted to the external terminal 12 from the lower chip 13 via the upper chip 14 so as to be output to the outside of the package.
[0084] That is, the lower chip 13 has the conductive layers 16 as the leads to the upper chip 14. The package substrate 11 has the conductive layers 18, and the bonding wires 17 connect the conductive layers 16 and 18, respectively. The convex portion 20 has the conductive line 19 which connects one of the external terminals 12 to the conductive layer 18.
[0085] As a result, the external terminal 12 as the signal terminal is connected to the upper chip 14 via the bump 15, the conductive layer 16, the bonding wire 17, the conductive layer 18 and the conductive line 19.
[0086] Since a cavity CA is provided on a part of the convex portion 20, the conductive layers 16 and 18 can be jointed to each other by the bonding wires 17.
C. Summary
[0087] According to the first example, since the lower chip has the conductive layer as the lead to the upper chip, the performance of the system in package device can be heightened.
(2) Second Example
A. Constitution
[0088] FIG. 5 illustrates a system in package device according to a second example. FIG. 6 is a cross-sectional view taken along a line VI-VI of FIG. 5 .
[0089] The external terminals 12 of the array pattern are arranged on one face side of the package substrate 11. In this example, the external terminals 12 are bumps, but the external terminals are not limited to them and thus may be pins, pads or the like.
[0090] The lower chip 13 is arranged on the other face side of the package substrate 11. The lower chip 13 is, for example, a logic chip. The rear face of the lower chip 13 is jointed to the other face of the package substrate 11 by adhesive.
[0091] The upper chip 14 is arranged on the lower chip 13. The upper chip 14 is a chip having a function different from that of the lower chip 13, such as an interface chip.
[0092] Bumps of an array pattern (for example, micro-bumps having diameter of 100 μm or less) 15 are arranged between the lower chip 13 and the upper chip 14.
[0093] Since the upper chip 14 is flip-chip bonded to the lower chip 13, the front face of the lower chip 13 is opposed to the front face of the upper chip 14.
[0094] Since the size of the upper chip 14 is smaller than that of the lower chip 13, the front face of the upper chip 14 is completely hidden when viewed from above the package substrate 11.
[0095] In this example, a signal to be input into the external terminal 12 is input into the lower chip 13 via the upper chip 14. The signal is transmitted to the external terminal 12 from the lower chip 13 via the upper chip 14 so as to be output to the outside of the package.
[0096] That is, the upper chip 14 has through holes 21 which pierce the chip 14 and the conductive layers 16 which are arranged on the rear face of the chip 14. The package substrate 11 has the conductive layers 18, and the conductive line 19 which connects one of the external terminals 12 to the conductive layer 18. The bonding wire 17 connects the conductive layers 16 and 18.
[0097] As a result, the external terminal 12 as the signal terminal is connected to the upper chip 14 via the conductive layer 16, the bonding wire 17, the conductive layer 18, the conductive line 19 and the through hole 21.
B. Modified Example
[0098] FIG. 7 illustrates a system in package device according to a modified example of the second example. FIG. 8 is a cross-sectional view taken along a line VIII-VIII of FIG. 7 .
[0099] The feature of this modified example is that the external terminals 12 of the array pattern are arranged on the other face side of the package substrate 11. Accordingly, the constitution in FIGS. 5 and 6 is partially changed.
[0100] The heat spreader 31 is arranged on one face side of the package substrate 11. This modified example has an advantage that the large heat spreader 31 can be arranged on one side face of the package substrate 11.
[0101] The convex portion (package substrate) 20 is arranged along the edge of the other face side of the package substrate 11. The convex portion 20 is jointed to the package substrate 11 by adhesive.
[0102] The external terminals 12 of the array pattern are arranged on the convex portion 20.
[0103] The lower chip 13 is arranged on the center of the other face side of the package substrate 11. The rear face of the lower chip 13 is jointed to the other face of the package substrate 11 by adhesive.
[0104] The upper chip 14 is arranged on the lower chip 13. The upper chip 14 is a chip which has a function different from that of the lower chip 13.
[0105] The bumps 15 of the array pattern are arranged between the lower chip 13 and the upper chip 14.
[0106] Since the upper chip 14 is flip-chip bonded to the lower chip 13, the front face of the lower chip 13 is opposed to the front face of the upper chip 14 similarly to the constitution in FIGS. 5 and 6 .
[0107] Since the size of the upper chip 14 is smaller than the size of the lower chip 13, the face of the upper chip 14 is completely hidden when viewed from above the package substrate 11.
[0108] Similarly to the constitution in FIGS. 5 and 6 , the signal to be input into the external terminal 12 is input into the lower chip 13 via the upper chip 14. The signal is transmitted to the external terminals 12 from the lower chip 13 via the upper chip 14 so as to be output to the outside of the package.
[0109] That is, the upper chip 14 has the through holes 21 which pierce the chip 14, and the conductive layers 16 which are arranged on the rear face of the chip. The package substrate 11 has the conductive layers is, and the bonding wires 17 connect the conductive layers 16 and 18. The convex portion 20 has the conductive line 19 which connects one of the external terminals 12 to the conductive layer 18.
[0110] As a result, the external terminal 12 as the signal terminal is connected to the upper chip 14 via the conductive layer 16, the bonding wire 17, the conductive layer 18, the conductive line 19 and the through hole 21.
[0111] Since the cavity CA is provided on a part of the convex portion 20, the conductive layers 16 and 18 can be jointed by the bonding wire 17.
C. Summary
[0112] According to the second example, since the upper chip has the through holes which pierce the chip and the conductive layers arranged on the rear face of the chip, the performance of the system in package device can be heightened.
[0113] In case of the second example is compared with the first example, the cost increases due to the provision of the through holes. The conductive layers as the leads to the upper chip do not have to be provided on the lower chip. For this reason, the second example has an advantage that the size of the lower chip can be reduced.
(3) Third Example
A. Constitution
[0114] FIG. 9 illustrates a system in package device according to a third example. FIG. 10 is a cross-sectional view taken along a line X-X of FIG. 9 .
[0115] The external terminals 12 of the array pattern are arranged on one face side of the package substrate 11. In this example, the external terminals 12 are bumps, but the external terminals are not limited to them and thus may be pins, pads or the like.
[0116] The convex portion (package substrate) 20 is arranged along the edge of the other end face of the package substrate 11. The convex portion 20 is jointed to the package substrate 11 by adhesive.
[0117] The convex portion 20 can be provided also by providing a concave portion on the center of the package substrate 11.
[0118] The lower chip 13 is arranged on the center of the other face side of the package substrate 11. The lower chip 13 is, for example, a logic chip. The rear face of the lower chip 13 is bonded to the other face of the package substrate 11 by adhesive.
[0119] The upper face of the lower chip 13 approximately matches with the upper face of the convex portion 20.
[0120] The upper chip 14 is arranged to straddle the lower chip 13 and the convex portion 20. The upper chip 14 is a chip having a function different from that of the lower chip 13, such as an interface chip.
[0121] Bumps of the array pattern (for example, micro-bumps having diameter of 100 μm or less) 15 are arranged between the lower chip 13 and the upper chip 14. Bumps of the array pattern (for example, normal flip-chip bumps having diameter of more than 100 μm) 22 are arranged between the convex portion 20 and the upper chip 14.
[0122] One of the external terminals 12 is a signal terminal.
[0123] In this example, the signal to be input into the signal terminal is input into the lower chip 13 via the upper chip 14. The signal is transmitted to the signal terminal from the lower chip 13 via the upper chip 14 so as to be output to the outside of the package.
[0124] That is, the convex portion 20 has the conductive layers 18, and one bump 22 as the signal terminal is connected to the conductive layer 18. The package substrate 11 and the convex portion 20 have the conductive line 19 which connects one of the external terminals 12 to the conductive layer 18.
[0125] As a result, the external terminal 12 as the signal terminal is connected to the upper chip 14 via the conductive layer 18, the conductive line 19 and the bump 22.
B. First Modified Example
[0126] FIG. 11 illustrates a system in package device according to a first modified example of the third example. FIG. 12 is a cross-sectional view taken along a line XII-XII of FIG. 11 .
[0127] The feature of the first modified example is that the external terminals 12 of the array pattern are arranged on the other face side of the package substrate 11. Accordingly, the constitution in FIGS. 9 and 10 is partially changed.
[0128] The heat spreader 31 is arranged on one face side of the package substrate 11. The first modified example has an advantage that the large heat spreader 31 can be arranged on one face side of the package substrate 11.
[0129] Convex portions (package substrates) 20A and 20B are arranged along the edge of the other face side of the package substrate 11. The convex portions 20A and 208 are jointed to the package substrate 11 by adhesive.
[0130] The convex portion 20A can be formed also by providing a concave portion on the center of the package substrate 11.
[0131] The external terminals 12 of the array pattern are arranged on the convex portion 20B.
[0132] The lower chip 13 is arranged on the center of the other face side of the package substrate 11. The rear face of the lower chip 13 is jointed to the other face of the package substrate 11 by adhesive.
[0133] The upper chip 14 is arranged on the lower chip 13 and the convex portion 20A so as to straddle both of them. A part of the convex portion 20A is not covered with the convex portion 20B so that the upper chip 14 can be arranged. The upper face of the lower chip 13 is approximately on a level with the upper face of the convex portion 20A.
[0134] The upper chip 14 is a chip which has a function different from that of the lower chip 13.
[0135] The bumps 15 of the array pattern are arranged between the lower chip 13 and the upper chip 14. The bumps 22 of the array pattern are arranged between the convex portion 20A and the upper chip 14.
[0136] Similarly to the constitution in FIGS. 9 and 10 , the signal to be input into the external terminal 12 is input into the lower chip 13 via the upper chip 14. The signal is transmitted to the external terminal 12 from the lower chip 13 via the upper chip 14 so as to be output to the outside of the package.
[0137] That is, the convex portion 20A has the conductive layers 18, and one bump 22 as the signal terminal is connected to the conductive layer 18. The convex portions 20A and 20B have the conductive line 19 which connects one of the external terminals 12 to the conductive layer 18.
[0138] As a result, the external terminal 12 as the signal terminal is connected to the upper chip 14 via the conductive layer 18, the conductive line 19 and the bump 22.
[0139] In the first modified example, the package substrate 11 can be omitted. In this case, the lower chip 13, and the convex portions (package substrate) 20A and 20B are mounted directly on the head spreader 31.
C. Second Modified Example
[0140] FIG. 13 illustrates a system in package device according to a second modified example of the third example.
[0141] The feature of the second modified example is that upper chips 14A, 14H, 14C and 14D are arranged on the lower chip 13 and the convex portion 20, and the other parts of the constitution are the same as those of the constitution in FIGS. 9 and 10 .
[0142] In this example, the four upper chips 14A, 14B, 14C and 14D are arranged in such a manner that each chip is arranged on each side of the lower chip 13, respectively. However, the number of the chips is not limited to that in this example, and thus any number is acceptable as long as it is two or more.
[0143] The upper chips 14A, 14B, 14C and 14D have the same feature as that of the upper chip 14 in the constitution of FIGS. 9 and 10 .
[0144] That is, bumps 15A, 15B, 14C and 15D are arranged between the lower chip 13 and the upper chips 14A, 14B, 14C and 14D, respectively, and bumps 22A, 22B, 22C and 22D are arranged between the convex portion 20 and the upper chips 14A, 14B, 14C and 14D, respectively.
[0145] The signal to be input into the external terminal 12 is input into the lower chip 13 via one of the upper chips 14A, 14B, 14C and 14D. The signal is transmitted to the external terminal 12 from the lower chip 13 via one of the upper chips 14A, 14B, 14C and 14D so as to be output to the outside of the package.
[0146] The functions of the upper chips 14A, 14B, 14C and 14D may be the same as one another or may be varied from one another.
[0147] For example, the upper chip 14A can be a high-speed interface chip, and the residual three upper chips 14B, 14C and 14D can be normal CMOS interface chips.
D. Summary
[0148] According to the third example, since the upper chips are arranged on the lower chip and the convex portion of the package substrate so as to straddle them, the performance of the system in package device can be heightened.
3. Application Example
[0149] The examples of the present invention can be applied to high-speed communication systems.
[0150] For example, when the lower chip in the first to third examples is the logic chip and the upper chip is the interface chip, the signal is input/output to/from the logic chip via the interface chip, thereby enabling high-speed communication.
[0151] Examples of the interface chip include SerDes (serializer/deserializer) I/O chip.
[0152] In this case, for example, serial data is input into the upper chip from an external bus via the external terminal. The serial data is converted into parallel data in the upper chip, and the parallel data is output to the lower chip.
[0153] For example, the parallel data is input from the lower chip into the upper chip. The parallel data is converted into serial data in the upper chip, and the serial data is output to the external bus via the external terminal.
4. Conclusion
[0154] According to the present invention, the performance of the system in package device having the two chips stacked on each other via the bump can be heightened.
[0155] Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.
[B] Second System-in-Package Device
1. Outline
[0156] The present invention proposes a constitution in which two chips (first and second chips) arranged in parallel are connected to each other by a wiring chip (third chip).
[0157] Specifically, the wiring chip straddles the two chips and covers only some portions of front faces of the two chips. The two chips are connected to the wiring chip by a bump.
[0158] As a result, even if the number of terminals of the chips increases according to the heightening of the performance of the system, the connection between the two chips can be secured in the package. Since the wiring chip does not completely cover the front faces of the two chips, the connection of the two chips to the external terminals of the package can be secured.
[0159] Further, when the package substrate is arranged along the edge of one face side of the heat spreader and the two chips are arranged side by side on the center of the heat spreaders this constitution can contribute to improvement in a radiation property.
[0160] The front face of the chip is the face on which an element or a conductive layer is formed, and the rear face of the chip is the face on which neither an element nor a conductive layer is formed.
2. Examples
[0161] Some examples which seem to be the best will be described below.
(1) First Example
A. Constitution
[0162] FIG. 14 illustrates a system in package device according to a first example. FIG. 15 is a cross-sectional view taken along a line XV-XV of FIG. 14 .
[0163] The external terminals 12 of the array pattern are arranged on one face side of the package substrate 11. In this example, the external terminals 12 are bumps, but the external terminals are not limited to them and thus may be pins, pads or the like.
[0164] Two LSI chips 13 and 14 are arranged on the other face side of the package substrate 11 side by side. The LSI chip 13 is, for example, a logic chip, and the LSI chip 14 is, for example, a memory chip. The rear faces of the LSI chips 13 and 14 are jointed to the other face of the package substrate 11 by adhesive.
[0165] A wiring chip 15 is arranged on the LSI chips 13 and 14 so as to straddle them. The wiring chip 15 has a conductive layer which connects the LSI chips 13 and 14.
[0166] As a result, the LSI chips 13 and 14 transmit and receive a signal via the wiring chip 15. The wiring chip 15 has only the conductive layer which connects the LSI chips 13 and 14, for example.
[0167] The wiring chip 15 covers only some portions on the front faces of the LSI chips 13 and 14. In order to realize this constitution, for example, an area of the front face of the wiring chip 15 may be made to be smaller than a total area of the front faces of the LSI chips 13 and 14.
[0168] As a result, the connection between the LSI chips 13 and 14 and the external terminals 12 is secured. That is, the LSI chips 13 and 14 are connected to the external terminals 12 via the bonding wires 17, the conductive layers 18 and the conductive lines 19.
[0169] The bumps of the array pattern (for example, micro-bumps having diameter of 100 μm or less) 16 are arranged between the LSI chips 13 and 14 and the wiring chip 15.
[0170] Since the wiring chip 15 is flip-chip bonded to the LSI chips 13 and 14, the front faces of the LSI chips 13 and 14 are opposed to the front face of the wiring chip 15.
[0171] As a result, even if the number of the terminals of the chips increases according to the heightening of the performance of the system, the connection of the LSI chips 13 and 14 in the package can be secured.
B. Modified Example
[0172] FIG. 16 illustrates a system in package device according to a modified example of the first example. Since a plan view of the system in package device in FIG. 16 is the same as FIG. 14 , it is omitted.
[0173] The feature of this modified example is that an LSI chip (bus bridge) 21 having a bus and a bus controller is used instead of the wiring chip 15 in FIGS. 14 and 15 . The other parts are the same as those in FIGS. 14 and 15 .
[0174] The LSI chip 21 is arranged on the LSI chips 13 and 14 so as to straddle them. The LSI chip 21 has a bus which connects the LSI chips 13 and 14, and the bus controller which controls the connection between the LSI chips 13 and 14.
[0175] The LSI chip 21 covers only some portions of the front faces of the LSI chips 13 and 14. In order to realize this constitution, for example, an area of the front face of the LSI chip 21 may be made to be smaller than a total area of the front faces of the LSI chips 13 and 14.
C. Summary
[0176] According to the first example, the constitution which can cope with the increase in the number of the terminals of the chips can be realized in the parallel type system in package device.
(2) Second Example
A. Constitution
[0177] FIG. 17 illustrates a system in package device according to a second example. FIG. 18 is a cross-sectional view taken along a line XVIII-XVIII of FIG. 17 .
[0178] The package substrates 20A and 20B are arranged along the edge of one face side of the heat spreader 31. The external terminals 12 of the array pattern are arranged on the package substrate 20B. In this example, the external terminals 12 are humps, but the external terminals are not limited to them and thus may be pins, pads or the like.
[0179] The size of the package substrate 20B is smaller than the size of the substrate package 20A, and the package substrate 20A is partially exposed when viewed from above the heat spreader 31. The exposed portions become bonding portions.
[0180] The conductive layers 18 are arranged on the bonding portions, and the conductive layers 18 are connected to the external terminals 12 via the conductive lines 19, respectively.
[0181] The LSI chips 13 and 14 are arranged side by side on the center of one face side of the heat spreader 31. The LSI chip 13 is, for example, a logic chip, and the LSI chip 14 is, for example, a memory chip. The rear faces of the LSI chips 13 and 14 are jointed to the other face of the package substrate 11 by adhesive.
[0182] The wiring chip 15 is arranged on the LSI chips 13 and 14 so as to straddle them. The wiring chip 15 has a conductive layer which connects the LSI chips 13 and 14.
[0183] As a result, the LSI chips 13 and 14 transmit and receive a signal via the wiring chip 15. The wiring chip 15 has only the conductive layer which connects the LSI chips 13 and 14.
[0184] The wiring chip 15 covers only some portions on the front faces of the LSI chips 13 and 14. In order to realize this constitution, for example, the area of the front face of the wiring chip 15 may be made to be smaller than the total area of the front faces of the LSI chips 13 and 14.
[0185] As a result, the connection between the LSI chips 13 and 14, and the external terminals 12 of the package is secured. That is, the LSI chips 13 and 14 are connected to the external terminals 12 via the bonding wires 17, the conductive layers 18 and the conductive lines 19.
[0186] The bumps (for example, micro-bumps having diameter of 100 μm or less) 16 are arranged between the LSI chips 13 and 14 and the wiring chip 15.
[0187] Since the wiring chip 15 is flip-chip bonded to the LSI chips 13 and 14, the front faces of the LSI chips 13 and 14 are opposed to the front face of the wiring chip 15.
[0188] As a result, even if the number of the terminals of the chips increases according to the heightening of the performance of the system, the connection of the LSI chips 13 and 14 can be secured in the package.
[0189] Further, the heat spreader 31 can be brought into direct contact with the LSI chips 13 and 14, thereby contributing to improvement in the radiation property.
B. Modified Example
[0190] FIG. 19 illustrates a system in package device according to a modified example of the second example. Since a plan view of the system in package device in FIG. 19 is the same as that of FIG. 17 , it is omitted.
[0191] The feature of the modified example is that the LSI chip (bus bridge) 21 having the bus and the bus controller is used instead of the wiring chip 15 in FIGS. 17 and 18 . The other portions are the same as those in FIGS. 17 and 18 .
[0192] The LSI chip 21 is arranged on the LSI chips 13 and 14 so as to straddle them. The LSI chip 21 has the bus which connects the LSI chips 13 and 14, and the bus controller which controls the connection of the LSI is chips 13 and 14.
[0193] The LSI chip 21 covers only some portions of the front faces of the LSI chips 13 and 14. In order to realize this constitution, for example, the area of the front face of the LSI chip 21 may be made to be smaller than the total area of the front faces of the LSI chips 13 and 14.
C. Summary
[0194] According to the second example, the constitution which can cope with the increase in the number of the terminals of the chips and the constitution having good radiation property can be realized simultaneously in the parallel type system in package device.
3. Application Example
[0195] The examples of the present invention can be applied to memory systems.
[0196] For example, when the LSI chip 13 in FIGS. 14 to 19 is a logic chip, and the LSI chip 14 is a memory chip, electronic devices such as PDA (personal digital assistance) which are mounted with the system in package device according to the examples of the present invention can be manufactured. In this case, a microcomputer chip may be mounted into the package.
[0197] The examples of the present invention can be applied to logic systems.
[0198] For example, an interface circuit is formed in the wiring chip 15 or the LSI chip 21 of FIGS. 14 to 19 . In this case, a signal is input/output into/from the LSI chips 13 and 14 via the interface circuit in the wiring chip 15 or the LSI chip 21.
[0199] For example, in the case of the constitution shown in FIGS. 20 and 21 , the LSI chip (logic chip) 13 is connected to one of the external terminals 12 via the interface circuit in the wiring chip 15, the conductive line 22 in the LSI chip 14, the bonding wire 17, the conductive layer 18 and the conductive line 19.
[0200] In the case of the constitution shown in FIGS. 22 and 23 , the LSI chip (logic chip) 13 is connected to one of the external terminals 12 via the interface circuit in the wiring chip 15, the through hole 21 in the wiring chip 15, the conductive layer 22 on the rear face of the wiring chip 15, the bonding wire 17, the conductive layer 18 and the conductive line 19.
4. Conclusion
[0201] According to the present invention, in the parallel type system in package device, the constitution which can cope with the increase in the number of the terminals of the chips and the structure having the excellent radiation property can be realized.
[0202] Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.
Claims
What is claimed is:
1. A system in package device comprising:
a package substrate;
an external signal terminal arranged on a first face side of the package substrate, wherein the second face side is opposite the first face side;
a logic chip arranged on the second face side of the package substrate;
an interface chip arranged on the logic chip so the logic chip is between the interface chip and the second face side of the package substrate; and
bumps arranged between the logic chip and the interface chip,
wherein an input signal is transferred from the external signal terminal to a logic area on the logic chip through the interface chip, wherein the input signal is first transferred from the external signal terminal to the interface chip and then transferred from the interface chip to the logic area of the logic chip via one or more of the bumps.
2. The system in package device of claim 1, wherein the interface chip is smaller than the logic chip.
3. The system in package device of claim 1, wherein an output signal is transferred from the logic chip to the external signal terminal through the interface chip, wherein the output signal is first transferred from the logic chip to the interface chip via one or more of the bumps and then transferred from the interface chip to the external signal terminal.
4. The system in package device of claim 1, wherein the interface chip is flip-chip bonded to the logic chip.
5. The system in package device of claim 1, wherein the input signal is transferred from the external signal terminal to the interface chip via a bonding wire.
6. The system in package device of claim 1, wherein the logic chip has a first conductive layer on a surface of the logic chip where the interface chip is arranged, wherein the input signal is transferred from the external signal terminal to the logic chip via the first conductive layer of the logic chip.
7. The system in package device of claim 6, wherein the first conductive layer of the logic chip is connected to at least one of the bumps.
8. The system in package device of claim 7, wherein the first conductive layer of the logic chip is connected to the bump arranged on an edge of the interface chip.
9. The system in package device of claim 8, wherein the first conductive layer of the logic chip is connected to a bonding wire, wherein the bonding wire is connected to the external signal terminal.
10. The system in package device of claim 9, wherein the input signal is transferred from the external signal terminal to a second conductive layer on the second face side of the package substrate and from the second conductive layer to the first conductive layer of the logic chip via the bonding wire.
11. The system in package device of claim 10, wherein the external signal terminal is connected to the second conductive layer via a conductive line implemented in the substrate.
12. The system in package device of claim 11, wherein the second conductive layer is one of a plurality of second conductive layers arranged along an edge of the second face side of the package substrate.
13. The system in package device of claim 12, wherein the first conductive layer of the logic chip is one of a plurality of first conductive layers arranged along an edge of the interface chip, wherein each of the second conductive layers is connected to a corresponding one of the plurality of first conductive layers of the logic chip.
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