Systems and methods for hard disk drive data storage including reduced latency loop recovery

[0001] The present inventions are related to systems and methods for storing information, and more particularly to systems and methods for reducing loop recovery latency in a storage device.

[0002] A typical data processing system receives an analog input signal that is amplified using a variable gain amplifier. The amplified signal is converted to a digital signal and processed using one of a variety of digital processing techniques. Feedback from the digital processing is provided back to a summation element to adjust the low frequency offset. As bit periods have decreased, faster and faster data processing has been developed. Because of this, the feedback latency has grown in terms of the number of bit periods. This latency negatively effects loop stability.

[0003] Turning to FIG. 1, a data detection system 100 including a prior art low frequency offset feedback loop is shown. Data detection system 100 includes a variable gain amplifier 110 that receives an analog input signal 105, and provides an amplified output 112. Amplified output 112 is provided to a summation element 199 that sums an analog feedback signal 197 with amplified output 112 to provide a sum output 115. Analog feedback signal 197 is a low frequency offset correction that is more fully described below, and sum output 115 is amplified output 112 less the low frequency offset. Sum output 115 is provided to a magneto-resistive asymmetry correction circuit 120 that yields a corrected output 125. Corrected output 125 is filtered using a continuous time filter 130, and a resulting filtered output 135 is provided to an analog to digital converter 140. Analog to digital converter 140 provides a series of digital samples 145 corresponding to filtered output 135. The series of digital samples 145 are provided to a digital filter 150 that provides a digitally filtered output 155. A data detection algorithm is applied by a data detector 160 to digitally filtered output 155 to recover a Y_ideal output 165.

[0004] Y_ideal output 165 is provided to a partial response target filter 180 that conforms Y_ideal to a partial response target and provides a target output 185. Digitally filtered output 155 is provided to a delay circuit 170 that provides a delayed signal 175 that corresponds to digitally filtered output 155 delayed in time sufficient to align it with target output 185. A summation element 192 subtracts target output 185 from delayed signal 175, and provides the result as an error signal 189. Error signal 189 is stored to an offset update register 190. The output of offset update register 190 is converted to analog feedback signal 197 using a digital to analog converter 195. As previously discussed, analog feedback signal 197 is provided to summation element 199 where it is subtracted from amplified output 112.

[0005] There can be a substantial latency between the time that summation element 199 provides sum output 115 and when analog feedback signal 197 corresponding to sum output 115 is available. As this latency grows to several bit periods, it can result in substantial loop instability as analog feedback signal 197 can be applied well after the condition it was intended to correct has resolved itself. Indeed, in some cases, analog feedback signal 197, rather than operating as a negative feedback may operate as a positive feedback accentuate an undesired operational condition.

[0006] Hence, for at least the aforementioned reasons, there exists a need in the art for advanced systems and methods for reduced latency data processing.

[0007] The present inventions are related to systems and methods for storing information, and more particularly to systems and methods for reducing loop recovery latency in a storage device.

[0008] Various embodiments of the present invention provide storage devices that include a storage medium, a read/write head assembly, an analog processing circuit, and a digital processing circuit. The read/write head assembly is operable to access information stored on the storage medium and to transfer the information to an analog processing circuit. The analog processing circuit includes a summation circuit and an analog to digital converter. The summation circuit subtracts a low frequency offset feedback from a derivative of the information to yield a processing output. The analog to digital converter converts a derivative of the processing output to a series of digital samples. The digital processing circuit includes a data detector circuit, an error feedback circuit, an error calculation circuit, and a digital to analog converter. The data detector circuit applies a data detection algorithm to a derivative of the series of digital samples and provides an ideal output. The error feedback circuit includes a conditional subtraction circuit that conditionally subtracts an interim low frequency offset correction signal from a delayed version of the derivative of the series of digital samples to yield an interim factor. The error calculation circuit generates an interim low frequency offset correction signal based at least in part on the interim factor and a derivative of the ideal output. The digital to analog converter converts a derivative of the interim low frequency offset correction signal to yield the low frequency offset feedback.

[0009] In some instances of the aforementioned embodiments, the analog processing circuit further includes a magneto-resistive asymmetry correction circuit and a filter. The magneto-resistive asymmetry correction circuit receives the processing output and provides a corrected output, and the filter receives the corrected output and provides the derivative of the processing output. In various instances of the aforementioned embodiments, the digital processing circuit further includes a digital filter that receives the series of digital samples and provides the derivative of the series of digital samples.

[0010] In some instances of the aforementioned embodiments, the summation circuit is a first summation circuit, and the conditional subtraction circuit includes a delay circuit and a second summation circuit. The delay circuit provides a delayed version of the interim low frequency offset correction signal. The second summation circuit subtracts the delayed version of the interim low frequency offset correction signal from the interim low frequency offset correction signal to yield a compensation factor. In some cases, the aforementioned delay circuit is a first delay circuit, and the conditional subtraction circuit further includes a second delay circuit and a third summation circuit. The second delay circuit receives the derivative of the series of digital samples and provides the delayed version of the derivative of the series of digital samples. The third summation circuit subtracts the compensation factor from the delayed version of the interim low frequency offset correction signal to yield the interim factor.

[0011] In one or more instances of the aforementioned embodiments, the summation circuit is a first summation circuit, and the error calculation circuit includes a second summation circuit that subtracts the derivative of the ideal output from the interim factor to yield the interim low frequency offset correction signal. In particular instances of the aforementioned embodiments, the digital processing circuit further includes a multiplication circuit that multiplies the interim low frequency offset correction signal by a gain factor to yield the derivative of the interim low frequency offset correction signal. In some cases, the gain factor yields a loop gain of unity. In particular instances of the aforementioned embodiments, the error calculation circuit includes a partial response target circuit that receives the ideal output and yields the derivative of the ideal output.

[0012] Other embodiments of the present invention provide data processing circuits. Such data processing circuits include a summation circuit, a data detector circuit, an error feedback circuit, and an error calculation circuit. The summation circuit subtracts a low frequency offset feedback from an input signal to yield a processing output. The data detector circuit applies a data detection algorithm to a derivative of the processing output and provides an ideal output. The error feedback circuit includes a conditional subtraction circuit that conditionally subtracts an interim low frequency offset correction signal from a delayed version of the derivative of the processing output to yield an interim factor. The error calculation circuit generates an interim low frequency offset correction signal based at least in part on the interim factor and a derivative of the ideal output. In such embodiments, the low frequency offset feedback is derived from the interim low frequency offset correction signal.

[0013] Yet other embodiments of the present invention provide methods for reduced latency data processing. Such methods include providing a summation circuit; subtracting a low frequency offset feedback from an input signal to yield a processing output; applying a data detection algorithm to a derivative of the processing output to yield an ideal output; perform a conditional subtraction where an interim low frequency offset correction signal is subtracted from the derivative of the processing output to yield an interim factor during a limited period after the interim low frequency offset correction signal becomes available; and subtracting a derivative of the ideal output from the interim factor to yield the interim low frequency offset correction signal. The low frequency offset feedback is a derivative of the interim low frequency offset correction signal. In some instances of the aforementioned embodiments, the derivative of the processing output is a first derivative of the processing output, and the methods further include multiplying the interim low frequency offset correction signal by a gain factor to yield the derivative of the interim low frequency offset correction signal; performing an analog to digital conversion of a second derivative of the processing output to yield the first derivative of the processing output; and performing a digital to analog conversion of the derivative of the interim low frequency offset correction signal to yield the low frequency offset feedback.

[0014] This summary provides only a general outline of some embodiments of the invention. Many other objects, features, advantages and other embodiments of the invention will become more fully apparent from the following detailed description, the appended claims and the accompanying drawings.

[0020] The present inventions are related to systems and methods for storing information, and more particularly to systems and methods for reducing loop recovery latency in a storage device.

[0021] Proper function of low frequency correction feedback loops is important to ensuring reasonable performance in read channel devices. Undesired low frequency errors may derive from an input signal and/or later analog processing circuitry used in processing the input signals. Various embodiments of the present invention provide low frequency offset correction circuits offering reduced latency when compared with existing offset correction circuits. Such embodiments rely on a summation element in the error computation path that allows for early utilization of a preliminary correction feedback signal, and for canceling out the preliminary correction feedback signal once the correction feedback signal has propagated through the loop. By preliminary utilization of the correction feedback signal, an undesirable low frequency offset may be corrected in a data processing system without requiring the latency of existing loops.

[0022] Turning to FIG. 2, a data detection system 200 including a reduced latency low frequency offset correction loop circuit is shown in accordance with various embodiments of the present invention. Data detection circuit 200 includes a variable gain amplifier 210 that receives an analog input signal 205, and provides a variably amplified output 212. Variable gain amplifier 210 may be any amplifier known in the art that is capable of providing a variably amplified output, with the amount of amplification being based upon a feedback signal (not shown). Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of variable gain amplifiers that may be used in relation to different embodiments of the present invention. Analog input signal 205 may be derived from a variety of sources. For example, where data detection system 200 is used to process data receives from a storage medium, analog input signal 205 may be derived from a read/write head assembly (not shown) that is disposed in relation to the magnetic storage medium (not shown). Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of sources for analog input signal 205.

[0023] Variably amplified output 212 is provided to a summation element that subtracts an analog feedback signal 297 from variably amplified output 212 to yield a processing output 215. As further disclosed below, analog feedback signal 297 corresponds to a low frequency offset correction value. Thus, processing output 215 represents variably amplified output 212 with the low frequency offset subtracted from it. Processing output 215 provided to a magneto-resistive asymmetry correction circuit 220 that yields a corrected output 225. Magneto-resistive asymmetry correction circuit 220 may be any correction circuit known in the art that is capable of mitigating the effects of MR asymmetry. Corrected output 225 is filtered using a continuous time filter 230. In some cases, continuous time filter 230 is an RC filter circuit as is known in the art that is tuned to operate as a band pass filter, a high pass filter, or a low pass filter. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of filters that may be used as continuous time filter 230. It should also be noted that other analog processing circuits may be included with continuous time filter 230 depending upon the particular operation of the circuit. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of analog processing circuitry that may be incorporated in data detection system 200.

[0024] A filtered output 235 is provided from continuous time filter 230 to an analog to digital converter 240. Analog to digital converter 240 may be any circuit known in the art that is capable of converting an analog input signal to a series of digital samples corresponding thereto. Analog to digital converter 240 samples filtered output 235 and provides a series of digital samples 245 corresponding to the magnitude of filtered output 235 at respective sampling points. Digital samples 245 are provided to a digital filter 250. Digital filter 250 provides a digitally filtered output 255. In some embodiments of the present invention, digital filter 250 is a digital finite impulse response filter as are known in the art. In one particular embodiment of the present invention, digital filter 250 is a ten tap digital finite impulse response filter.

[0025] Digitally filtered output 255 is provided to a data detector circuit 260. Data detector circuit 260 may be any detector/decoder known in the art. For example, data detector circuit 260 may incorporate a low density parity check decoder. As another example, data detector circuit 260 may incorporate a Viterbi algorithm decoder. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize various detector circuits that may be used in relation to different embodiments of the present invention. Using digitally filtered output 255, data detector circuit 260 generates a Y_ideal output 265. Y_ideal output 265 represents signal input 205 with various error corrections applied by the data detection process. Y_ideal output 265 is made available for downstream processing.

[0026] In addition, Y_ideal output 265 is provided to a partial response target circuit 280 that conforms the output to a known target. Partial response target circuit 280 may be any target filter known in the art. In some embodiments of the present invention, partial response target circuit is a digital finite impulse response filter as are known in the art. In one particular embodiment of the present invention, partial response target circuit 280 is a three tap digital finite impulse response filter.

[0027] Partial response target circuit 280 provides a target output 285 to a summation element 292. Summation element 292 subtracts target output 285 from an adjusted output 279, and the result is provided as an error signal 289 that is stored to a offset update register 290. As discussed below, adjusted output 279 is derived from digitally filtered output 255. A preliminary low frequency offset correction output 291 is provided from offset update register 290. Preliminary low frequency offset correction output 291 is multiplied by a gain factor 288 using a multiplier circuit 293 yielding a low frequency offset correction output 294. Low frequency offset correction output 294 is converted to analog feedback signal 297 using a digital to analog converter 295. As mentioned above, analog feedback signal 297 is subtracted from variably amplified output 212 using summation element 299 to yield processing output 215.

[0028] The latency between the time that summation element 299 provides processing output 215 and when analog feedback signal 297 corresponding to variably amplified output 212 is available is reduced by applying an interim correction. The interim correction is achieved by feeding preliminary low frequency offset correction output 291 into the calculation of error signal 289 without waiting for the low frequency offset adjustment to propagate back through the loop via summation element 299. As an overview, the interim correction effectively subtracts preliminary low frequency offset correction output 291 from digitally filtered output 255 before comparison with target output 285 to yield error signal 289. As such, any low frequency offset correction corresponding to error signal 289 is quickly available for calculating a new value of error signal 289. This results in a reduction in latency between the availability of processing output 215 and the application of signals derived there from to error signal 289 (and thus preliminary low frequency offset correction output 291). As just some advantages, such a reduction in latency increases loop stability and allows for decreased bit periods along with correspondingly higher bandwidth through data detection system 200.

[0029] In particular, preliminary low frequency offset correction output 291 is provided to a delay circuit 213. A delayed output 217 from delay circuit 213 is provided to a summation element 210 where it is subtracted from preliminary low frequency offset correction output 291 to yield output 211. Delay circuit 213 applies a delay to preliminary low frequency offset correction output 291 that accounts for the time that it takes for preliminary low frequency offset correction output 291 to be reflected in error signal 289 via the path through summation element 299 (i.e., preliminary low frequency offset correction output 291 to digital to analog converter 295, magneto-resistive asymmetry correction circuit 220, continuous time filter 230, analog to digital converter 240, digital filter 250, data detector 260, partial response target circuit 280 and summation element 292). This loop is referred to herein as the slave loop. Delayed output 217 is provided to summation element 210 that subtracts a delayed version of preliminary low frequency offset correction output 291 from a current version of preliminary low frequency offset correction output 291 to yield a summation output 211. Summation output 211 is provided to a summation element 277 where it is subtracted from a delayed output 275 of digitally filtered output 255 provided by delay circuit 270. The result from summation element 277 is provided as an adjusted output 279. The loop from error signal 289 through offset update register 290, delay circuit 213, summation element 210, summation element 277 and summation element 292 is referred to herein as a master loop.

[0030] Summation output 211 initially reflects the value of preliminary low frequency offset correction output 291, but after the expiration of the delay period imposed by delay circuit 213, summation output 211 is zero as preliminary low frequency offset correction output 291 is subtracted out by summation element 210. The following pseudo-code describes the value of summation output 211:

[0031]

	If (t < T+delay period of Delay Circuit 213){
	Summation Output 211 = Preliminary Low Frequency Offset
	Correction Output 291
	}
	Else If (t >= T+delay period of Delay Circuit 213){
	Summation Output 211 = 0
	}

In this way, any offset reflected by preliminary low frequency offset correction output 291 can be applied very quickly to the generation of error signal 289 as part of the master loop, but the offset reflected by preliminary low frequency offset correction output 291 that is applied to the slower slave loop can be cancelled when it is applied to error signal 289. This prevents double counting of preliminary low frequency offset correction output 291, while at the same time allowing for an interim use of preliminary low frequency offset correction output 291. In effect, preliminary low frequency offset correction output 291 is accelerated into error signal 289 via the master loop for the initial period where low frequency offset correction is still propagating through the slave loop, and then the actual affect of preliminary low frequency offset correction output 291 on summation element 299 is applied after it is propagated through the slave loop.

[0032] Digitally filtered output 255 is provided to a delay circuit 270 that provides a delayed filtered output signal 275. The period of delay imposed by delay circuit 270 corresponds to the time required for a signal to propagate through data detector 260 and partial response target circuit 280, less the amount of time required to propagate through summation element 277. By imposing this delay, adjusted output 279 is aligned in time with target output 285 (i.e., a corresponding digitally filtered output 255 is used to create both target output 285 and adjusted output 279.

[0033] Turning to FIG. 3, a flow diagram 300 shows a method for reducing low frequency offset correction latency in a data detection system in accordance with one or more embodiments of the present invention. Following flow diagram 300, a data input is received (block 305). This data input may be, for example, an analog input signal derived from a magnetic storage medium. A variable gain amplification is performed on the data input (block 310). In some cases, the variable amplification is done using an analog variable gain amplifier. The variable gain amplification provides a variably amplified output. A low frequency offset is subtracted from the variably amplified output (block 312), and analog processing is applied to the resulting processed output (block 315). This analog processing may include, but is not limited to, a continuous time filtering process and/or magneto-resistive asymmetry correction as is known in the art. The analog processed output is then converted to one or more digital samples through an analog to digital conversion process (block 320).

[0034] The resulting digital samples are digitally filtered to yield a Y output (block 325). In some cases, the digital filtering is done using a digital finite impulse response filter as are known in the art. A data detection process is performed on the Y output to generate a Y_ideal output (block 330). The data detection process may be performed using any data detector/decoder known in the art. In addition, a partial response filtering is applied to the Y_ideal output to yield a target output (block 335). In some cases, the partial response filtering is done using a digital finite impulse response filter where the taps of the filter are coupled to a target set as is known in the art.

[0035] The Y output is delayed in time to align it with the target output (block 340). Once the Y output aligns with the target output (or will align after a multiplication process) (block 340), it is determined whether the current low frequency offset correction output has propagated through the generation of a feedback error signal (block 345). Where the current low frequency offset correction output has not yet propagated back through to the generation of the feedback error signal (block 345), the low frequency offset correction output is subtracted from the Y output to yield a Y feedback value (block 350). Otherwise, where the current low frequency offset correction output has propagated back through to the generation of the feedback error signal (block 345), the Y output is passed through as the Y feedback signal (block 355). In both cases, the target output (from block 335) is subtracted from the Y feedback signal to update the low frequency offset correction output (block 360). This low frequency offset correction output (block 365) is multiplied by a gain factor and the product is converted to an analog low frequency offset signal (block 370). This analog low frequency offset signal is used in the subtraction of block 312. The gain factor is selected such that the loop gain for the low frequency correction loop is unity.

[0036] Turning to FIG. 4, a storage system 400 including a read channel 410 with low latency loop recovery is shown in accordance with various embodiments of the present invention. Storage system 400 may be, for example, a hard disk drive. The low latency loop recovery includes a data detector that may be any data detector known in the art including, for example, a Viterbi algorithm data detector. Storage system 400 also includes a preamplifier 470, an interface controller 420, a hard disk controller 466, a motor controller 468, a spindle motor 472, a disk platter 478, and a read/write head 476. Interface controller 420 controls addressing and timing of data to/from disk platter 478. The data on disk platter 478 consists of groups of magnetic signals that may be detected by read/write head assembly 476 when the assembly is properly positioned over disk platter 478. In one embodiment, disk platter 478 includes magnetic signals recorded in accordance with either a longitudinal or a perpendicular recording scheme.

[0037] In a typical read operation, read/write head assembly 476 is accurately positioned by motor controller 468 over a desired data track on disk platter 478. Motor controller 468 both positions read/write head assembly 476 in relation to disk platter 478 and drives spindle motor 472 by moving read/write head assembly to the proper data track on disk platter 478 under the direction of hard disk controller 466. Spindle motor 472 spins disk platter 478 at a determined spin rate (RPMs). Once read/write head assembly 478 is positioned adjacent the proper data track, magnetic signals representing data on disk platter 478 are sensed by read/write head assembly 476 as disk platter 478 is rotated by spindle motor 472. The sensed magnetic signals are provided as a continuous, minute analog signal representative of the magnetic data on disk platter 478. This minute analog signal is transferred from read/write head assembly 476 to read channel module 464 via preamplifier 470. Preamplifier 470 is operable to amplify the minute analog signals accessed from disk platter 478. In turn, read channel module 410 decodes and digitizes the received analog signal to recreate the information originally written to disk platter 478. This data is provided as read data 403 to a receiving circuit. As part of decoding the received information, read channel 410 performs a variable gain amplification based on a gain adjustment feedback circuit. The gain adjustment feedback circuit includes both a master loop and a slave loop. In some cases, read channel 410 includes circuitry similar to that discussed above in relation to FIG. 2. In some cases, gain adjustment process is performed in accordance with that discussed above in relation to FIG. 3. A write operation is substantially the opposite of the preceding read operation with write data 401 being provided to read channel module 410. This data is then encoded and written to disk platter 478.

[0038] In conclusion, the invention provides novel systems, devices, methods and arrangements for performing data processing. While detailed descriptions of one or more embodiments of the invention have been given above, various alternatives, modifications, and equivalents will be apparent to those skilled in the art without varying from the spirit of the invention. Therefore, the above description should not be taken as limiting the scope of the invention, which is defined by the appended claims.