Method for fabricating semiconductor device

[0001] The present application claims priority of Korean Patent Application No. 10-2009-0117435, filed on Nov. 30, 2009, which is incorporated herein by reference in its entirety.

[0002] Exemplary embodiments of the present invention relate to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a semiconductor device having a buried bit line connected to a one-sidewall contact.

[0003] There is a limit to improving an integration degree of a conventional MOSFET element because a leakage current, an on-current, and a short channel effect may result as the element is ultra-miniaturized. To address such a limit, a planar channel has been replaced with a vertical channel protruding in a perpendicular direction from a substrate.

[0004] Hereafter, the structure of a conventional vertical-channel semiconductor device and concerns thereof are described in detail with reference to FIGS. 1A and 1B.

[0005] FIGS. 1A and 1B are diagrams illustrating the structure of the conventional vertical-channel semiconductor device. FIG. 1A is a perspective view of the semiconductor device, and FIG. 1B is a plan view of the semiconductor device.

[0006] Referring to FIGS. 1A and 1B, the conventional vertical-channel semiconductor device includes a plurality of pillars 11 protruding from a substrate 10, a plurality of parallel buried bit lines BBL extended along a first direction I-I′, and a plurality of parallel word lines WL extended along to a second direction II-II′ crossing over the first direction I-I′.

[0007] Specifically, a plurality of pillar structures, including a first hard mask layer 14 and the pillars 11, extend in a vertical direction from the substrate 10. Each of the pillars 11 is surrounded by a gate electrode 13, and a gate dielectric layer 12 is interposed between the pillar 11 and the gate electrode 13 as shown FIG. 1B.

[0008] The buried bit lines BBL are formed by implanting impurity ions into the substrate 10, and a trench T is formed between the neighboring buried bit lines BBL. Although not illustrated in FIG. 1A, an insulation layer for separating the neighboring buried bit lines from each other is filled in the trench T.

[0009] Each of the word lines WL connects the gate electrodes 13 of the pillars 11 arranged in the second direction II-II′, and is extended to cross over the corresponding buried bit line BBL.

[0010] In accordance with the conventional vertical-channel semiconductor device, since the buried bit lines BBL are formed by implanting dopants into the substrate 10 through an ion implantation process, there is a limit in reducing the resistance of the buried bit lines BBL.

[0011] Furthermore, while the word lines WL are formed after the gate electrodes 13 are formed, the sheet resistance of the word lines WL may be increased by resistance components of the gate electrodes 13.

[0012] Furthermore, when the hard mask layer 14 and the substrate 10 are etched to form the pillar structures, the pillar structures may be inclined or collapse in the fabricating process of the semiconductor device, because the pillar structures have a large aspect ratio.

[0013] Exemplary embodiments of the present invention are directed to a method for fabricating a semiconductor device, which is capable of reducing the resistance of buried bit lines thereof.

[0014] Exemplary embodiments of the present invention are also directed to a method for fabricating a semiconductor device, which is capable of preventing pillars from becoming inclined or collapsing.

[0015] In accordance with an exemplary embodiment of the present invention, a method for fabricating a semiconductor device includes forming a plurality of first trenches by etching a substrate, forming a plurality of buried bit lines in the first trenches, forming a plurality of second trenches to expose at least one sidewall of the buried bit lines by etching the substrate, and forming a plurality of one-sidewall contact plugs which fill the second trenches.

[0016] In accordance with another exemplary embodiment of the present invention, a method for fabricating a semiconductor device includes forming a plurality of first line-type trenches by etching a substrate, forming a plurality of bit lines buried in the first trenches, forming a plurality of second line-type trenches to expose one sidewall of the bit lines by etching the substrate, forming a plurality of one-sidewall contact plugs which fill the second trenches, forming an inter-layer dielectric layer over the entire resultant structure having the one-sidewall contact plugs formed therein, forming a plurality of third trenches by selectively etching the inter-layer dielectric layer to expose a surface of the substrate in a region distinct from regions where the buried bit lines and the one-sidewall contact plugs are formed, and forming a plurality of pillars buried in the third trenches.

[0020] Exemplary embodiments of the present invention will be described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Throughout the disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present invention.

[0021] The drawings are not necessarily to scale and in some instances, proportions may have been exaggerated in order to clearly illustrate features of the embodiments. When a first layer is referred to as being “on” a second layer or “on” a substrate, it not only refers to a case where the first layer is formed directly on the second layer or the substrate, but also a case where a third layer exists between the first layer and the second layer or the substrate.

[0022] FIGS. 2A to 2G are perspective views explaining a method for fabricating a vertical-channel semiconductor device in accordance with an exemplary embodiment of the present invention.

[0023] Referring to FIG. 2A, a pad layer 21 and a first hard mask layer 22 are formed on a substrate 20. The pad layer 21 may include an oxide layer, and the first hard mask layer 22 may include a nitride layer. Furthermore, the pad layer 21 may have a thickness ranging from approximately 50 Å to approximately 100 Å, and the first hard mask layer 22 may have a thickness ranging from approximately 50 Å to approximately 300 Å.

[0024] A plurality of mask patterns 23 for buried bit lines are formed on the first hard mask layer 22. The mask patterns 23 may be photoresist patterns. Furthermore, the mask patterns 23 may be line-type patterns extended in parallel along a first direction I-I′.

[0025] Using the mask patterns 23 as an etching barrier, the first hard mask layer 22 and the pad layer 21 are etched, and the substrate 20 is then etched to a certain depth to form a plurality of trenches T1 for the buried bit lines. The etching depth of the trenches T1, that is, the etching depth of the substrate 20 may range from approximately 500 Å to approximately 1,000 Å.

[0026] A wall oxidation process is performed to form a sidewall oxide layer 24 on inner walls and bottom surfaces of the exposed trenches T1. The sidewall oxide layer 24 may have a thickness ranging from approximately 30 Å to approximately 70 Å.

[0027] Referring to FIG. 2B, the mask patterns 23 are removed, and a conductive layer is formed on the entire resultant structure having the sidewall oxide layer 24 formed therein. The conductive layer may be deposited to a thickness ranging from approximately 1,000 Å to approximately 1,400 Å. A planarization process is performed until the surface of the first hard mask layer 22 is exposed.

[0028] Accordingly, a plurality of buried bit lines 25 are formed in the trenches T1. The buried bit lines 25 may include a tungsten silicide layer. When the buried bit lines 25 are formed of a tungsten silicide WSi_x, the buried bit lines 25 are prevented from being oxidized even during a subsequent high-temperature annealing process and a subsequent oxidization process, because the tungsten silicide has a high thermal stability.

[0029] Because of the manner in which the buried bit lines 25, including a metallic material, are formed, the resistance of the buried bit lines 25 can be reduced.

[0030] Referring to FIG. 2C, a second hard mask layer 26 is formed on the resultant structure where the buried bit lines 25 are formed. The second hard mask layer 26 may include a nitride layer and have a thickness ranging from approximately 50 Å to approximately 200 Å.

[0031] A plurality of line-type mask patterns 27 for subsequently forming one-sidewall contact plugs are formed on the second hard mask layer 26 so as to be extended in parallel along the first direction. Herein, line-type patterns are characterized as parallel structures in the same plane and separated by a space for exposing a surface beneath the plane. The mask patterns 27 may be photoresist patterns.

[0032] The mask patterns 27 are used for forming a plurality of one-sidewall contact plugs which may electrically connect one sidewall of pillars, formed by a subsequent process, to the buried bit lines 25. Each of the mask patterns 27 may be formed in such a shape as to expose portions of the second hard mask layer 26 along a line (e.g., a line in the I-I′ direction in FIG. 2C) aligned with one sidewall of the buried bit line 25, while covering the corresponding buried bit line 25.

[0033] Furthermore, each of the mask patterns 27 may be formed in such a manner that the space between the mask patterns 27 may have a certain width, which extends over the buried bit line 25 by a certain width and over the subsequently formed insulation layer by a certain width. In this case, the one-sidewall contact plug and the buried bit line 25 may overlap each other by a certain width.

[0034] Using the mask patterns 27 as an etching barrier, the second hard mask layer 26, the first hard mask layer 22, and the pad layer 21 are etched, and the substrate 20 and the sidewall oxide layer 24 are etched. At this time, the buried bit lines 25 may be partially etched together during the etching of the substrate 20 and the sidewall oxide layer 24. Accordingly, a plurality of trenches T2 for one-side contact plugs are formed to expose one sidewall of the buried bit lines 25.

[0035] In FIG. 2C, the substrate having the trenches T2 formed therein is represented by reference numeral 20A, and the first hard mask layer 22, the pad layer 21, and the sidewall oxide layer 24 etched during the forming of the trenches T2 are represented by reference numerals 22A, 21A, and 24A, respectively.

[0036] The width W1 of the trenches T2 for the one-sidewall contact plugs may range from approximately 5% to approximately 15% of the depth D1 of the trenches T1 for the buried bit lines 25. The depth D2 of the trenches T2 may range from approximately 70% to approximately 90% of the depth D1 of the trenches T1. For example, when the depth of the trenches T1 ranges from approximately 500 Å to approximately 1,000 Å, the width of the trenches T2 may range from approximately 25 Å to approximately 150 Å.

[0037] Referring to FIG. 2D, the mask patterns 27 are removed, and a conductive layer for one-sidewall contact plugs 28 is formed on the entire resultant structure wherein the trenches T2 are formed. The one-sidewall contact plugs 28 may include a doped polysilicon layer or a metallic layer. In particular, the one-sidewall contacts 28 may be formed of a metal material having a high thermal stability. Furthermore, the one-sidewall contacts 28 may be formed of a is material having a high etching selectivity with respect to the buried bit lines 25.

[0038] An etch back process is performed in such a manner that the conductive layer remains with a certain thickness in the trenches T2. In this case, a blanket etch back process may be performed. Accordingly, the one-sidewall contact plugs 28 are formed so as to partially fill the trenches T2. As such, when the one-sidewall contact plugs 28 are formed after the buried bit lines 25 are formed, damage to the one-sidewall contact plugs 28 caused during the fabricating process of the semiconductor device may be reduced/minimized.

[0039] The etch back process may be performed until the conductive layer within the trenches T2 has a remaining volume ranging from approximately 20% to approximately 60% of that of the trenches T2. For example, when the trenches T2 have a width ranging from approximately 50 Å to approximately 100 Å, the etch back process may be performed until the conductive layer with a thickness ranging from approximately 200 Å to approximately 400 Å remains.

[0040] Furthermore, the etch back process may be performed under such a condition that the etching selectivity of the conductive layers for the one-sidewall contact plugs with respect to the buried bit lines is high.

[0041] An insulation layer 29 is formed on the one-sidewall contact plugs 28 within the trenches T2. The insulation layer 29 is provided to insulate the buried bit lines 25 from the substrate 20A which is to become a drain region, and may be formed by the wall oxidation process. For example, when the buried bit lines 25 including the tungsten silicide are formed, the insulation layer 29 including a silicon oxide SiO₂ may be formed by the wall oxidation process.

[0042] The insulation layer 29 may have a thickness ranging from approximately 50 Å to approximately 100 Å.

[0043] Referring to FIG. 2E, an inter-layer dielectric layer 30 is formed on the entire resultant structure wherein the insulation layer 29 is formed. The inter-layer dielectric layer 30 may include a tetraethyl orthosilicate (TEOS) layer, a high density plasma (HDP) oxide layer, or a spin-on dielectric (SOD) layer which is formed by a chemical vapor deposition (CVD) process, and may have a thickness ranging from approximately 1,000 Å to approximately 2,000 Å.

[0044] A mask pattern 31 for subsequently forming pillars is formed on the inter-layer dielectric layer 30.

[0045] The mask pattern 31 may be a photoresist pattern. Furthermore, the mask pattern 31 may be formed to have a plurality of openings arranged in the first and second directions I-P and while covering the regions where the buried bit lines 25 and the one-sidewall contact plugs 28 are formed.

[0046] Using the mask pattern 31 as an etching barrier, the inter-layer dielectric layer 30, the second hard mask layer 26, the first hard mask layer 22A, and the pad layer 21A are etched to form a plurality of trenches T3 which expose the surface of the substrate 20A.

[0047] At this time, the trenches T3 for subsequently forming pillars are desired to be arranged in such a manner that the buried bit lines 25 and the one-sidewall contact plugs 28 are not exposed.

[0048] In FIG. 2E, the second hard mask layer 26, the first hard mask layer 22A, the pad layer 21A etched during the forming of the trenches T3 are represented by reference numerals 26A, 22B, and 21B, respectively.

[0049] Referring to FIG. 2F, the mask pattern 31 is removed, and a plurality of pillars 32 are formed in the trenches T3. At this time, the pillars 32 may be formed by a silicon epitaxial growth (SEG) process.

[0050] When the pillars 32 are formed by the SEG process, a native oxide layer on the surface of the substrate 20A exposed at the bottom of the trenches T3 is removed. The native oxide layer is omitted in FIG. 2F. The removal of the native oxide layer may be performed by a baking process using H₂ gas and a HF vapor process. For example, after the baking process using H₂ gas is performed at a temperature ranging from approximately 700° C. to approximately 1,200° C. for 10 seconds or more, the HF vapor process may be performed for 25 seconds or less.

[0051] In the SEG process, a mixed gas of SiH₂Cl₂ (dichloro silane) gas, HCl gas, and H₂ gas or a mixed gas of Si₂H₆ gas and Cl₂ gas may be used as source gas. The SEG process may be performed at a temperature ranging from approximately 700° C. to 1,200° C. Furthermore, a base pressure may be a low pressure ranging from 10⁻⁶ Torr to 10⁻⁸ Torr, and a process pressure may be 10⁻⁵ Torr or less.

[0052] A planarization process is performed on the resultant structure where the silicon is deposited by the SEG process until the surface of the inter-layer dielectric layer 30 is exposed. Accordingly, the plurality of pillars 32 arranged in the first and second directions I-I′and II-II′ may be formed.

[0053] Because the pillars 32 are formed after the buried bit lines 25 and the one-sidewall contact plugs 28 are formed, the pillars 32 may be not become inclined or collapse during the fabricating process of the semiconductor device.

[0054] The inter-layer dielectric layer 30 buried between the plurality of pillars 32 is removed to expose the pillars 32. For example, a dry etching process may be performed in such a manner that the inter-layer dielectric layer 30 with a thickness ranging from approximately 30 Å to approximately 70 Å remains on the second hard mask layer 26A, and a wet etching dip process may be performed to remove the inter-layer dielectric layer 30 remaining on the second hard disk layer 26A. In this case, while the inter-layer dielectric layer 30 buried between the plurality of pillars 32 is removed, the inter-layer dielectric layer 30A buried in the trenches T2 within the second hard mask layer 26A may remain. Thus, the remaining portions of the second hard mask layer 26A can prevent the buried bit lines 25 from being exposed as a result of the removal of the inter-layer dielectric layer 30.

[0055] Referring to FIG. 2G, a gate dielectric layer 33 is formed on the entire surface of the resultant structure having the exposed pillars 32. The formation of the gate dielectric layer 33 may be performed by a radical oxidation process. When the radical oxidation process is performed, the surface of the etched second hard mask layer 26A is oxidized. Therefore, the gate dielectric layer 33 is formed on the entire surface of the resultant structure.

[0056] A conductive layer is formed on the entire resultant structure wherein the gate dielectric layer 33 is formed. A planarization process is performed, and the conductive layer is etched by using a plurality of word-line mask patterns as an etching barrier. The word-line mask patterns are omitted in FIG. 2G. However, FIG. 2G shows a plurality of word lines 34 formed by the etch using the word-line mask patterns. More specifically, the word lines 34 may be parallel to each other and may extend in the second direction II-II′.

[0057] Although not illustrated in FIG. 2G, an inter-layer dielectric layer may be buried in a gap region between the adjacent word lines 34, and processes for forming storage node contact plugs, capacitors, and metal interconnections may be sequentially performed.

[0058] FIGS. 3A to 3C are perspective views explaining a method for fabricating a semiconductor device in accordance with another exemplary embodiment of the present invention. In the following exemplary embodiment of the present invention, the descriptions are focused on the pillar formation process, and other processes overlapping the processes in accordance with the above-discussed exemplary embodiment of the present invention are omitted.

[0059] Referring to FIG. 3A, a resultant structure wherein buried bit lines 45 and one-sidewall contact plugs 48 are formed is provided. Processes for forming the buried bit lines 45 and the one-sidewall contact plugs 48 may be performed in the same manner as those in the above-discussed embodiment of the present invention. Reference numerals 40, 41, 42, 44, 46, and 49 represent a substrate, a pad layer, a first hard mask layer, a sidewall oxidation layer, a second hard mask layer, and an insulation layer, respectively.

[0060] An inter-layer dielectric layer 50 is formed on the entire resultant structure having the buried bit lines 45 and the one-sidewall contacts 48, and a plurality of first mask patterns 51 are formed.

[0061] The plurality of first mask patterns 51 may be line-type patterns, which extend in the first direction and are parallel to each other, while covering the regions where the buried bit lines 45 and the one-sidewall contact plugs 48 are formed.

[0062] Using the first mask patterns 51 as an etching barrier, the inter-layer dielectric layer 50, the second hard mask layer 46, the first hard mask layer 42, and the pad layer 41 are etched to form a plurality of line-type trenches T4 exposing the surface of the substrate 40. At this time, the line-type trenches T4 are to be arranged in such a manner that the buried bit lines 45 or the one-sidewall contact plugs 48 are not exposed during the etching process for forming the line-type trenches T4.

[0063] Referring to FIG. 3B, the first mask patterns 51 are removed, and a plurality of active regions 52 are formed in the line-type trenches T4 by the SEG process. For example, as shown in FIG. 3B, The plurality of active regions 52 may extend in the first direction I-I′ and may be parallel to each other.

[0064] A plurality of line-type second mask patterns 53 are formed on the resultant structure wherein the active regions 52 are formed. The plurality of second mask patterns 53 may, for example, extend in the second direction II-II′ and may be parallel to each other, while covering pillar formation regions. The pillar formation regions are island-type regions where pillars are to be formed by a subsequent process and which are arranged at certain intervals in the first and second directions I-I′ and II-II′.

[0065] Referring to FIG. 3C, the active regions 52 and the inter-layer dielectric layer 50 are etched using the second mask patterns 53 as an etching barrier, and the inter-layer dielectric layer 50 under the second mask patterns 53 is further removed through the above-discussed dry etching and wet etching dip processes in order to form a plurality of pillars 52A arranged in the first and second directions and II-II′.

[0066] The etching process of the active regions 52 and the inter-layer dielectric layer 50 using the second mask patterns 53 may be performed under such a condition that the etching selectivity of the active regions 52 with respect to the inter-layer dielectric layer 50 is low. In particular, the etching process may be performed under a non-selectivity condition.

[0067] In FIG. 3C, the inter-layer dielectric layer, which remains in the trenches within the second hard mask layer 46A after the etching process of the active regions 52, is represented by a reference numeral 50A.

[0068] Although not illustrated in FIG. 3C, a gate dielectric layer is formed on the entire surface of the resultant structure wherein the pillars 52A are formed, and a word-line conductive layer is formed on the gate dielectric layer. The word-line conductive layer is patterned to form a plurality of word lines, which extend in the second direction II-II′ and are parallel to each other.

[0069] In accordance with the exemplary embodiments of the present invention, because of the manner in which the buried bit lines, including a metallic material, are formed, the resistance of the buried bit lines can be reduced. Furthermore, since the one-sidewall contact plugs are formed after the buried bit lines are formed, the one-sidewall contacts can be prevented from being damaged during the fabricating process.

[0070] Furthermore, since the pillars are formed after the buried bit lines and the one-sidewall contact plugs are formed, the pillars may be prevented from becoming inclined or collapsing while the buried bit lines and the one-sidewall contact plugs are formed.

[0071] While the present invention has been described with respect to the specific exemplary embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.