Failure diagnostic apparatus, failure diagnostic system, and failure diagnostic method

[0001] This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2007-093853 filed on Mar. 30, 2007, the entire contents of which are incorporated herein by reference.

[0002] 1. Field of the Invention

[0003] The application relates to failure diagnosis for estimating the location of failure that occurs in a semiconductor integrated circuit device.

[0004] 2. Description of the Related Art

[0005] In recent years, as a manufacturing test of a semiconductor integrated circuit device, a BIST method has been used more frequently than a SCAN test method. Use of a BIST method makes failure diagnosis for estimating the location of failure more difficult than the case where a SCAN test method is used. In failure diagnosis of a semiconductor integrated circuit device using a BIST method, there are some case that the BIST method cannot be employed according to the state of operation of the circuit. Therefore, there is a need to estimate the location of failure independent of the state of operation of the circuit.

[0006] A method that meets the above need is described, for example, in “Computer Independent Direct Diagnosis”, Wu-Tung Cheng et al., IEEE Computer Society, 2004, pp. 204-209.

[0007] According to an aspect of the present invention, there is provided a failure diagnostic apparatus that diagnoses a semiconductor integrated circuit device for failure based on a compressed signal obtained by compressing a plurality of signals outputted from a plurality of scan chains in which a plurality of scan flip-flops, to which signals from the semiconductor integrated circuit device are inputted, are connected in series. For each stage of the scan chains, the failure diagnostic apparatus sets a virtual space compression circuit that compresses output signals of the scan flip-flops in the stage and a virtual pin connected to the output terminal of the virtual space compression circuit, and the output signal of the virtual pin is compared with the compression signal to diagnose the semiconductor integrated circuit device for failure.

[0008] The above-described embodiments of the present invention are intended as examples, and all embodiments of the present invention are not limited to including the features described above.

[0022] Reference may now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout.

[0023] FIG. 1A shows a semiconductor integrated circuit device. The semiconductor integrated circuit device 10 employs a SCAN test method as a manufacturing test of a random logic circuit. As shown in FIG. 1A, a random logic circuit 11 of the semiconductor integrated circuit device 10 is coupled to input terminals D of scan-type flip-flop circuits (hereinafter referred to as SFFs) 12a, 12b, 13a, 13b, 14a and 14b that form scan chains 12, 13 and 14. Signals are inputted to scan-in terminals SI of the SFFs 12a, 13a and 14a. Output terminals Q of the SFFs 12a, 13a and 14a are coupled to the scan-in terminals SI of the SFFs 12b, 13b and 14b in the next stage. The output terminals Q of the SFFs 12b, 13b and 14b are coupled to test output terminals SD0 to SD2, respectively.

[0024] In the SCAN test method, output signals of the random logic circuit 11 are held in the SFFs 12a to 14b. The signals held in the SFFs 12a to 14b are sequentially outputted based on a clock signal. That is, in the scan chain 12 including the SFFs 12a and 12b, the signals held in the SFF 12b and the SFF 12a are sequentially outputted to the test output terminal SD0. Let t be the cycle in which such a signal is outputted. The signal SD0(t) (t=0, 1) at the output terminal SD0 is expressed as follows:
SD0(0)=0b,SD0(1)=0a
where 0a and 0b are the signals held in the SFFs 12a and 12b, respectively.

[0025] Similarly, the signals 1a and 1b held in the SFFs 13a and 13b are outputted in the following expressions:
SD1(0)=1b,SD1(1)=1a

[0026] The signals 2a and 2b held in the SFFs 14a and 14b are outputted in the following expressions:
SD2(0)=2b,SD2(1)=2a

[0027] The output signals are compared with expectation values in a test apparatus. When the comparison shows that a disparity occurs (also referred to as failed), in general, the terminal and the cycle in which the disparity has occurred are stored in the test apparatus and outputted as a failure log. For example, when a disparity occurs at the SD1 in the cycle 0, a failure log 15 shown in FIG. 1B is outputted.

[0028] Failure diagnosis (estimation of the location of failure) is carried out to investigate causes of failure of a semiconductor integrated circuit device showing a disparity, that is, a failed semiconductor integrated circuit device.

[0029] The first operation of failure diagnosis is identifying the SFF that has captured failure. The SFF that has captured failure is the SFF that has captured an output signal showing a disparity from the random logic.

[0030] In the second operation, a failure diagnostic apparatus (computer) assumes the state of the failure on the net data of the random logic circuit 11, and carries out failure simulation. If the SFF to which the failure has been transmitted in the result of the failure simulation coincides with the SFF identified in the first operation, the assumed failure can be judged to be true (the actual failure in the failed semiconductor integrated circuit device coincides with the assumed failure).

[0031] In the SCAN test method, the signal observed at a test output terminal in a cycle has a one-to-one relationship with the signal captured at each SFF. Therefore, the failure diagnostic apparatus can use the failure point (terminal and cycle) recorded in the failure log to easily identify the SFF that has captured the failure. For example, when the value of SD1(0) (=1b) is failed, that is, does not coincide with its expectation value, the SFF 13b that has captured the signal 1b can be identified. That is, the failure diagnosis described above can be applied to the SCAN test.

[0032] However, the SCAN test method has a problem of increased test time when the total number of SFFs in a semiconductor integrated circuit device and hence the number of SFFs per scan chain increases. To reduce the test time, it is effective to increase the number of scan chains. However, because of constraints of test apparatus and circuit design, it is difficult to reduce the number of SFFs per scan chain and hence the test time by increasing the number of test output terminals.

[0033] Therefore, a BIST (Built-in Self Test) circuit is provided in a semiconductor integrated circuit device. As shown in FIG. 2A, a semiconductor integrated circuit device 10a includes a test output compression circuit 16 as a space compression circuit. The test output compression circuit 16 is coupled to test output terminals SD. The test output compression circuit 16 compresses a plurality of input scan chain signals into a fewer number of signals than a number of the plurality of input scan chain signals. In FIG. 2A, the test output compression circuit 16 compresses the three 1-bit signals of the three scan chains into a one-bit signal. Such a test output compression circuit can increase the number of scan chains in the semiconductor integrated circuit device without increasing the number of test output terminals. That is, such a test output compression circuit can reduce the number of SFFs per scan chain and shorten the test time.

[0034] The test output compression circuit 16 is, for example, an exclusive OR circuit (XOR circuit). The test output compression circuit 16 compresses output signals of the SFFs 12a, 13a and 14a or SFFs 12b, 13b and 14b into a one-bit output signal. FIG. 2B shows the relationship between the signal observed at a test output terminal and the signal captured at each SFF.
SD(0)=0b xor 1b xor 2b
SD(1)=0a xor 1a xor 2a

[0035] However, in this method, since the signals captured at the SFFs in each stage (12b, 13b and 14b, for example) are compressed into a one-bit signal, the SFF where a disparity occurs cannot be identified from the result of recording a failure log. For example, when SD(0) shows a disparity, any one of the SFFs 12b, 13b and 14b may show a disparity, or all the SFFs may show disparities.

[0036] FIG. 3 shows a semiconductor integrated circuit device. For the semiconductor integrated circuit device shown in FIG. 3, virtual circuit data in which virtual space compression circuits 17a and 17b and virtual SFFs 18a and 18b are set for respective stages of a scan chain are generated in a failure diagnostic apparatus. A virtual space compression circuit and a virtual SFF are also generated for each test output terminal not shown. Each of the virtual space compression circuits 17a and 17b has the same configuration as that of the test output compression circuit 16 shown in FIG. 2A. The signal observed at the test output terminal SD in the virtual circuit data is the same as that observed in the actual circuit, so that the failure diagnostic method described above can be applied to the virtual circuit data.

[0037] However, in the method for the semiconductor integrated circuit device shown in FIG. 3, each of the one-bit virtual SFFs 18a and 18b represents the operations of the pins other than the input terminals D of SFFs as single operation of SFF by compressing. There is therefore a constraint that all signals other than those inputted to the input terminals D, such as clock signals, presets, and clear signals (none of them are illustrated), for a plurality of SFFs grouped as a virtual SFF, change in the same manner. Thus, the method described above may not accommodate all possible states of operation. An example of such situations is a case that the clock signal cka for SFFs 12a and 12b and the clock signal ckc for SFFs 14a and 14b are active, and the clock signal ckb for SFFs 13a and 13b is inactive as shown in FIG. 4. The SFFs 13a and 13b do not capture signals from a random logic circuit and output the signals originally held in the SFFs 13a and 13b. Therefore, the output signal SD(1) has a signal value obtained by compressing the signals that the SFFs 12a and 14a have captured from the random logic circuit and the signal that the SFF 13a has originally held (which is not a captured output signal from the random logic circuit). The output signal SD(1) has a signal value obtained by compressing the signals that the SFFs 12a, 13a and 14a have captured from the random logic circuit in on the virtual circuit data, and hence may differ from actual operation.

[0038] FIG. 5 shows an embodiment.

[0039] As shown in FIG. 5, a test system 20 includes a test apparatus 21 as a data generation unit, an observation unit, an execution unit and a judgment unit, and a failure diagnostic apparatus 22. The test apparatus 21 judges whether or not a semiconductor integrated circuit device (hereinafter referred to as LSI) 24 as a test target is good based on an input test pattern 23. The test pattern 23 includes a pattern of test signals for operating the LSI 24 for each cycle number in a shipping test, and expectation values representing signals that are expected to be outputted from the LSI 24 for that pattern. The test apparatus 21 not only operates the LSI 24 in the test mode but also supplies the test signals to the LSI 24. The test apparatus 21 compares the output signal, which is the test result outputted from the LSI 24, with its expectation value to judge whether or not the LSI 24 is good. The test apparatus 21 judges that the LSI 24 is defective when the output signal does not coincide with the expectation value, and generates a failure log 25 containing information on the cycle for the output signal of the judgment and the terminal where the output signal does not coincide with the expectation value.

[0040] The failure diagnostic apparatus 22 has a storage device (not illustrated). The storage device stores circuit information (net list) 26 of the LSI 24 as the test target. The failure diagnostic apparatus 22 constructs virtual circuit data of the LSI 24 based on the circuit information 26, assumes failure in the virtual circuit data, and performs failure simulation. The failure diagnostic apparatus 22 judges that the assumed failure (location, failure mode) is correct (true) when the simulation result coincides with the values in the failure log 25, while judging the assumed failure is incorrect (false) when the simulation result does not coincide with the values in the failure log 25. The failure diagnostic apparatus 22 then generates failure candidates 27 including the failure that has been judged to be true. According to this configuration, it is easily possible to judge whether the assumed failure is true or false. It is noted that a plurality of failures may be judged to be true depending on the failure of the LSI 24 and contained in the failure candidates 27.

[0041] In a detailed description, the failure diagnostic apparatus 22 sets a virtual circuit equivalent to the LSI 24, specifically, a logic circuit 31, scan chains 34 to 36, and a test output compression circuit 37, based on the net list. The virtual circuit includes a virtual pin set in such a way that a virtual output signal equivalent to the output signal outputted from the LSI 24 is obtained. The test apparatus 21 stores the test result of the LSI 24 as a failure log. The failure diagnostic apparatus 22 then executes failure simulation on the virtual circuit, acquires the simulation result at the set virtual pin, and compares the value of the simulation result with the information in the failure log. The failure diagnostic apparatus 22 judges that the assumed failure (location, failure mode) is correct (true) when the simulation result coincides with the values in the failure log, while judging that the assumed failure is incorrect (false) when the simulation result does not coincide with the values in the failure log.

[0042] FIG. 6 shows a semiconductor integrated circuit device (LSI).

[0043] As shown in FIG. 6, an LSI 24 includes a random logic circuit 31 and a BIST (Built-in Self Test) circuit 32 for carrying out the manufacturing test of the logic circuit 31. In this embodiment, the BIST circuit includes a test control circuit 33, a plurality of (three in FIG. 6) scan chains 34 to 36, and a test output compression circuit 37 as a space compression circuit. When test signals are inputted from the test apparatus 21, the test control circuit 33 operates the scan chains 34 to 36 and the test output compression circuit 37, supplies the test pattern to the logic circuit 31 via the scan chains 34 to 36 to operate the random logic circuit 31. The random logic circuit 31 operates according to the supplied test pattern and outputs resultant output signals to the scan chains 34 to 36. The scan chains 34 to 36 transmit the output signals of the random logic circuit 31 to the test output compression circuit 37. The test output compression circuit 37 is, for example, an exclusive OR circuit (XOR circuit), compresses the plurality of output signals outputted from the random logic circuit 31 into, for example, a one-bit output signal, and outputs the compressed signal.

[0044] The scan chain 34 includes scan flip-flops (SFFs) 34a and 34b that are connected in series and form two stages. Similarly, the scan chain 35 includes SFFs 35a and 35b, and the scan chain 36 includes SFFs 36a and 36b.

[0045] The random logic circuit 31 receives input signals from output terminals Q of the scan flip-flops (SFFs) 34a to 36b that form the scan chains 34 to 36. Output signals of the random logic circuit 31 are inputted to input terminals D of the SFFs 34a to 36b. In each of the scan chains 34 to 36, scan-in terminals SI of the SFFs 34a, 35a and 36a in the same stage (first stage) receive output signals of the test control circuit 33. The output terminals Q of the SFFs 34a to 36a in the same stage are coupled to the scan-in terminals SI of the SFFs 34b to 36b in the next stage (final stage). The output terminals Q of the SFFs 34b to 36b that form this stage are coupled to the test output compression circuit 37.

[0046] Although not illustrated, clock signals corresponding to the scan chains 34 to 36 (see FIG. 4) are supplied to the SFFs 34a to 36b. The SFFs 34a to 36b capture the output signals of the random logic circuit 31. The scan chains 34 to 36 operate as so-called shift registers in which the signals held in the SFFs are transmitted in response to the respective clock signals. For example, the SFF 34b, which is a component of the scan chain 34, sequentially outputs the signals held in the SFF 34b and the SFF 34a.

[0047] As described above, the test output compression circuit 37 is an exclusive OR circuit (XOR circuit). The test output compression circuit 37 compresses the plurality of output signals outputted from the SFFs 34b to 36b in the final stage into a one-bit output signal and outputs the compressed signal via a test output terminal SD. The test apparatus 21 shown in FIG. 5 compares the signals sequentially outputted from the test output terminal SD with expectation values, and, when they differ from each other (failed), stores information on the cycle and the terminal (such as the terminal number) as the failure log 25.

[0048] The failure diagnostic apparatus 22 shown in FIG. 5 generates virtual circuit data based on the circuit information (net list) 26 of the LSI 24. Specifically, the failure diagnostic apparatus 22 sets a virtual space compression circuit and a virtual external pin for each stage of the scan chains 34 to 36. The virtual space compression circuit has the same configuration as that of the space compression circuit (test output compression circuit 37).

[0049] For the LSI 24 shown in FIG. 6, the SFFs 34a to 36a form the same stage and the SFFs 34b to 36b form the same stage. As shown in FIG. 7, the failure diagnostic apparatus 22 generates a test output compression circuit 37a as the virtual space compression circuit to which the output terminals of the SFFs 34a to 36a that form the same stage are connected and a virtual pin PT1 connected to the circuit 37a.

[0050] The failure diagnostic apparatus 22 further generates a test output compression circuit 37b as the virtual space compression circuit to which the output terminals of the SFFs 34b to 36b that form the same stage are connected and a virtual pin PT0 connected to the circuit 37b. That is, the failure diagnostic apparatus 22 generates virtual circuit data for each stage of the scan chains 34 to 36 in such a way that the output signals of the SFFs are compressed and outputted to the virtual pin.

[0051] The output signals of the virtual pins PT0 and PT1 have a one-to-one relationship with the signals outputted in a time series from the test output terminal SD of the LSI 24. Specifically, the output signal of the virtual pin PT0 corresponds to the signal outputted from the test output terminal SD of the LSI 24 in the cycle 0. The output signal of the virtual pin PT1 corresponds to the signal outputted from the test output terminal SD of the LSI 24 in the cycle 1.

[0052] Then, based on the contents of the failure log 25, the failure diagnostic apparatus 22 assigns the failure log to the corresponding virtual pin. The signals captured at the SFFs 34a to 36a and 34b to 36b in the respective stages are compressed and outputted from the test output terminal SD. The signals outputted in a time series correspond to the stage numbers of the scan chains 34 to 36. For example, the failure log first observed (cycle 0) at the test output terminal SD corresponds to the final stage of the scan chains 34 to 36. Therefore, the failure diagnostic apparatus 22 assigns the first observed failure log to the virtual pin PT0 to which the final stage is connected.

[0053] Then, the failure diagnostic apparatus 22 assumes failure in the random logic circuit 31 in the generated virtual circuit data and carries out failure simulation. The result of the failure simulation is obtained in the form of whether or not the failure is transmitted to one of the set virtual pins, that is, whether or not a signal at a level according to the failure is outputted.

[0054] The output signals at the virtual pins in the failure simulation correspond to the signals that the test output compression circuit 37a and 37b compresses the signals held in the SFFs that form each stage of the scan chains 34 to 36. The signal held in each SFF is determined by the signal to the input terminal of the SFF. For example, when the clock signal is active, the signal value at the input terminal D is captured. When the clock signal is inactive, the signal value already held remains. Therefore, for example, even when the clock is inactive at one SFF in a certain stage, the output signal observed at each of the virtual pins reflects the state of the clock signal at each SFF.

[0055] When the clock signal supplied to the SFF 35a shown in FIG. 7 is inactive and the clock signals supplied to the SFFs 34a and 36a are active, the SFF 35a does not capture the signal inputted to the input terminal D but holds the state of the current signal, and the SFFs 34a and 36a capture the signals inputted to the input terminals D. The output signal of the virtual pin PT1 corresponds to the value obtained by compressing the signal values of the SFFs 34a to 36a connected to the test output compression circuit 37a to which the virtual pin PT1 is connected, that is, the value obtained by compressing the signal values that the SFFs 34a and 36a have captured from the random logic circuit 31 and the signal value that the SFF 35a has originally held. Therefore, even in the case described above, the signal level at the test output terminal SD in the actual circuit will not differ from the signal levels at the virtual pins PT1 and PT1 in the virtual circuit data.

[0056] Then, the failure diagnostic apparatus 22 checks whether the virtual pin to which the failure is transmitted in the failure simulation coincides with the virtual pin to which the failure log 25 is assigned. When these virtual pins coincide with each other, the failure diagnostic apparatus 22 judges that the assumed failure is true. On the other hand, when these virtual pins do not coincide with each other, the failure diagnostic apparatus 22 judges that the assumed failure is false. When the failure diagnostic apparatus 22 has judged the assumed failure to be false, the failure diagnostic apparatus 22 assumes other failure mode or failure location and then carries out failure simulation for judgment described above.

[0057] This embodiment provides the following advantages:

[0058] (1) Based on the circuit information 26 of the LSI 24, the failure diagnostic apparatus 22 generates the virtual circuit data that sets, for the stages of the scan chains 34 to 36, the test output compression circuits 37a and 37b that compress the output signals of the scan flip-flops 34a to 36a and 34b to 36b in the respective stages as well as the virtual pins PT1 and PT0 connected to the output terminals of the compression circuits 37a and 37b. Then, the failure diagnostic apparatus 22 has the LSI 24 carry out a test and observes the signal at the test output terminal SD. The failure diagnostic apparatus 22 carries out failure simulation on the virtual circuit data to check whether or not the assumed failure has been transmitted to the virtual pins PT1 and PT, and then compares the failure log 25 at the test output terminal SD with the result of whether or not the failure has been transmitted to the virtual pins PT1 and PT0 to judge whether or not the LSI 24 has failed.

[0059] The signal at each of the virtual pins PT1 and PT0 corresponds to the signal observed at the test output terminal SD independent of the operation of the scan chains 34 to 36. That is, the signal at each of the virtual pins corresponds to the signal observed at the test output terminal described above. Failure diagnosis can therefore be carried out in a failure diagnostic method similar to the SCAN test method. Furthermore, since the scan flip-flops are independent of each other, failure diagnosis of the semiconductor integrated circuit device (LSI 24) can be carried out without operation condition constraints.

[0060] Although the LSI 24 with three scan chains 34 to 36 is diagnosed for failure in this embodiment, an LSI with two, four or more scan chains may be diagnosed for failure.

[0061] Although the scan chains 34 to 36 in this embodiment include two scan flip-flops 34a and 34b, 35a and 35b, and 36a and 36b, respectively, an LSI using scan chains including three (three stages) or more scan flip-flops may be diagnosed for failure.

[0062] Although the LSI 24 with one test output terminal SD has been diagnosed for failure in this embodiment, an LSI with a plurality of test output terminals may be diagnosed for failure. For example, as shown in FIG. 8, an LSI 40 includes a random logic circuit 41, four scan chains 42 to 45 connected to the circuit 41, a test output compression circuit 46 as the space compression circuit that compresses the output signals of the scan chains 42 and 43, and a test output compression circuit 47 as the space compression circuit that compresses the output signals of the scan chains 44 and 45.

[0063] The output terminals of the test output compression circuits 46 and 47 are connected to two test output terminals SD0 and SD1, respectively. The failure diagnostic apparatus 22 generates virtual circuit data shown in FIG. 9 based on the circuit information of the LSI 40. The virtual circuit data includes a test output compression circuit 46a as the virtual space compression circuit to which SFFs 42a and 43a, which form the first stage of the scan chains 42 and 43, are connected, and a test output compression circuit 47a as the virtual space compression circuit to which SFFs 44a and 45a, which form the first stage of the scan chains 44 and 45, are connected.

[0064] Furthermore, the virtual circuit data includes a test output compression circuit 46b as the virtual space compression circuit to which SFFs 42b and 43b, which form the final stage of the scan chains 42 and 43, are connected, and a test output compression circuit 47b as the virtual space compression circuit to which SFFs 44b and 45b, which form the final stage of the scan chains 44 and 45, are connected. That is, in the LSI 40 shown in FIG. 8, a virtual pin and a test output compression circuit are set for each of the test output terminals and each stage of the scan chains.

[0065] In the semiconductor integrated circuit device shown in FIG. 8, the output signals of the scan chains 42 and 43 are compressed and outputted to one test output terminal SD0. The output signals of the scan chains 44 and 45 are compressed and outputted to one test output terminal SD1. These output signals may be outputted to a plurality of test output terminals. For example, in an LSI 50 shown in FIG. 10, output signals of the scan chains 42, 43 and 44 are inputted to a test output compression circuit 51 as the space compression circuit. Output signals of the scan chains 43, 44 and 45 are inputted to a test output compression circuit 52 as the space compression circuit. Therefore, in the LSI 50, the output signals of the scan chains 43 and 44 are compressed along with the output signals of the other scan chains and outputted to the two test output terminals SD0 and SD1, respectively.

[0066] In the case of the LSI 50, the connection of test output compression circuits in virtual circuit data is the same as the connection in the actual LSI 50. That is, as shown in FIG. 11, SFFs 42a, 43a and 44a, which form the first stage of the scan chains 42 to 44, are connected to a test output compression circuit 51a as the virtual space compression circuit. SFFs 43a, 44a and 45a, which form the first stage of the scan chains 43 to 45, are connected to a test output compression circuit 52a as the virtual space compression circuit. Similarly, SFFs 42b, 43b and 44b, which form the final stage of the scan chains 42 to 44, are connected to a test output compression circuit 51b as the virtual space compression circuit. SFFs 43b, 44b and 45b, which form the final stage of the scan chains 43 to 45, are connected to a test output compression circuit 52b as the virtual space compression circuit.

[0067] The number of scan chains, the number of stages of SFFs that form each of the scan chains, the number of test output terminals, and the configuration of the test output compression circuit may be changed or combined in any way.

[0068] In this embodiment, the test apparatus 21 carries out the test on the actual LSI 24, and the failure diagnostic apparatus 22 carries out, based on the circuit information 26 on the LSI 24, the construction of the virtual circuit data, the failure simulation, and the failure judgment. However, these operations may be carried out in a single apparatus.

[0069] Although this embodiment employs the configuration in which the test pattern 23 is inputted to the test apparatus 21, a configuration in which the LSI includes a circuit that generates a test pattern may be employed. Alternatively, the LSI may include a circuit that compares an output signal with its expectation value and outputs the comparison result.

[0070] Although a few preferred embodiments of the present invention have been shown and described, it would be appreciated by those skilled in the art that changes may be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the claims and their equivalents.