Method for making electrode

[0001] This application is a divisional application of and claims the benefit of U.S. patent application Ser. No. 11/391,993 filed Mar. 28, 2006 now U.S. Pat. No. 7,812,450, entitled “ELECTRODE AND METHOD FOR MAKING THE SAME”, the entire contents of which are incorporated herein by reference.

[0002] 1. Technical Field

[0003] The invention relates generally to methods for making electrodes, more particularly, to a method for making an electrode having a high specific surface area thereof.

[0004] 2. Description of Related Art

[0005] In recent years, demand has been growing for more compact and thin electronic equipment, thus capacitors and batteries used in electronic equipment are also required to be thin whilst also providing high capacitance. For example, in a non-contact IC card, the thickness thereof is as thin as 1 mm or less, so the thickness of the capacitors included therein should be several hundred microns or less.

[0006] A parallel plate capacitor is one kind of conventional charge storage device. The basic design of these capacitors involves two conductive electrodes separated by a dielectric or insulative thin film material. To provide increased capacitance, one or both electrodes of the storage capacitors can be formed with a roughened surface, such as that which is provided by hemispherical grained (HSG) polysilicon, so as to increase the area over that which is provided by electrodes having planar surfaces. Other methods of providing increased capacitance involve using an insulating material having an increased dielectric constant and reducing the thickness of the dielectric insulating layer so as to reduce the distance between the electrodes.

[0007] While many variations of this type of capacitor have been developed, all of the known designs suffer from many disadvantages, having complicated structures, high construction costs and poor surface quality. Furthermore, mechanical strength becomes poorer as the capacitor becomes thinner.

[0008] What is needed, therefore, is an electrode having high capacitance and simple structure, and a method for making the electrode.

[0015] Corresponding reference characters indicate corresponding parts throughout the several views. The exemplifications set out herein illustrate at least one preferred embodiment of the present invention, in one form, and such exemplifications are not to be construed as limiting the scope of the invention in any manner.

[0016] Reference will now be made to the drawings to describe embodiments of the present electrode and the method for making the same, in detail.

[0017] Referring to FIG. 4, an electrode 100 according to an exemplary embodiment is shown. The electrode 100 includes a conducting substrate 10 with a number of nano-sized structures 13 thereon and a coating 15 formed on the nano-sized structures. The conducting substrate 10 is made of a material selected from the group consisting of graphite, lithium, aluminum, copper, silver, nickel, tungsten, molybdenum and any suitable combination alloy thereof.

[0018] The nano-sized structures 13 are convex-shaped. A size of each nano-sized structure is in the range from 2 nanometers to 50 nanometers. The size of each nano-sized structure is generally in the range from 10 nanometers to 40 nanometers. The nano-sized structures 13 are configured for increasing a specific surface area of the electrode 10.

[0019] The coating 15 is formed on the nano-sized structures 13. The coating 15 is comprised of carbon nanotubes and nano-sized particles. The nano-sized particles are selected from the group consisting of indium tin oxide, chromium oxide (CrO_x), cobalt oxide (CoO_x), nickel oxide (NiO_x), ferric oxide (FeO_y), aluminum oxide, zinc oxide (ZnO_x), silica oxide, titanium oxide and zirconium oxide (ZrO_x), wherein x is in the range from 1 to 2; and y is in the range from 1 to 1.5. A thickness of the coating 15 is in a range from 1 nanometer to 20 nanometers. Preferably, the thickness of the coating 15 is in a range from 2 nanometers to 10 nm.

[0020] Referring to FIG. 5, an electrode 200 according to an alternative embodiment is shown. The electrode 200 includes a conducting substrate 102 with a number of nano-sized structures 132 thereon, and a coating 152 formed on the nano-sized structures 132. The main difference between the electrodes 100 and 200 is that the nano-sized structures 132 of the electrode 200 are concave-shaped.

[0021] In another embodiment, a method for making above-described electrode 10 includes the following steps in no particular order of:

• • [0022] providing a conducting substrate;
  • [0023] forming a number of nano-sized structures on the conducting substrate;
  • [0024] forming a coating on the nano-sized structures, wherein the nano-sized structures are configured for increasing a specific surface area of the electrode.

[0025] Referring FIG. 1, a conducting substrate 10 and an imprinting mold 11 for making the electrode 10 are provided. The conducting substrate 10 is made of a material selected from the group consisting of graphite, lithium, aluminum, copper, silver, nickel, tungsten, molybdenum and any suitable combination alloy thereof. The imprinting mold 11 is used for imprinting nano-sized structures on the conducting substrate 10. The imprinting mold 11 is made by a photolithography method and has a nano-sized structures surface 12 according to a predetermined design pattern. The imprinting mold 11 is made of a silicon-based material and has a nickel coating (not shown) on the nano-sized structures surface 12.

[0026] Also referring to FIG. 2 and FIG. 3, through a nano imprinting process, a plurality of nano-sized structures 13 is formed on a surface of the conducting substrate 10 using the imprinting mold 11. Nano imprinting method is one of cheapest nanolithography techniques available for laboratories, and resolutions as low as 10 nm can be reached. The principle of the nano imprinting method is an embossing of a patterned mold in a heat resistant container. The first step in nano imprinting method is to build a silicon relief mold using direct-write electron-beam equipment. That is a slow process wherein each feature is defined by rastering an electron beam across the wafer, but once the imprinting mold has been defined, it can be used to stamp out features with the same speed of the mask-based exposure process. As a result, nano imprinting methods can make nano-sized structures easily accessible for industrial applications. An electrode 100 made by a nano imprinting process is shown in FIG. 3.

[0027] Referring to FIG. 4, a coating 15 is deposited on the nano-sized structures 13 by a chemical vapor deposition method or a sputtering method. A thickness of the nano material coating 15 is in a range from 1 nanometer to 20 nanometers. Preferably, the thickness of the coating 15 is in a range from 2 nanometers to 10 nm. The coating 15 is comprised of carbon nanotubes and nano-sized particles. The nano-sized particles are selected from the group consisting of indium tin oxide, chromium oxide (CrO_x), cobalt oxide (CoO_x), nickel oxide (NiO_x), ferric oxide (FeO_y), aluminum oxide, zinc oxide (ZnO_x), silica oxide, titanium oxide and zirconium oxide (ZrO_x) wherein x is in the range from 1 to 2; and y is in the range from 1 to 1.5.

[0028] The conventional capacitors are regular oxide materials with flat surfaces and have limited capacity for electrical charges. The present invention uses nano-sized structures and a coating to increase specific surface area, so that the present electrode can store much more electrical charge.

[0029] Finally, it is to be understood that the above-described embodiments are intended to illustrate rather than limit the invention. Variations may be made to the embodiments without departing from the spirit of the invention as claimed. The above-described embodiments illustrate the scope of the invention but do not restrict the scope of the invention.