AC and DC temperature compensation scheme for DCR current sense

[0001] This application claims the benefit of U.S. Provisional Application Ser. No. 61/015,859, filed on Dec. 21, 2007, which is herein incorporated by reference for all intents and purposes.

[0002] The benefits, features, and advantages of the present invention will become better understood with regard to the following description, and accompanying drawings in which:

[0003] FIG. 1 is a simplified schematic and block diagram of a multiphase voltage regulator including a current sense scheme according to one embodiment to provide both AC and DC temperature compensation;

[0004] FIG. 2 is a simplified schematic and block diagram of a voltage regulator including a current sense scheme according to one embodiment to provide both AC and DC temperature compensation illustrating a more detailed scheme of the controller;

[0005] FIG. 3 is a schematic diagram of a voltage regulator circuit including a current sense scheme according to one embodiment to provide both AC and DC temperature compensation in which the sense signal is provided as a current to a temperature coefficient RC circuit;

[0006] FIG. 4 is a schematic diagram of a voltage regulator circuit including a current sense scheme according to another embodiment to provide both AC and DC temperature compensation in which the sense signal is provided as a voltage applied to a temperature coefficient RC circuit; and

[0007] FIG. 5 is a schematic diagram of a portion of a voltage regulator circuit including a current sense scheme according to yet another embodiment to provide both AC and DC temperature compensation similar to that shown in FIG. 4 yet using a single summing amplifier.

[0008] The following description is presented to enable one of ordinary skill in the art to make and use the present invention as provided within the context of a particular application and its requirements. Various modifications to the preferred embodiment will, however, be apparent to one skilled in the art, and the general principles defined herein may be applied to other embodiments. Therefore, the present invention is not intended to be limited to the particular embodiments shown and described herein, but is to be accorded the widest scope consistent with the principles and novel features herein disclosed.

[0009] It is desired to accurately sense the inductor current of each phase for loadline and current sharing purposes in voltage regulator applications including multiphase voltage regulators. In one existing scheme a resistor-capacitor (RC) circuit is coupled across the output inductor (L) used to measure the voltage drop across the inherent DC resistance (DCR) of the output inductor. The DCR has a temperature coefficient, denoted DCR(T), meaning that its value is a function of temperature (T). In one embodiment, DCR(T) is positive such that its resistance increases with increasing temperature. A negative temperature coefficient (NTC) resistor has been used in conventional circuits in an attempt to cancel the DC impact of the DCR change with temperature. The AC impact of the temperature variation, however, has been ignored in the conventional configurations. In this manner, the time constant L/DCR(T) of the output inductor (with inductance L) is not cancelled under all operational temperature conditions. Thus, there exists some difference between the sensed current signal and the real current during transient events in the voltage regulator. In the conventional configuration, DCR is smaller in cooler operating conditions causing undesirable overshoot and undershoot in response to transient events.

[0010] FIG. 1 is a simplified schematic and block diagram of a multiphase voltage regulator 100 including a current sense scheme according to one embodiment to provide both AC and DC temperature compensation. The voltage regulator 100 includes a controller 101 for controlling “N” power phases (in which N is a positive integer) for converting an input voltage VIN to an output voltage VOUT developed on an output node 103. The controller 101 is referenced to a signal ground (RGND) whereas each of the N power phase circuits are referenced to a separate power ground (PGND) as understood by those skilled in the art. An output capacitor CO is coupled between the output node 103 and PGND. Each of the power phase circuits are configured in similar manner. In the first power phase circuit, VIN is provided to the drain of a high side electronic switch QH1 which has its source coupled to a first phase node PH1. In the illustrated embodiment, PH1 is provided to an input of the controller 101. A lower electronic switch QL1 has its drain coupled to PH1 and its source coupled to PGND. The controller 101 provides a high gate control signal GH1 to the gate of QH1 and a low gate control signal GL1 to the gate of QL1. The first power phase circuit includes a first output inductor L1 coupled between PH1 and the output node 103 and the first output inductor L1 develops a current IL1. In the last power phase circuit, VIN is provided to the drain of an upper electronic switch QHN which has its source coupled to a phase node PHN, which is provided to an input of the controller 101. A lower electronic switch QLN has its drain coupled to PHN and its source coupled to PGND. The controller 101 provides a high gate control signal GHN to the gate of QHN and a low gate control signal GLN to the gate of QLN. The last power phase circuit includes an output inductor LN coupled between PHN and the output node 103 and the last output inductor LN develops a current ILN.

[0011] Although only two power phase circuits 1 and N are shown, it is understood that any number of power phase circuits may be implemented. It is further noted that the present invention is equally applicable to a single-phase power regulator. The electronic switches QH1, QL1, . . . , QHN, QLN are each depicted as N-channel metal-oxide-semiconductor, field-effect transistor (MOSFET) devices having their drain-source current paths coupled in series between VIN and PGND. Other types of electronic switching devices are contemplated, such as P-channel switches or MOS-type switches or the like. In one embodiment, the controller 101 incorporates driver circuitry or the like for each phase to drive the upper and lower gate signals GHi and GLi (in which “i” is an index from 1 to N representing a given power phase circuit) to turn on and off the corresponding electronic switches QHi and QLi. In an alternative embodiment, the controller 101 provides corresponding pulse width modulation (PWM) signals (not shown) to corresponding driver circuits (not shown) for driving the electronic switches for each phase. In operation, the controller 101 asserts the upper drive signal GHi high to activate the corresponding phase circuit and then asserts GHi low and asserts GLi high to de-activate the corresponding phase circuit. For example, the controller 101 asserts GH1 high to turn on QH1 which effectively couples VIN to L1 via the phase node PH1 during a portion of the PWM cycle. The controller 101 then asserts QH1 low and asserts GL1 high to turn QL1 on which effectively couples PGND to L1 via the phase node PH1. The controller 101 operates each phase in similar manner. In one embodiment, the controller 101 activates each of the power phase circuits one at a time in round-robin fashion or the like. In an alternative embodiment, multiple phase circuits may be active at any one time depending upon the particular control configuration.

[0012] As noted above, it is desired to accurately sense the inductor current ILi of each phase for loadline and current sharing purposes or the like. In the first phase circuit, an RC circuit including a resistor R1 and a capacitor C1 is coupled to the first inductor L1. As shown, R1 has one end coupled to PH1 at one end of the inductor L2, and the other end of the resistor R1 is coupled to one end of a corresponding capacitor C1. The other end of the capacitor C1 is coupled to the other end of the inductor L1 at the output node 103. The intermediate junction between R1 and C1 is coupled to a positive current sense pin IS1+ of the controller 101. It is noted that pin names are the same as the corresponding signal or node names unless otherwise specified (e.g., pin IS1+ develops a signal IS1+ on a node IS1+). The other end of the capacitor C1 is coupled to one end of a sense resistor RSEN1, which has its other end coupled to a negative current sense pin IS1+ of the controller 101. Each phase circuit is configured in substantially the same manner with a corresponding RC circuit. As shown for the last phase circuit N, for example, a resistor RN and a capacitor CN are coupled in series across the output inductor LN. The intermediate junction of RN and CN is coupled to a positive current sense pin ISN+ of the controller 101, and the other end of the capacitor CN is coupled to one end of another sense resistor RSENN. The other end of the resistor RSENN is coupled to a negative current sense pin ISN− of the controller 101. In an alternative embodiment, each of the sense resistors RSENi may be incorporated within the controller 101.

[0013] The controller 101 internally includes a sense circuit 105 which is coupled to each of the positive and negative current sense pins ISi+ and ISi− of the power phase circuits. The sense circuit 105 is also coupled to a sense pin SEN externally coupled to an RC circuit 107 referenced to RGND. The RC circuit 107 also has a temperature coefficient, denoted RC(T), such that its “value” or time constant is a function of temperature (T). The sense circuit 105 is further coupled to a correction pin COR2, which is further coupled to another RC circuit 109 referenced to RGND. In the illustrated embodiment, the RC circuit 109 includes a resistor RX and a capacitor CX coupled in parallel between COR2 and RGND. In one embodiment no additional pins are provided. In another embodiment, as illustrated using dashed lines, the sense circuit 105 is further coupled to another correction pin COR1 which is further coupled to the RC circuit 107 as further described below.

[0014] The time constant of the RC circuits coupled to each of the output inductors Li are approximately equal and are further equal to the time constant of the RC circuit 109. In particular, R1*C1≈R2*C2 (for phase 2, not shown)≈ . . . ≈RN*CN≈RX*CX (in which an asterisk “*” denotes multiplication). It is noted that the resistances of resistors, capacitance of capacitors and inductance of inductors are the same as the component name unless otherwise specified. Thus, for example, the resistor R1 has a resistance R1, the capacitor C1 has a capacitance C1, the inductor L1 has an inductance L1, etc. Although the resistances of the resistors R1, R2, . . . , RN and RX may be equal to each other, they may also be different as long as the capacitances of the corresponding capacitors C1, C2, . . . , CN and CX are adjusted accordingly to maintain approximately equal time constants. Also, the particular time constant may be any convenient value and does not necessarily be the same as the time constant of the inductors Li as further described below.

[0015] The sense circuit 105 develops a sense signal on the SEN pin based on the ISi+ and ISi− signals from the power phase circuits and applies the sense signal to the RC circuit 107. The particular type of sense signal on the SEN pin depends upon the particular embodiment of the sense circuit 105. Each of the output inductors Li has an inherent DC resistance DCR with a temperature coefficient, denoted DCR(T), which modifies the corresponding ISi+/− signals accordingly. For convenience and simplicity, the inductance (L) and inherent DC resistance DCR(T) of each of the inductors Li are assumed to be approximately equal. The RC circuit 107 is configured with an opposite temperature coefficient RC(T) as each of the inductors Li so that the value (or time constant) of RC(T) is also modified with temperature in such a manner as to compensate for the temperature coefficient of the inductors Li. In one embodiment, the RC circuit 107 adjusts the sense signal on the SEN pin according to temperature and the sense circuit 105 correspondingly adjusts COR2 applied to the RC circuit 109. In another embodiment, the RC circuit 107 provides a signal on the COR1 pin in response to the sense signal provided on the SEN pin and the sense circuit 105 correspondingly adjusts COR2 applied to the RC circuit 109. In either case, the sense circuit 105 applies the adjustment to develop a corrected current sense signal ISEN_COR which is temperature-compensated for both AC and DC conditions.

[0016] FIG. 2 is a simplified schematic and block diagram of a voltage regulator 200 including a current sense scheme according to one embodiment to provide both AC and DC temperature compensation. The voltage regulator 200 is shown with a single phase although it is understood that the voltage regulator 200 generically represents a single-phase voltage regulator or a multiphase voltage regulator with any number of phases (2 or more) as understood by those skilled in the art. The sole power phase circuit is generically shown as an output inductor L coupled between a phase node PH and an output node 203 developing an output voltage VOUT. The inductor L develops a current IL and further includes an inherent DC resistance (DCR) having a temperature coefficient, denoted DCR(T). The inherent DC resistance of the inductor L is shown as a separate resistor DCR(T) developing a voltage V1, where it is understood that the resistor DCR(T) is not a separate resistor but is incorporated within or otherwise represents the resistance of the windings of the inductor L. An RC circuit 204 including a resistor R and a capacitor C is provided in which R and C are coupled in series between PH and VOUT in a similar manner previously described. The intermediate junction between R and C of the RC circuit 204 is coupled to a positive current sense pin IS+ of a controller 201 which operates in a similar manner as the controller 101 to provide AC and DC compensation as further described herein. The other end of the capacitor C is coupled to a sense resistor RSEN, having its other end coupled to a negative current sense pin IS− of the controller 201. The capacitor C develops a voltage V2 which is sensed by the controller 201 using the sense resistor RSENS.

[0017] The controller 201 includes a first amplifier circuit (AMP1) 205 internally coupled to the IS+/− pins for sensing the voltage V2 across the capacitor C. The amplifier circuit 205 develops a sense signal SEN at its output, which is provided to the RC circuit 107 via the SEN pin in a similar manner as previously described. In one embodiment, the SEN signal is provided directly to an input of a second amplifier circuit (AMP2) 207 as a correction signal COR1. In an alternative embodiment, a separate COR1 signal is provided from the RC circuit 107 via a separate COR1 pin which is coupled to the input of the amplifier circuit 207. The alternative configurations are depicted using dashed lines. The RC circuit 109 is shown generically as a resistor R and a capacitor C coupled in parallel between a COR2 pin and RGND in a similar manner as previously described. The COR2 pin/node is further coupled internally to another input of the amplifier circuit 207, which develops the correct sense signal ISEN_COR at its output. It is noted that the RC circuit 204 coupled to the inductor L is shown with similar R and C components as the RC circuit 109, where it is understood that the resistances of the resistors R or the capacitances of the capacitors C need not be equal, as long as the time constant R*C is approximately equal for both RC circuits 204 and 109. In one embodiment, the time constant RC of the RC circuits 109 and 204 need not be related to the time constant of the inductor L, or L/DCR. In an alternative embodiment, the time constant R*C of each of the RC circuits 204 and 109 is approximately equal to the time constant L/DCR (T_NOM) of the inductor L at a particular temperature T_NOM. The temperature T_NOM is selected as any convenient value, such as room temperature or an expected nominal operating temperature or the like.

[0018] The time constant of the RC circuit 107 is approximately equal to the time constant L/DCR(T) of the inductor L. The amplifier circuit 205 develops the SEN signal based on the sensed voltage V2 representing the current IL through the inductor L. The amplifier circuit 205 applies the SEN signal to the RC circuit 107 and either the SEN signal or the COR1 signal is adjusted based on temperature. The amplifier circuit 207 applies COR1 (or SEN) as COR2 to the RC circuit 109 and develops the ISEN_COR signal. The current sense signal ISEN_COR is a corrected sense signal which is temperature-compensated for both AC and DC conditions.

[0019] FIG. 3 is a schematic diagram of a voltage regulator circuit 300 including a current sense scheme according to one embodiment to provide both AC and DC temperature compensation. Each of N phases PH1-PHN is shown generically in a similar manner as shown in FIG. 2. The inherent DC resistance DCR(T) with temperature dependency of the inductor L for each of N phases (in which N is a positive integer) develops a voltage V1 as a function of the inductor current IL in each phase. The RC circuit 204 including the series-coupled resistor R and capacitor C is coupled across the output inductor L in each phase as shown in which the capacitor C develops a voltage V2 in a similar manner as previously described. V2 is equal to V1 if the time constant R*C is equal to L/DCR(T). The resistance value of DCR(T), however, varies with temperature. In the first phase circuit, the junction between R and C is coupled to the IS1+ pin of a controller 301. The other end of the capacitor C is coupled to one end of a sense resistor RSEN, having its other end coupled to the IS1− pin of the controller 301. Each phase circuit is substantially similar except coupled to different current sense pins as shown. For example, the RC circuit 204 and sense resistor RSEN of the last phase circuit N is coupled to current sense pins ISN+ and ISN−.

[0020] The voltage V2 of each phase is sensed with a corresponding one of multiple operational amplifiers 303, each having its non-inverting (+) input coupled to the positive current sense pin ISi+ and its inverting (−) input coupled to the negative current sense pin ISi−. An N-channel device 305, such as an N-channel FET or the like, has its gate coupled to the output of the amplifier 303 and its source coupled to the inverting input of the amplifier 303 in each phase. In each phase, the drain of the corresponding device 305 is coupled to the input of a current mirror 308, and each current mirror 308 has its output coupled to a current summing node 309. In the illustrated embodiment, each current mirror is configured with a pair of P-channel devices P1 and P2 with commonly-coupled sources and gates. The gates are further coupled to the drain of P1 at the input of the current mirror 308, in which the drain of P2 forms its output. In operation, the amplifier 303 of each phase circuit has a virtual ground input which effectively places the voltage V2 across RSEN to develop a current ISENi. The amplifier 303 controls the device 305 to sink the current ISENi from the input of the corresponding current mirror 308, which mirrors the current ISENi into the summing node 309. In this manner, a current ISEN1 is developed for phase 1, a current ISEN2 (not shown) is developed for phase 2, and so on up to ISENN for the last phase N. A current ISENX represents any currents from other phases (not shown, e.g., 2, 3, etc.), for a combined current of ISEN. Thus, ISEN=ISEN1+ISEN2+ . . . +ISENN is applied to the summing node 309 from all of the phase circuits. For multiphase applications, ISEN is equal to the sum of all sensed phase current or the average of all sensed phase current.

[0021] The summing node 309 is internally coupled to the SEN pin of the controller 301, and an external RC circuit 307 is coupled between the SEN pin and RGND. The RC circuit 307 includes a resistor RT and a capacitor CT coupled in parallel, and summing node 309 develops a sense voltage of V_ISEN in response to the ISEN current flowing into RT and CT via the SEN pin. The summing node 309 is coupled to the non-inverting input of another operational amplifier 311, having its inverting input coupled to the COR2 pin of the controller 301. The RC circuit 109 comprising the resistor R and capacitor C is coupled between the COR2 pin and RGND. An N-channel device 313 is coupled to the amplifier 311 in a similar manner as the device 305 is coupled to the amplifier 303. In particular, the output of the amplifier 311 is coupled to the gate of 313, having its source coupled to the inverting input of the amplifier 311. The drain of device 313 is coupled to the input of a current mirror 315, having an output providing the corrected sense current ICOR_SEN. The current mirror 315 is configured in substantially the same manner as the current mirror 308 including P-channel devices P1 and P2 coupled to operate in substantially the same manner. In summary, the ISEN current is provided via the SEN pin to the RC circuit 307, which develops the V_ISEN voltage provided to an input of the amplifier 311. In this case, the SEN pin providing the ISEN current operates as the first correction node so that separate pin COR1 is not provided.

[0022] The following equation (1) is used to determine the voltage V2 across the capacitor C:

[0023] $\begin{array}{cc}V2=\frac{\mathrm{sL}+\mathrm{DCR}\left(T\right)}{1+\mathrm{sCR}}\left(\frac{V1}{\mathrm{DCR}\left(T\right)}\right)& \left(1\right)\end{array}$
in which “s” is the Laplace transform complex variable. The voltage V1 across the inherent DC resistance DCR(T) of each inductor L is according to the following equation (2):
V1=DCR(T)*IL  (2)
In this manner, the voltage V2 may be re-written according to the following equation (3):

[0024] $\begin{array}{cc}V2=\frac{\mathrm{sL}+\mathrm{DCR}\left(T\right)}{1+\mathrm{sCR}}\left(\mathrm{IL}\right)& \left(3\right)\end{array}$
in which RSEN is the resistance of the sense resistor RSEN. The sense current ISEN1 of the first phase circuit is according to the following equation (4):

[0025] $\begin{array}{cc}\mathrm{ISEN}1=\frac{V2}{\mathrm{RSEN}}=\frac{\mathrm{sL}+\mathrm{DCR}\left(T\right)}{1+\mathrm{sRC}}\left(\frac{\mathrm{IL}}{\mathrm{RSEN}}\right)& \left(4\right)\end{array}$
The voltage V_ISEN at summing node 309 is determined according to the following equation (5):

[0026] $\begin{array}{cc}\mathrm{V\_ISEN}=\mathrm{ISEN}\frac{\mathrm{RT}}{1+\mathrm{sRC}}=\sum _{i=0}^N\mathrm{ISENi}\frac{\mathrm{RT}}{1+\mathrm{sRT}*\mathrm{CT}}& \left(5\right)\end{array}$
where equation (5) may be rewritten according to the following equation (6):

[0027] $\begin{array}{cc}\mathrm{V\_ISEN}=\frac{\mathrm{sL}+\mathrm{DCR}\left(T\right)}{1+\mathrm{sRC}}\left(\frac{\mathrm{RT}}{1+\mathrm{sRT}*\mathrm{CT}}\right)\left(\frac{\sum ^{}\mathrm{IL}}{\mathrm{RSEN}}\right)& \left(6\right)\end{array}$
and where equation (6) may be rewritten according to the following equation (7):

[0028] $\begin{array}{cc}\mathrm{V\_ISEN}=\frac{s\frac{L}{\mathrm{DCR}\left(T\right)}+1}{1+\mathrm{sRC}}\left(\frac{\mathrm{DCR}\left(T\right)*\mathrm{RT}}{1+\mathrm{sRT}*\mathrm{CT}}\right)\left(\frac{{\mathrm{IL}}_{\mathrm{TOT}}}{\mathrm{RSEN}}\right)& \left(7\right)\end{array}$
where the load current IL_TOT represents the total inductor current of all phases. If the resistor RT is a NTC (negative temperature coefficient) resistor configured to achieve a constant value KT when multiplied by DCR(T) according to the following equation (8):
DCR(T)*RT=KT  (8)
and if RT and CT are according to the following equations (9) and (10):

[0029] $\begin{array}{cc}\mathrm{RT}*\mathrm{CT}=\frac{L}{\mathrm{DCR}\left(T\right)},& \left(9\right)\\ \mathrm{CT}=\frac{L}{\mathrm{KT}}& \left(10\right)\end{array}$
then V_ISEN can be determined according to the following equation (11):

[0030] $\begin{array}{cc}\mathrm{V\_ISEN}=\frac{\mathrm{KT}}{1+\mathrm{sRC}}\left(\frac{{\mathrm{IL}}_{\mathrm{TOT}}}{\mathrm{RSEN}}\right)& \left(11\right)\end{array}$
CT is selected and RT is configured to meet these conditions. It is noted that the notation “CT” with respect to the capacitor of the RC circuit 307 does not have a temperature dependency but is coupled with RT, which does have the desired temperature dependency. The corrected sense current ISEN_COR may be determined according to the following equation (12):

[0031] $\begin{array}{cc}{\mathrm{ISEN}}_{\mathrm{COR}}=\frac{\mathrm{V\_ISEN}}{\left(\frac{R}{1+\mathrm{sRC}}\right)}=\frac{\mathrm{KT}}{1+\mathrm{sRC}}\left(\frac{{\mathrm{IL}}_{\mathrm{TOT}}}{\mathrm{RSEN}}\right)\left(\frac{1+\mathrm{sRC}}{R}\right)=\frac{\mathrm{KT}*{\mathrm{IL}}_{\mathrm{TOT}}}{R*\mathrm{RSEN}}& \left(12\right)\end{array}$

[0032] In this manner, the output sense current ISEN_COR is not temperature dependent and thus provides both AC and DC temperature compensation. The resistor RT is generally positioned to have substantially the same temperature as the output inductors L, such as being placed adjacent to or sufficiently close to the output inductors L. It is desired that the filter time constant for the SEN pin be equal to or greater than the L/R time constant. Since the time constant RT*CT is equal to L/DCR(T), V_ISEN voltage is used as the sense signal. In this manner, only one extra pin and one RC circuit is needed for this scheme. In one embodiment, the sensed phase current signals of each of the phases, or ISEN1, ISEN2, . . . , ISENN, are used for current balance.

[0033] FIG. 4 is a schematic diagram of a voltage regulator circuit 400 including a current sense scheme according to another embodiment to provide both AC and DC temperature compensation. The regulator circuit 400 includes a controller 401 and is similar to the regulator circuit 100 except that the external sense resistors RSEN are replaced with internal sense resistors RSEN1 for each phase. The amplifiers 303, the devices 305 and the current mirrors 308 are provided within the controller 401 and operate in similar manner to provide sense currents ISEN1-ISENN from the phases to an internal summing node 309. In this case, however, the summing node 309 is not externally provided but instead is coupled to one end of another internal sense resistor RSEN2, having its other end coupled to RGND. A total sense current ISEN flows through RSEN2 to develop a voltage V_ISEN which is buffered through a separate buffer 403. The summing node 309 is coupled to the input of the buffer 403, having its output providing the voltage V_ISEN to the SEN pin of the controller 401. In this case, the sense signal is a voltage signal rather than a current signal. The external RC circuit 307 is replaced with another external RC circuit 407, which is similar to the RC circuit 307 including RT and CT coupled in parallel between a correction node COR1 and RGND. The RC circuit 407, however, includes another resistor RA coupled between the SEN pin and the correction node COR1. The correction node COR1 is coupled to a COR1 pin of the controller 401, which internally provides a signal COR1 to the non-inverting input of the amplifier 311. The RC circuit 109 is coupled to the COR2 pin which is internally coupled to the inverting input and output of the amplifier 311 in substantially the same manner as previously described. The amplifier 311 controls the device 313 in the same manner for developing the corrected sense current ISEN_COR through the mirror circuit 315 in substantially similar manner.

[0034] The sense current ISEN1 of the first phase circuit is according to the following equation (13):

[0035] $\begin{array}{cc}\mathrm{ISEN}1=\frac{V2}{\mathrm{RSEN}1}=\frac{\mathrm{sL}+\mathrm{DCR}\left(T\right)}{1+\mathrm{sRC}}\left(\frac{\mathrm{IL}}{\mathrm{RSEN}1}\right)& \left(13\right)\end{array}$
The voltage V_ISEN is determined according to the following equation (14):

[0036] $\begin{array}{cc}\mathrm{V\_ISEN}=\mathrm{ISEN}*\mathrm{RSEN}2=\sum _{i=0}^N\mathrm{ISENi}*\mathrm{RSEN}2& \left(14\right)\end{array}$
where equation (14) may be rewritten according to the following equation (15):

[0037] $\begin{array}{cc}\mathrm{V\_ISEN}=\frac{\mathrm{sL}+\mathrm{DCR}\left(T\right)}{1+\mathrm{sRC}}\left(\frac{\mathrm{RSEN}2}{\mathrm{RSEN}1}\right){\mathrm{IL}}_{\mathrm{TOT}}& \left(15\right)\end{array}$
The voltage of COR1 is according to the following equation (16):

[0038] $\begin{array}{cc}\mathrm{COR}1=\frac{\mathrm{RT}}{\mathrm{RA}+\mathrm{RT}}\left(\frac{1}{1+\mathrm{sCT}\left(\frac{\mathrm{RA}*\mathrm{RT}}{\mathrm{RA}+\mathrm{RT}}\right)}\right)\mathrm{V\_ISEN}& \left(16\right)\end{array}$
which may be rewritten according to the following equation (17):

[0039] $\begin{array}{cc}\mathrm{COR}1=\frac{\mathrm{sL}+\mathrm{DCR}\left(T\right)}{1+\mathrm{sRC}}\left(\frac{\mathrm{RSEN}2}{\mathrm{RSEN}1}\right)\left(\frac{\mathrm{RT}}{\mathrm{RA}+\mathrm{RT}}\right)\left(\frac{1}{1+\mathrm{sCT}\frac{\mathrm{RA}*\mathrm{RT}}{\mathrm{RA}+\mathrm{RT}}}\right){\mathrm{IL}}_{\mathrm{TOT}}& \left(17\right)\end{array}$
The corrected sense current ISEN_COR may be written according to the following equation (18):

[0040] $\begin{array}{cc}{\mathrm{ISEN}}_{\mathrm{COR}}=\frac{\mathrm{COR}1}{\left(\frac{R}{1+\mathrm{sCR}}\right)}& \left(18\right)\end{array}$
which may be written according to the following equation (19):

[0041] $\begin{array}{cc}{\mathrm{ISEN}}_{\mathrm{COR}}=\frac{\mathrm{sL}+\mathrm{DCR}\left(T\right)}{1+\mathrm{sCR}}\left(\frac{\mathrm{RSEN}2}{\mathrm{RSEN}2}\right)\left(\frac{\mathrm{RT}}{\mathrm{RA}+\mathrm{RT}}\right)\left(\frac{1}{1+\mathrm{sCT}\left(\frac{\mathrm{RA}*\mathrm{RT}}{\mathrm{RA}+\mathrm{RT}}\right)}\right)\left(\frac{1+\mathrm{sCR}}{R}\right){\mathrm{IL}}_{\mathrm{TOT}}& \left(19\right)\end{array}$
which is rewritten according to the following equation (20):

[0042] $\begin{array}{cc}{\mathrm{ISEN}}_{\mathrm{COR}}=\frac{\left(\frac{\mathrm{sL}}{\mathrm{DCR}\left(T\right)}\right)+1}{1+\mathrm{sCR}}\left(\frac{\mathrm{RSEN}2}{\mathrm{RSEN}1}\right)\left(\frac{\mathrm{RT}}{\mathrm{RA}+\mathrm{RT}}\right)\left(\frac{\mathrm{DCR}\left(T\right)}{1+\mathrm{sCT}\left(\frac{\mathrm{RA}*\mathrm{RT}}{\mathrm{RA}+\mathrm{RT}}\right)}\right)\left(\frac{1+\mathrm{sCR}}{R}\right){\mathrm{IL}}_{\mathrm{TOT}}& \left(20\right)\end{array}$
If DCR(T)*RT/(RA+RT)=KT, where KT is a constant, and if CT=L/(RA*KT), then ISEN_COR may be written according to the following equation (21):

[0043] $\begin{array}{cc}{\mathrm{ISEN}}_{\mathrm{COR}}=\frac{\mathrm{RSEN}2}{\mathrm{RSEN}1}\left(\frac{\mathrm{KT}}{R}\right){\mathrm{IL}}_{\mathrm{TOT}}& \left(21\right)\end{array}$
RA and CT are selected and RT is configured to meet these conditions. It is noted that the timing constant for the RC circuit 407 as compared to the timing constant of the output inductor L may be written according to the following equation (22):

[0044] $\begin{array}{cc}\frac{L}{\mathrm{DCR}\left(T\right)}=\frac{\mathrm{RA}*\mathrm{RT}*\mathrm{CT}}{\left(\mathrm{RA}+\mathrm{RT}\right)}& \left(22\right)\end{array}$

[0045] In a similar manner as with the voltage regulator circuit 300, the output sense current ISEN_COR for the regulator circuit 400 is not temperature dependent and provides both AC and DC temperature compensation.

[0046] FIG. 5 is a schematic diagram of a portion of a voltage regulator circuit 500 including a current sense scheme according to yet another embodiment to provide both AC and DC temperature compensation. The regulator circuit 500 includes a controller 501 which uses a voltage adder and internal current sense resistors RM. The regulator circuit 500 is shown with N phases in which the controller senses the voltage across the capacitor C via corresponding ISi+/− pins in a similar manner as previously described. Each ISi+/− signal pair is provided through a pair of matching resistors RM to respective inputs of a differential amplifier 503, having an output coupled to a SEN pin. The SEN pin is externally coupled to the RC circuit 407 in substantially the same manner as for the controller 401. The RC circuit 407 develops a signal COR1 provided through the COR1 pin of the controller 501 to the non-inverting input of the amplifier 311. The RC circuit 109 is coupled to the COR2 pin in the same manner, where COR2 is provided to the inverting input of the amplifier 311. The device 313 and the current mirror 315 are coupled to the amplifier 311 to develop the corrected sense current ISEN_COR in similar manner as previously described.

[0047] It is assumed that the output inductors L of each phase are substantially similar, that each has equivalent DCR and inductance L and carries an inductor current IL, that the resistors RM are matched and that the summing amplifier 503 has a gain of 1. The voltage V_ISEN at the output of the amplifier 503 (summing node) and provided on the SEN pin is determined according to the following equation (23):

[0048] $\begin{array}{cc}\mathrm{V\_ISEN}=\sum ^{}\mathrm{IL}\left(\frac{\mathrm{DCR}\left(T\right)+\mathrm{sL}}{\mathrm{sCR}+1}\right)& \left(23\right)\end{array}$
The voltage on the COR1 pin is determined according to the following equation (24):

[0049] $\begin{array}{cc}\mathrm{COR}1=\mathrm{V\_ISEN}\left(\frac{\mathrm{RT}}{\mathrm{RA}+\mathrm{RT}}\right)\left(\frac{1}{s\left(\mathrm{RT}//\mathrm{RA}\right)\mathrm{CT}+1}\right)& \left(24\right)\end{array}$
in which the notation “//” is shorthand for the parallel equivalent of the indicated resistors RA and RT. Equation (24) is rewritten by substituting in equation (23) according to the following equation (25):

[0050] $\begin{array}{cc}\mathrm{COR}1=\frac{\mathrm{RT}}{\mathrm{RA}+\mathrm{RT}}\left(\frac{\mathrm{RT}}{\mathrm{RA}+\mathrm{RT}}\right)\left(\frac{1}{s\left(\mathrm{RT}//\mathrm{RA}\right)\mathrm{CT}+1}\right)\sum _{}^{}\mathrm{IL}\left(\frac{\mathrm{DCR}\left(T\right)+\mathrm{sL}}{\mathrm{sCR}+1}\right)& \left(25\right)\end{array}$
The DC gain of equation (25), denoted COR1_DC, is obtained by assuming that s is zero according to the following equation (26):

[0051] $\begin{array}{cc}\mathrm{COR}{1}_{\mathrm{DC}}=\frac{\mathrm{RT}*\mathrm{DCR}\left(T\right)}{\mathrm{RA}+\mathrm{RT}}\sum _{}^{}\mathrm{IL}& \left(26\right)\end{array}$
Again, RT and RA are configured such that DCR(T)*RT/(RA+RT)=KT, where KT is a constant. Furthermore, the RC time constant formed by CT and (RT//RA) is according to the following equation (27):

[0052] $\begin{array}{cc}\frac{\mathrm{RT}}{\mathrm{RA}+\mathrm{RT}}\mathrm{RA}*\mathrm{CT}=\frac{\mathrm{KT}}{\mathrm{DCR}\left(T\right)}\mathrm{RA}*\mathrm{CT}& \left(27\right)\end{array}$

[0053] In one embodiment, RA is a 1% tolerance resistor and CT is a 10% tolerance capacitor. The time constant can be made to matching the time constant of inductor L/DCR(T) as both of them are inversely proportional to DCR(T), which changes with temperature. The impedance on the inverse side of the amplifier 311 is according to the following equation (28):

[0054] $\begin{array}{cc}\frac{R/\mathrm{sC}}{R+1/\mathrm{sC}}=\frac{R}{\mathrm{sCR}+1}& \left(28\right)\end{array}$
The corrected sense current ISEN_COR is equal to the COR1 voltage divided by this impedance, which is determined according to the following equation (29):

[0055] $\begin{array}{cc}{\mathrm{ISEN}}_{\mathrm{COR}}=\frac{\mathrm{RT}}{\mathrm{RA}+\mathrm{RT}}\left(\frac{1}{s\left(\mathrm{RT}//\mathrm{RA}\right)\mathrm{CT}+1}\right)\left(\frac{\mathrm{sCR}+1}{R}\right)\sum _{}^{}\mathrm{IL}\left(\frac{\mathrm{DCR}\left(T\right)+\mathrm{sL}}{\mathrm{sCR}+1}\right)& \left(29\right)\end{array}$
which is rewritten according to the following equation (30):

[0056] $\begin{array}{cc}{\mathrm{ISEN}}_{\mathrm{COR}}=\mathrm{KT}\left(\frac{1}{s\frac{\mathrm{KT}}{\mathrm{DCR}\left(T\right)}\mathrm{CT}+1}\right)\left(\frac{1}{R}\right)\left(1+\frac{L}{\mathrm{DCR}\left(T\right)}\right)\sum _{}^{}\mathrm{IL}=\frac{\mathrm{KT}}{R}\sum _{}^{}\mathrm{IL}& \left(30\right)\end{array}$

[0057] In this manner, ISEN_COR is proportional to the inductor current summation with all the other time constants and DCR(T) temperature variations canceled. In one embodiment, the voltage between ISi+ and ISi− of each phase is used for current balance purposes. The controller 501 provides the benefit of having only one summing amplifier for all phases rather than a separate amplifier for each phase.

[0058] As may be used herein, the terms “substantially” and “approximately” provides an industry-accepted tolerance for its corresponding term and/or relativity between items. Such an industry-accepted tolerance ranges from less than one percent to fifty percent and corresponds to, but is not limited to, component values, integrated circuit process variations, temperature variations, rise and fall times, and/or thermal noise. Such relativity between items ranges from a difference of a few percent to magnitude differences. As may also be used herein, the term(s) “coupled to” and/or “coupling” includes direct coupling between items and/or indirect coupling between items via an intervening item (e.g., an item includes, but is not limited to, a component, an element, a circuit, and/or a module) where, for indirect coupling, the intervening item does not modify the information of a signal but may adjust its current level, voltage level, and/or power level. As may further be used herein, inferred coupling (i.e., where one element is coupled to another element by inference) includes direct and indirect coupling between two items in the same manner as “coupled to”. As may even further be used herein, the term “operable to” indicates that an item includes one or more of power connections, input(s), output(s), etc., to perform one or more its corresponding functions and may further include inferred coupling to one or more other items. As may still further be used herein, the term “associated with”, includes direct and/or indirect coupling of separate items and/or one item being embedded within another item. As may be used herein, the term “compares favorably”, indicates that a comparison between two or more items, signals, etc., provides a desired relationship. For example, when the desired relationship is that signal 1 has a greater magnitude than signal 2, a favorable comparison may be achieved when the magnitude of signal 1 is greater than that of signal 2 or when the magnitude of signal 2 is less than that of signal 1.

[0059] Although the present invention has been described in considerable detail with reference to certain preferred versions thereof, other versions and variations are possible and contemplated. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiments as a basis for designing or modifying other structures for providing out the same purposes of the present invention without departing from the spirit and scope of the invention as defined by the following claims.