Manufacturing method of a silicon carbide semiconductor device

[0001] This application claims priority from Japanese application Serial No. 2007-133597, filed on May 21, 2007, the contents of which are incorporated herein by reference in their entirety.

[0002] A. Field of the Invention

[0003] The present invention relates to a manufacturing method of a silicon carbide (hereinafter abbreviated as SiC) semiconductor device for high breakdown voltage and large current uses. More specifically, the invention relates to a manufacturing method including a dry etching method for forming a mesa groove having a junction end portion surface which surrounds an active portion where a main current flows in a power semiconductor device such as a diode or a MOSFET which uses a SiC semiconductor substrate.

[0004] B. Description of the Related Art

[0005] Power MOSFETs, IGBTs, etc. are known and widely used as silicon (hereinafter referred to as Si) power semiconductor devices which are used in inverters and for AC power control and other purposes. However, in recent years, Si as a semiconductor material has come to be used frequently in ranges that are close to its material property limits in terms of power device semiconductor characteristics. As a result, SiC, which is a semiconductor material whose material property limits are higher than those of Si has attracted a great deal of attention. SiC materials (in particular, the one having a 4H—SiC crystal form) have features that the dielectric breakdown electric field is one-order higher, the band gap is 2.9 times larger, the thermal conductivity is 3.2 times higher, and the temperature of transition to an intrinsic semiconductor is 3 to 4 times higher than those of Si. Therefore, the material properties of SiC, the limits of which are higher than those of Si, are exercised greatly, particularly when SiC is used as a substrate material for a power device. As a result, it is expected that power devices having an SiC substrate can satisfy both high breakdown voltage and low on-resistance, which is difficult for Si devices because of a tradeoff relationship between these two parameters. As such, in recent years, many approaches to implementing such SiC devices as products have come to be made.

[0006] Techniques relating to manufacturing methods, including etching for putting into practical use or implementing as products power devices using wide-band-gap semiconductor materials such as SiC, are disclosed in JP-A-2005-322811 (corresponding to US 2005/0250336 A1), JP-A-2005-56868 (corresponding to which WO 02/099870 A1), and JP-A-2006-228901. JP-A-2005-322811 relates to a dry etching mask and discloses a manufacturing method which can increase the adhesion of an etching mask to a GaN semiconductor substrate and enables high-accuracy groove formation. JP-A-2005-56868 discloses a method to prevent occurrence of micro-trenches (which tend to cause reduction in breakdown voltage) in dry-etching a SiC substrate in which dry etching using an Al mask and full-surface dry etching (which is performed after removing the Al mask) are combined. JP-A-2006-228901 has a statement to the effect that to prevent reduction in breakdown voltage at top corners of trenches formed in a SiC substrate by etching, trench top corners are rounded by performing isotropic etching after increasing the thickness of oxide films formed on the trench bottoms.

[0007] However, actual manufacturing processes for putting into practice or implementing as products SiC power devices still have many and various problems to be solved. One specific problem resides in a process of forming, for example, a trench for a trench gate or a mesa groove having a junction end portion surface which surrounds a device active portion by dry etching in manufacturing a device using a SiC substrate. That is, in dry etching a SiC substrate, if kinds of gases used for the etching and various etching conditions (ICP (induction-coupled plasma) power, bias power, gas pressure, and gas flow rates) are not controlled properly, an etching failure occurs because an etching mask material is stuck to an etching subject material (formation of micro-masks) during dry etching of mesa grooves or micro-trenches are formed (i.e., small grooves are formed by excessive etching at bottom corners of recesses formed by the etching). This is problematic for the following reason. If such micro-masks or micro-trenches are formed, acute-angled portions tend to be formed in the etching surfaces of a mesa groove. If such acute-angled portions are formed in the surfaces of a mesa groove, an electric field is concentrated which makes any resulting device prone to dielectric breakdown. That is, the breakdown voltage of the device cannot be increased.

[0008] Usually, in manufacture of a high-breakdown-voltage device using a SiC substrate or some other substrate such as a Si substrate, the etching surface is required to be as free of acute-angled portions as possible when a mesa groove is formed by etching. To this end, a method is employed in which the mesa groove formation in a SiC substrate by dry etching is done in two stages having different sets of etching conditions to suppress generation of micro-trenches as mentioned above. For example, etching is performed at a relatively high etching rate at the first stage and then the etching rate is lowered to obtain a smooth final etched shape. However, this two-stage etching method has problems because the process is complex and there still remains some doubt about its reproducibility.

[0009] The present invention is directed to overcoming or at least reducing the effects of one or more of the problems set forth above.

[0010] The present invention has been made in view of the above problems, and an object of the invention is therefore to provide a manufacturing method of a silicon carbide semiconductor device including a dry etching method which is necessary in manufacturing a high-breakdown-voltage device and which can increase the breakdown voltage by suppressing generation of micro-masks and thereby produce smoothly curved etched surfaces in forming a mesa groove which is as deep as 10 μm or more and reaches a SiC substrate past a drift layer.

[0011] In the invention, an Al film and a Ni film are laid on an SiC substrate in this order and wet-etched, whereby a two-layer etching mask is formed in which a Ni film portion overhangs an Al film portion. When a mesa groove is formed by dry etching using this etching mask, the rate of incidence of ions of an etching gas on the groove side walls and their vicinities is lowered by virtue of the Ni film portion which overhangs the Al film portion. This reduces the degree of a phenomenon that deep sub-trenches tend to be formed locally in the groove side walls and in their vicinities, and thereby provides an advantage that the breakdown voltage is increased.

[0012] The invention provides a manufacturing method of a silicon carbide semiconductor device, comprising a dry etching step of forming, by dry etching, a mesa groove as deep as 10 μm or more in a silicon carbide semiconductor substrate using, as an etching mask patterned on the silicon carbide semiconductor substrate, a metal lamination film formed by an Al film and a Ni film in such a manner that a Ni film portion covers and overhangs an Al film portion and also using an etching gas which is an induction-coupled plasma obtained by ionizing a mixed gas of SF₆, O₂, and Ar gases, under conditions that the SF₆, O₂, and Ar gases are caused to flow at flow rates of 26% to 35%, 7.5% to 8.5%, and 58% to 65% with respect to a total gas flow rate, respectively, temperature of the silicon carbide semiconductor substrate is 30° C.±5° C., and pressure is kept at 3 Pa or more.

[0013] It is preferable that the induction-coupled plasma power and bias power of the dry etching apparatus using the induction-coupled plasma be 500 W and 15 W, respectively.

[0014] It also is preferable that the total thickness of the metal lamination film be 0.5 to 2 μm. It is also preferable that the metal lamination film be formed by forming the Al film at a thickness of 30% to 50% of the total thickness and then forming the Ni film on the Al film at a thickness of 50% to 70% of the total thickness.

[0015] It is preferable that the metal lamination film be pattern-formed with a wet etching liquid which etches the Al film at a higher etching rate than the Ni film.

[0016] Furthermore, it is preferable that the wet etching liquid be a mixed acid including phosphoric acid, nitric acid, and acetic acid.

[0017] As such the invention can provide a manufacturing method of a silicon carbide semiconductor device including a dry etching method which is necessary in manufacturing a high-breakdown-voltage device and which can increase the breakdown voltage by suppressing generation of micro-masks and thereby producing smoothly curved etched surfaces in forming a mesa groove which is as deep as 10 μm or more and reaches a SiC substrate past a drift layer.

[0024] A manufacturing method of a silicon carbide semiconductor device according to an embodiment of the invention will be hereinafter described in detail with reference to the drawings. Various changes and modifications to the following embodiment are possible without departing from the spirit and scope of the invention.

[0025] FIG. 1 is a sectional view of a silicon carbide wafer and shows a photoresist pattern. FIG. 2 is a sectional view of the silicon carbide wafer and shows a pattern of an etching mask which is a metal lamination film. FIGS. 3A through 3F are sectional views of silicon carbide wafers and shows respective etched shapes corresponding to Etching Condition 1 to Etching Condition 6, respectively. FIGS. 4A through 4C are sectional views of silicon carbide wafers which show respective etched shapes corresponding to Etching Condition 7 to Etching Condition 9, respectively. FIG. 5 is a sectional view of the silicon carbide wafer which is formed with mesa grooves.

[0026] As shown in FIG. 1, n⁺ single crystal SiC substrate 1 having a (0001) Si surface as the major surface is prepared and n-type layer (n-type drift layer) 7 of 10 μm in thickness and 1×10¹⁶ cm⁻³ in impurity concentration is epitaxially grown thereon by thermal CVD. Alternatively, n-type drift layer 7 may be formed by implanting ions into an epitaxial layer. P-type base layer 5 and n⁺ source regions 6 are formed on n-type drift layer 7 by epitaxial growth or ion implantation, whereby a silicon carbide (SiC) wafer is obtained. P-type base layer 5 is 1 μm in thickness and 1×10¹⁷ cm⁻³ in impurity concentration, and n⁺ source regions 6 are 0.5 μm in junction depth and 1×10¹⁹ cm⁻³ in impurity concentration. Although any hexagonal-system silicon carbide materials can be used as the single crystal SiC substrate 1, 4H—SiC is preferable in terms of mobility. It is preferable to use nitrogen (N) as the donor of n-type drift layer 7 and n⁺ source regions 6 and to use aluminum (Al) as the acceptor of p-type base layer 5.

[0027] MOSFETs, IGBTs, etc. can be produced by forming trenches having a depth of about 2 μm from the surfaces of n⁺ source regions 6 by known dry etching or the like and forming a gate insulating film, gate electrodes, etc. The MOS structure may be a planar gate structure in which the gate insulating film is formed parallel with the wafer major surface, instead of the above trench gate structure. Since these MOS structures are well known, they will not be described further here. A diode may be formed by not forming n⁺ source region 6.

[0028] Al film 2 and Ni film 3 are sequentially formed as an etching mask by sputtering, for example, on the SiC wafer in which p-type base layer 5 and n⁺ source regions 6 have been formed in the above-described manner. These metal films may be formed by known methods. The use of Ni film 3 is preferable because it provides a large selective etching ratio with SiC substrate 1 and hence the side walls of mesa grooves 8 can be made almost perpendicular to the surface of the SiC wafer in forming mesa grooves 8 by dry etching. Al film 2 is used because it is etched at a higher rate than Ni film 3 and hence lamination structures are formed in such a manner that Ni film portions 3 overhang Al film portions 2 (see FIG. 2) when a mask pattern is formed. The thicknesses of Al film 2 and Ni film 3 are 0.4 μm and 0.6 μm, respectively.

[0029] After the SiC wafer is cleaned, it is dried at 120° C. for 10 minutes. Then, after the SiC wafer is left as it is in an atmosphere such as a vapor of hexamethyldisilazane (OAP: trade name of Tokyo Ohka Kogyo Co., Ltd.) to increase the degree of adhesion to a photoresist, photoresist 4 is applied to Ni film 3. Then, photoresist 4 is soft-baked by processing the SiC wafer in an oven at 100° C. for 10 minutes. After the baking, exposure is performed with an ultraviolet exposing apparatus using an etching mask having an arbitrary pattern. After the exposure, unnecessary portions of photoresist 4 are removed by development and hard baking is performed at 125° C. for 20 minutes, whereby a photoresist pattern as shown in the sectional view of FIG. 1 is formed. In this state, the thickness of photoresist 4 is about 2.5 μm. There are no problems even if photoresist 4 has other thickness values, as long as it is thick enough to withstand wet etching.

[0030] After the formation of the photoresist pattern, the SiC wafer is immersed in an etching liquid which is a mixed acid of phosphoric acid, nitric acid, and acetic acid capable of pattern-etching Ni film 3 and Al film 2 (the etching liquid is heated to a prescribed temperature), whereby Ni film 3 and Al film 2 are wet-etched. As a result, an etching mask which is a Ni film/Al film lamination layer in which Ni film portions overhang Al film portions is formed as shown in the sectional view of FIG. 2. The shape that Ni film portions overhang Al film portions is formed as shown in the sectional view of FIG. 2 because, as mentioned above, the mixed acid etches Al film 2 faster than Ni film 3. After the wet etching of Ni film 3 and Al film 2, photoresist 4 is removed by immersing the SiC wafer into a photoresist stripper. Openings of the etching mask are formed so as to surround the active portions of devices on the wafer, respectively. Line width errors produced by the wet etching, which is not high in accuracy, do not cause serious problems because the width (area) of mesa grooves 8 (having junction end portion surfaces which influence the device breakdown voltage) to be formed by dry etching is greater than that of trench gate grooves. After the formation of the etching mask, water cleaning and drying are performed and the SiC (or SiC film) is subjected to dry etching in the following manner.

[0031] ICP power and bias power are applied to the SiC wafer at a pressure of 3 Pa in a mixed gas atmosphere including SF₆, O₂, and Ar, whereby mesa grooves 8 are formed which reach SiC substrate 1 penetrating through p-type base layer 5 and n-type drift layer 7. The depth of mesa grooves 8 should be 10 μm or more in the case where the thickness of n-type drift layer 7 is 10 μm. This is to maintain a high breakdown voltage. That is, mesa grooves 8 should be deep enough (i.e., deeper than the low-impurity-concentration n⁻ drift layer 7) to prevent depletion layers (which develop when a voltage close to a breakdown voltage is applied) from reaching the bottoms of mesa grooves 8. It is necessary that mesa grooves 8 be filled later with a proper insulating material 9 such as polyimide, SiO₂, silicon nitride, or polysilicon. One method for cutting the wafer into chips of respective devices is that wide mesa grooves 8 are formed and the wafer is cut at the centers of the mesa grooves. In another cutting method, in which cutting lines are set on the SiC wafer surface, ring-like mesa grooves 8 are formed for respective devices on the wafer.

[0032] Next, experiments will be described that were carried out to determine optimum etching conditions for forming mesa grooves 8 to maintain a high breakdown voltage by dry-etching the above-described SiC wafer. This will be described especially in detail because the optimum etching conditions for forming mesa grooves 8 for maintaining a high breakdown voltage is an important feature of the invention.

[0033] Experiments in which the conditions of the dry etching of the SiC (or SiC film) were varied were carried out after the water cleaning and drying of the SiC wafer bearing the etching mask. More specifically, to determine optimum etching conditions, an ICP plasma dry etching apparatus and an SF₆/O₂/Ar mixed gas were used and the etching conditions were varied in the following manner. Table 1 shows selective ratios (i.e., ratios of the SiC etching rate to the etching mask etching rate) which were obtained when the etching conditions (kinds of gases, flow rates, ICP power, bias power, pressure, and temperature) were varied.

[0034]

	TABLE 1
		ICP	Bias
	Gases and flow rates	power	power	Pressure	Temperature	Selective
	(sccm)	(W)	(W)	(Pa)	(° C.)	ratio
Condition 1	SF6/O2/Ar = 30/10/0	500	50	3	30	9.7
Condition 2	SF6/O2/Ar = 30/10/0	500	15	3	30	16.7
Condition 3	SF6/O2/Ar = 10/3.3/25	500	50	3	30	x
Condition 4	SF6/O2/Ar = 10/3.3/25	500	50	3	75	x
Condition 5	SF6/O2/Ar = 10/3.3/25	500	50	0.5	75	x
Condition 6	SF6/O2/Ar = 10/3.3/25	500	15	0.5	75	11

[0035] In Table 1, mark “x ” in the column of selective ratio means that the mask could not bear the etching and the SiC substrate surface under the mask was etched.

[0036] FIGS. 3A to 3F (sectional views) show etched shapes corresponding to Condition 1 to Condition 6, respectively. When the bias power was reduced from 50 W to 15 W (from Condition 1 to Condition 2 in Table 1), the selective ratio was improved from 9.7 to 16.7. As shown in FIGS. 3A and 3B, micro-trenches (sub-trenches) 11 at the bottoms of side walls 10 of mesa grooves 8 decreased. Reference symbol 3 denotes Ni film 3 of the etching mask.

[0037] When the flow rates of SF₆ and O₂ were lowered from 30 sccm and 10 sccm to 10 sccm and 3.3 sccm with their ratio approximately fixed at 3:1 and Ar was added (flow rate: 25 sccm) (from Condition 1 to Condition 3), as shown in FIG. 3C, the etching mask could not bear the etching and SiC substrate surface 12 under the mask was etched down and the height of side walls 10 was shortened. However, as seen from FIGS. 3A, 3B and 3C, micro-trenches 11 were smaller than in the case of Condition 1 (the bias power remained the same (50 W)). This is an advantage of the addition of Ar.

[0038] It is seen from Condition 3 and Condition 4 that the change in the temperature at the time of etching did not cause any improvement in the selective ratio (also see FIGS. 3C and 3D).

[0039] No improvement was found in the selective ratio either by lowering the pressure from 3 Pa to 0.5 Pa (from Condition 4 to Condition 5). SiC substrate surface 12 under the mask was etched down and the height of side walls 10 was shortened as shown FIGS. 3D and 3E.

[0040] When the bias power was lowered from 50 W to 15 W in the state that Ar was added and the temperature was kept at 75° C. (from Condition 5 to Condition 6), the selective ratio was improved, whereby the etching rate of the etching mask was lowered and SiC substrate surface 12 under the mask was not etched down as shown in FIGS. 3E and 3F.

[0041] The above results show that as for the etching conditions it is proper to add Ar, not to increase the temperature from 30° C., not to lower the pressure from 3 Pa, and set the bias power low (15 W).

[0042] In the two-layer (Ni film 3/Al film 2) etching mask according to the embodiment, it is intended to suppress occurrence of micro-trenches 11 by utilizing the overhanging of Ni film portions 3. However, when the SiC wafer is etched to form 10-μm-deep grooves, for example, the overhanging of Ni film portions 3 is meaningless unless a selective ratio is realized which can leave Ni film portions 3. In the embodiment, since Ni film 3 is 0.6 μm in thickness, calculation shows that the selective ratio should be 16.6 or more.

[0043] Next, a description will be made of a study that was made to adjust the SF₆/O₂ ratio to improve the selective etching ratio. Table 2 shows selective ratios that were obtained when the SF₆/O₂ ratio was varied.

[0044]

	TABLE 2
		ICP	Bias
	Gases and flow rates	power	power	Pressure	Temperature	Selective
	(sccm)	(W)	(W)	(Pa)	(° C.)	ratio
Condition 7	SF6/O2/Ar = 6/3.3/25	500	15	3	30	14.6
Condition 8	SF6/O2/Ar = 10/3.3/25	500	15	3	30	17.7
Condition 9	SF6/O2/Ar = 15/3.3/25	500	15	3	30	19.5

[0045] FIGS. 4A to 4C (sectional views) show etched shapes corresponding to Condition 7 to Condition 9 of Table 2, respectively. It is seen from Table 2 that the selective ratio can be improved to 19.5 by increasing the SF₆/O₂ ratio to 15:3.3 (Condition 9). Calculation shows that with this selective ratio Ni film portions 3 remain even if the SiC wafer is etched to form 11.7-μm-deep grooves. It is seen from FIG. 4C (sectional view) that the intersecting portion 14 of etched side wall 10 and bottom 13 is made much gentler by virtue of the SF₆/O₂ ratio 15:3.3 in condition 9. Overhanging portions of the etching mask remained surely, and it seems that these overhanging portions caused ions that contribute to the etching of end portions to be less prone to concentrate there. Even Condition 8 can be employed because the selective ratio was increased from the above-mentioned value of 16.6 to 17.7.

[0046] It is concluded from the above results that employing the two-layer (Ni film 3/Al film 2) etching mask having the overhanging Ni film portions 3 and using Etching Conditions 8 and 9 in Table 2 make it possible to form, in an SiC wafer, mesa grooves 8 which are free of micro-masks or micro-trenches 11 and have smooth etched shapes (without acute-angled portions). In manufacturing a silicon carbide semiconductor device, these etching conditions reduce the degree of electric field concentration at junction end portion surfaces of mesa grooves 8 which determine the breakdown voltage of the device. An optimum manufacturing method capable of increasing the breakdown voltage can thus be realized.

[0047] Thus, a method of manufacturing a silicon carbide semiconductor device has been described according to the present invention. Many modifications and variations may be made to the techniques and structures described and illustrated herein without departing from the spirit and scope of the invention. Accordingly, it should be understood that the methods described herein are illustrative only and are not limiting upon the scope of the invention.