Universal error control coding scheme for digital communication and data storage systems

[0001] This application is a divisional of U.S. patent application Ser. No. 11/492,383 filed Jul. 25, 2006.

[0002] This invention relates to error control coding of data in data communication and data storage systems.

[0003] It is a problem in the field of data communication and data storage systems that the demand for efficiency and reliability is driven by the need to exchange and store the vast amounts of data generated in modern information societies. The transmission of information across a wired or wireless communication channel, as well as the storage and retrieval of information using a magnetic or optical medium, are processes where the information is always subject to corruption by distortion and noise. Signals conveying the information can be so contaminated in this process that errors occur in the recovered information. Since the distortions and noise encountered over any communication channel or storage medium cannot be completely eliminated, these systems must be designed to control the effect of the errors so that the information transmitted or stored can be reliably recovered.

[0004] In 1948, Shannon's landmark channel coding theorem showed that, with proper channel encoding and decoding, the probability of errors induced by a noisy transmission channel or storage medium can be reduced to any desired level, provided that the information transmission rate is less than an upper limit defined by the channel, called the channel capacity. Channel encoding allows a certain level of errors caused by the noise to be correctable by the channel decoder and is often referred to as forward error-correction coding (FEC). The need for powerful forward error-correction coding techniques having a high level of error correction capability, as well as efficient encoding and decoding implementations, has become critically important in the design of modern digital communications and storage systems.

[0005] Because of their many similarities, typical digital communications and data storage systems can be specified in terms of the block diagram shown in FIG. 1. A sequence of information bits is transmitted across a channel or written into a storage medium. The channel encoder transforms this sequence of information bits into an encoded bit sequence or code sequence to enable the correction of errors. This is done by introducing redundant bits into the code sequence in a controlled manner. There are basically two classes of channel codes: block codes and convolutional codes. In a block code, the sequence of information bits is divided into successive non-overlapping blocks of length k, and each information block is encoded independently into a codeword of length n bits, resulting in a code rate of r=k/n. The set of 2^k codewords, each of blocklength equal to n, is called an (n,k) block code. Block codes that have been widely used include Golay, BCH, and Reed-Solomon codes, as well as low density parity check (LDPC) codes. In a convolutional code, the encoder also processes a sequence of successive blocks of k information bits and produces a code sequence consisting of a sequence of successive n-bit code blocks. However, each encoded block of n bits depends not only on the corresponding k-bit information block occurring at the same time but also on m previous information blocks. Hence, the encoder has a memory of order m, which is often specified in terms of a code constraint length K=m+1. The code rate is again equal to r=k/n. Thus, the encoder maps the entire sequence of information bits into a single code sequence. While the sequence of information bits to be encoded may be of variable length in convolutional coding, it can also be set to a fixed length. In the latter case, the convolutional code can be viewed as a (possibly long blocklength) block code. A rate −½ and constraint length K=7 convolutional code has been used in many applications, as well as the more powerful turbo coding method using either parallel or serial concatenated convolutional codes.

[0006] Discrete symbols are generally not suitable for transmission over a wireline or wireless channel or for recording directly on a magnetic or optical storage medium. The role of the digital modulator (or data recording unit for storage) is to transfer the code sequence at the output of the channel encoder into a sequence of analog waveforms of some fixed duration T that is suitable for transmission (or for recording). Single carrier modulation waveforms are often used, such as binary phase shift keying (BPSK) and quadrature phase shift keying (QPSK), which modulate only the phase of a sinusoidal carrier, and quadrature amplitude modulation (QAM), which modulates both the carrier amplitude and phase. The digital modulator may also be used to map code sequences into multi-carrier modulation waveforms. In these systems, an Inverse Fast Fourier Transform (IFFT) processing is performed by the digital modulator to generate the transmission waveforms. In optical fiber networks, transmission waveforms are generated at the digital modulator by modulating a laser light source on and off. In storage applications, the recording unit generates the binary signal waveforms that are written on the storage medium.

[0007] The waveform output of the digital modulator enters the physical transmission channel for propagation to the receiver (or recorded on the storage medium). Waveforms transmitted across either wireline or wireless channels are subject to corruption in a variety of ways, for example, by thermal noise, inter-symbol interference, crosstalk interference from other transmissions, multi-path propagation, signal fading, etc. Storage media can be contaminated by media surface defects as well as dust particles, and may also experience intersymbol interference and recording noise at high storage bit densities. These disturbances introduced by the transmission channel (or storage medium) cause errors, which must be corrected by the channel decoder using the error correction capability of the forward error-correction code.

[0008] The channel decoder must employ digital processing to be able to efficiently correct errors introduced by the channel in an optimum manner to minimize the probability of decoding error. The role of the digital demodulator (or storage data reading unit) is to convert the analog waveform output of the channel (or storage medium) into a digital form that can be processed by the channel decoder. A hard-decision demodulator attempts to directly reconstruct the transmitted code sequence and outputs this reconstructed code sequence to the channel decoder. A soft-decision demodulator outputs a quantitized digital version of a reconstructed transmitted modulation signal to the channel decoder. This reconstruction process can be designed to maximize signal-to-noise ratio and may include signal equalization to remove intersymbol interference introduced by the channel (or storage medium). In multi-carrier systems, such as orthogonal frequency division multiplexed (OFDM) and discrete multi-tone (DMT) modulations, the digital demodulator also includes the Fast Fourier Transform (FFT) processing that inverts the IFFT operation performed at the digital modulator. The corresponding channel decoders use either hard-decision or soft-decision decoding algorithms to correct channel errors. Soft-decision channel decoding generally performs better than their hard-decision counterpart, however, often at the cost of much higher implementation complexity.

[0009] The block diagram in FIG. 1 represents a one-way communication system in which information transmission occurs strictly in one direction, from transmitter to receiver. In this instance, error control can only be provided through the use of forward error-correction coding. In some cases, a communication system can support a two-way exchange of information between transmitter and receiver across the channel. Error control in a two-way communication system can use an error detection and retransmission scheme called automatic repeat request (ARQ). In an automatic repeat request system, a request is sent by the receiver to the transmitter to repeat the transmission of the information when errors are detected. The major advantage of automatic repeat request systems over forward error-correction coding is that error detection requires much simpler decoding complexity than error correction at the channel decoder. Also, an automatic repeat request system adapts to channel conditions in the sense that information is only re-transmitted when channel errors occur. However, high channel error rates can result in a large number of retransmissions and, therefore, low system information throughput rates. A better alternative is a hybrid combination of an automatic repeat request system with forward error-correction coding so that frequent channel error patterns are correctable by the forward error-correction code and retransmissions only occur for infrequent severe channel error conditions when the forward error-correction coding error correction capability is exceeded.

[0010] From the viewpoint of the communications system designer, the communications channel consists of the part of the system that cannot be changed. The choice of digital modulation waveforms is often fixed and governed by system bandwidth and power specifications. The choice of digital demodulators, whether soft-decision or hard-decision, is often fixed by practical system complexity constraints. For example, while soft-decision demodulation is viable for asymmetrical digital subscriber loop (ADSL) systems, it cannot be economically implemented for high-speed 10 Gbps OC-192 SONET networks. Consequently, the digital modulator (or data recording unit), the physical channel (or storage medium), and the digital demodulator (or data reading unit) can be combined to form a fixed coding channel for the purposes of designing forward error-correction coding systems. This is shown in the block diagram of FIG. 2. Design of forward error-correction coding systems involves only the design of the channel code and the channel encoder and channel decoder blocks. This model given by the block diagram of FIG. 2 also applies to the design and implementation of network layer coding methods.

[0011] The performance of a coded communication system is generally measured in terms of its probability of decoding error and its coding gain over an uncoded system that transmits information at the same rate. There are two types of error probabilities that are commonly considered to evaluate forward error-correction coding methods. One is the block error rate (BLER), which is the probability that a block of information bits is decoded in error at the output of the channel decoder. The other is the bit error rate (BER), which is the probability that an information bit is decoded in error at the output of the channel decoder. Forward error-correction coding methods are designed in coded communication systems to minimize these error probabilities to the extent possible under the constraints of signal power, bandwidth, and implementation complexity. The error probability is often measured as a function of a receiver signal-to-noise ratio, which is often taken to be equal to E_b/N₀, which is the ratio of the signal energy per information bit to the noise power spectral density level at the input of the digital demodulator. The other performance measure that is frequently used to measure the performance of a forward error-correction coding method is the coding gain, which is defined to be the reduction in E_b/N₀ required to achieve a specified error probability level (BER or BLER) for a coded communication system compared to an uncoded system. Coding gain, which is usually expressed in terms of decibels (dBs), measures the power efficiency gain of a forward error-correction coded communication system compared to an uncoded system.

[0012] The design of a forward error-correction coding method for a coded digital communication (or data storage) system often requires a trade-off between the following factors:

• • [0013] 1. Coding Gain—Although higher coding gains result in better error probability performance, this may come at a cost of higher data bandwidth expansion from a lower code rate and/or higher implementation complexity using longer codes.
  • [0014] 2. Code Rate—Lower code rates can result in higher coding gains at the cost of higher transmission bandwidth requirements.
  • [0015] 3. Implementation Complexity—Implementation complexity generally increases when longer blocklength block codes and convolutional codes with larger encoding memory are used to increase coding gain. Implementation complexity also increases when soft-decision decoding is used instead of hard-decision decoding to improve error probability performance.

[0016] Digital communication (data storage) systems often employ multiple forward error-correction coding methods to provide programmable error control configurations that balance some of the above-mentioned factors. The motivation for implementing multiple forward error-correction codes in wireline and wireless digital communications systems is to provide programmability to adapt to changing channel noise conditions. The multiple forward error-correction codes implemented in these systems can then be programmed to dynamically adapt to changing channel conditions. Some magnetic hard disk read channel integrated circuit (IC) vendors have marketed products that incorporate multiple forward error-correction codes with different coding rates. In this application, the programmable forward error-correction coding allows hard disk manufacturers to optimize data integrity for particular disk drive configurations. In another application, larger magnetic hard disk sector sizes can accommodate forward error-correction codes with longer blocklengths to provide higher coding gains. Programmable forward error-correction coding read channel ICs for this application enables a tradeoff between data integrity and disk drive sector size storage efficiency.

[0017] However, there is presently a lack of a system that provides adjustable code rates and coding gains that is capable of being dynamically adjusted to adapt to changing channel (storage medium) conditions. In addition, there is presently a lack of a system in which a single encoder and a single decoder can be used to implement all the forward error-correction codes of different code rates.

[0018] The above-described problems are solved and a technical advance achieved by the present universal forward error-correction coding system, which provides adjustable code rates and coding gains to greatly benefit the design of many modern digital communications (data storage) systems. This universal forward error-correction coding system is capable of being adjusted dynamically to provide code rates and coding gains that adapt to changing channel (storage medium) conditions. The channel encoding and decoding methods in the present universal forward error-correction coding system are universal such that a single encoder and a single decoder can be used to implement all the forward error-correction codes of different code rates. This serves to greatly reduce the complexity, chip area, and chip power consumption in IC implementations. This universal forward error-correction coding system also includes a novel systematic code generation procedure that has the capability of generating many classes of codes that provide the best balance between coding gain performance and implementation complexity. In particular, an innovative low complexity channel encoder implementation is applicable to all codes generated by this systematic method. Codes generated by this systematic method are also shown to be consistently superior using a variety of hard-decision and soft-decision decoding algorithms of different implementation complexities.

Binary Linear Block Codes

[0047] In a binary block code, an information bit stream is first segmented into message blocks of fixed length consisting of k information bits. Denote each message block as u=(u₀, . . . u_k−1). The channel encoder maps each of the 2^k message blocks into a unique codeword which consists of a block of n bits, where k<n. Denote each codeword as v=(v₀, . . . v_n−1). The set of 2^k codewords v is called a binary block code of blocklength n and of code rate equal to k/n. A binary block code C with 2^k codewords v, each of blocklength n, is called a (n,k) linear code if the set of codewords v forms a k-dimensional subspace of the vector space of all the n-tuples over the binary Galois field GF(2). Since the code C is of dimension k, it is possible to find k linearly independent vectors g₀, . . . , g_k−1 that serve as a basis for this subspace. That is, every codeword v is a linear combination of these k basis vectors:
v=u₀g₀+u₁g₁+ . . . +u_k−1g_k−1  (1)

[0048] Each of these basis vectors g_i is also a codeword in C. The k×n matrix G, which is formed using these linearly independent vectors g₀, . . . , g_k−1 as its rows:

[0049] $\begin{array}{cc}G=\left[\begin{array}{c}{g}_0\\ ⋮\\ g_{k-1}\end{array}\right]& \left(2\right)\end{array}$
is called a generator matrix, G, for this code C. This generator matrix G can then be used to specify the mapping given by equation (1) from message blocks, u, to codewords, v, as follows:
v=uG  (3)

[0050] So the set of 2^k codewords v in code C is the row space of the generator matrix G. Since the set of basis vectors g₀, . . . , g_k−1 is not unique, the generator matrix G for a code C is also not unique. Different generator matrices G for a given linear code C has the same set of codewords v, but different mappings between the message blocks u and the codewords v.

[0051] For any k×n generator matrix G, there is a (n−k)×n matrix H with (n−k) linearly independent rows such that:
GH^T=0  (4)
That is, every vector in the row space of the generator matrix G is orthogonal to the rows of H. So an n-dimensional vector v is a codeword in code C if and only if:
vH^T=0  (5)
or, equivalently, if and only if the n-dimensional vector v is in the null space of the matrix H. This matrix H is called a parity check matrix of the code C. Since generator matrices G are not unique for a linear code C, parity check matrices H are also not unique. So a linear code C can be specified either in terms of the row space of a generator matrix G or in terms of the null space of a corresponding parity-check matrix H. The channel encoder can be implemented to carry out the mapping defined by (3) using the generator matrix G. The parity-check matrix H plays a major role in the implementation of various decoding algorithms for the channel decoder. These issues will be discussed below. The linear code C is called a systematic code if its generator matrix G is of the following form:
G=[IP]  (6)
where I is a k×k identity matrix and P is a k×(n−k) matrix. Using (3), it can be seen that the codewords v of a systematic code have the property that their first k components are the k information bits of the message block: v₀=u₀, v₁=u₁, . . . , v_k−1=u_k−1. Systematic codes have a decoding advantage of directly yielding the message block when a codeword has been decoded.

[0052] Finally, the weight of a codeword v is equal to the number of “1s” in the codeword v. The error correction capability of a block code can be specified in terms of the minimum distance of the code C. For linear codes, the code minimum distance is equal to the minimum weight over all possible non-zero codewords.

Binary Low Density Parity Check Codes

[0053] This universal forward error-correction coding system is based on using Low Density Parity Check (LDPC) codes of a particular quasi-cyclic structure for generating the codes and implementing the corresponding universal channel encoder and decoder for these codes. Low Density Parity Check codes can achieve a coding performance very close to the theoretically achievable performance quantified by the Shannon limit. The binary Low Density Parity Check codes are (n,k) linear codes that are usually specified in terms of their parity check matrices H. In particular, a binary (γ, ρ)-regular Low Density Parity Check code is defined as the null space of a sparse parity check matrix H with the following structural properties: (1) each row consists of ρ “1s”; (2) each column consists of γ “1s”; (3) the number of “1s” in common between any two columns, denoted by λ, is no greater than one; that is, λ=0 or 1; and (4) both ρ and γ are small compared with the blocklength n of the code and the number of rows in H. Properties (1) and (2) say that the parity check matrix H has constant row and column weights ρ and γ, respectively. Property (3) also implies that no two rows have more than one “1” in common, and is often referred to as the Row-Column (RC) constraint. Property (4) implies that the matrix H has a small density of “1s”; hence, it is a sparse matrix. For this reason, the code specified by H is called a Low Density Parity Check code. The rows of H are not necessarily linearly independent over GF(2), so H is not necessarily of full rank. In these cases, the dimension of the code must be determined by determining the rank of H which is equal to n−k. An example of a parity check matrix H for a binary (2,3)-regular Low Density Parity Check code is:

• • [0054] Consider the parity check matrix:

[0055] $H=\left[\begin{array}{ccc}100& 100& 100\\ 010& 010& 010\\ 001& 001& 001\\ 100& 010& 001\\ 010& 001& 100\\ 001& 100& 010\end{array}\right]$

• • [0056]  The rank of this parity check matrix H=5. So the null space of H is a (9,4) linear code.

[0057] If all the columns (or all the rows) of the parity check matrix H do not have the same weight, the code is called an irregular Low Density Parity Check code. The lack of structure in irregular Low Density Parity Check codes results in complex encoder implementations, which reduces their desirability for many applications.

Binary Quasi-Cyclic Low Density Parity Check Codes

[0058] Cyclic codes have the property that the cyclic shift of any codeword by any number of bit positions results in another codeword. This property allows easy implementations of channel encoders and syndrome calculations for channel decoding by employing shift registers with feedback connections. Many important cyclic codes, including BCH codes and Reed Solomon codes, have a rich algebraic structure that allows for practically implementable channel decoding algorithms as well. Quasi-Cyclic (QC) codes only have a partial cyclic structure that still allows for encoder implementations with simple shift registers. In particular, a Quasi-Cyclic code is a linear code for which shifting a codeword a fixed number n₀≠1 (or a multiple of n₀) of bit positions results in another codeword. A Quasi-Cyclic code also has another form. A codeword can be divided into n₀ sections of the same length. Simultaneously, cyclically shifting all of the n₀ sections one place to the right (or to the left) results in another codeword. We shall use a class of binary Quasi-Cyclic Low Density Parity Check (QC-Low Density Parity Check) codes as the basis for our universal coding scheme in which the parity check matrix H of each code in the class is given as an array of sparse circulant matrices of the same dimension. Binary Quasi-Cyclic Low Density Parity Check codes generated this way are of the second form. Well-designed Quasi-Cyclic Low Density Parity Check codes have been shown to perform as well as computer-generated random Low Density Parity Check codes, regular or irregular in terms of bit-error performance, block-error performance, rate of decoding convergence, and error-floor, collectively. Therefore, in practical applications, they are strong competitors to the random Low Density Parity Check codes due to their simple encoding, fast decoding convergence, and low error-floors. These codes also have advantages in VLSI IC decoder implementations due to their cyclic symmetry which results in simple regular wiring and modular structure. This universal forward error-correction coding system has made use of these properties to devise universal coding schemes with flexible code rates and coding gains as well as universal encoder and universal decoder implementations.

[0059] A circulant is a square matrix (with binary elements) in which each row is the cyclic shift (one place to the right) of the row above it and the first row is the cyclic shift of the last row. For such a circulant, each column is the downward cyclic shift of the column on its left and the first column is the cyclic shift of the last column. The row and column weights of a circulant are the same, say w. For simplicity, we say that the circulant has weight w. If w=1, then the circulant is a permutation matrix, called a circulant permutation matrix. For a circulant, the set of columns (reading from the top down) is the same as the set of rows (reading from right to left). A circulant is completely characterized by its first row (or first column) which is called the generator of the circulant.

[0060] All the rows of a b×b circulant A over GF(2) are linearly independent if its rank is equal to b. If its rank r_A is less than b, then any consecutive r_A rows (or columns) of A may be regarded as being linearly independent and the other b−r_A rows (or columns) are linearly dependent. This is due to the cyclic structure of A. For simplicity, we always take the first (or the last) r_A rows (or columns) of A as the independent rows (or columns). A binary Quasi-Cyclic Low Density Parity Check code is given by the null space of an array of sparse circulants of the same size. For two positive integers c and t with c≦t, consider the following c×t array of b×b circulants over GF(2):

[0061] $\begin{array}{cc}{H}_{\mathrm{qc}}=\left[\begin{array}{cccc}{A}_{1,1}& A_{1,2}& \dots & A_{1,t}\\ A_{2,1}& A_{2,2}& \dots & A_{2,t}\\ ⋮& ⋮& \ddots & ⋮\\ A_{c,1}& A_{c,2}& \dots & A_{c,t}\end{array}\right]& \left(7\right)\end{array}$
which has the following structural properties: (1) the weight of each circulant A_i,j is small compared to its size b; and (2) no two rows (or two columns) of H_qc have more than one 1-component in common (the Row-Column constraint). Property (1) simply implies that each circulant in H_qc is a sparse circulant; hence, H_qc is a sparse matrix. Property (2), the Row-Column constraint, ensures that there are no four 1-entries at the four corners of a rectangle in H_qc. Then the null space of H_qc gives a binary Quasi-Cyclic Low Density Parity Check code C_qc of length n=tb. If all the circulants in H_qc have the same weight w, then H_qc has constant column weight cw and constant row weight tw. In this case, C_qc is a regular Quasi-Cyclic Low Density Parity Check code. The Row-Column constraint on H_qc ensures that there are cw check-sums orthogonal on every code bit; hence, the minimum distance of C_qc is at least cw+1. If the weight distribution of the circulants in H_qc results in multiple column weights or multiple row weights in H_qc, then C_qc is an irregular Quasi-Cyclic Low Density Parity Check code.

[0062] The structure of a binary Quasi-Cyclic Low Density Parity Check code can be viewed from its parity-check matrix in circulant form given by equation (7). Based on this form, every codeword v in C_qc can be divided into t sections, v=(v₁, v₂, . . . , v_t), and each section v_j consists of b consecutive components of v. For 1≦j≦t, the b components of the j-th section v_j correspond to the b columns of the j-th column of circulants of H_qc. For 0≦l≦b, let v_j^(l) denote the vector obtained by cyclically shifting each of the b components of the j-th section v_j to the right l places. It is clear that v_j⁽⁰⁾=v_j^(b)=v_j. We call v_j^(l) the l-th (right) cyclic-shift of v_j. Then it follows from the circulant structure of H_qc that the vector v*=(v₁^(l), v₂^(l), . . . , v_t^(l)) is also a codeword in C_qc. This says that the code C_qc has sectionized cyclic structure. If the parity-check matrix H_qc consists of a single circulant or a single column of circulants, then C_qc is a cyclic code. Therefore, binary cyclic Low Density Parity Check codes form a subclass of binary Quasi-Cyclic Low Density Parity Check codes.

Universal Coding Based on Families of Structurally Compatible Binary Quasi-Cyclic-Low Density Parity Check Codes

[0063] This section describes a family of binary Quasi-Cyclic Low Density Parity Check codes of various blocklengths, rates, and error performances that can be obtained from a base Quasi-Cyclic Low Density Parity Check code. These codes are suitable for implementing coding schemes that can adapt to varying communications channel (storage medium) conditions and varying data transmission rates. This family of binary Quasi-Cyclic Low Density Parity Check codes are structurally compatible so that a single universal encoder can be implemented that can adapt to serve as an encoder for every code in this family. Each code in this family can also be decoded with one universal decoder. Therefore, this new universal forward error-correction coding system gives a method to realize and instrument a flexible universal coding scheme that can adapt to data rate and error performance requirements.

[0064] The family of structurally compatible binary Quasi-Cyclic Low Density Parity Check codes is obtained as follows. Consider first a binary Quasi-Cyclic Low Density Parity Check code C(c,t) defined as the null space of a parity check matrix H_qc(c, t), which is a c×t array of b×b circulants over GF(2) of the form given by equation (7). This is a code with blocklength equal to tb, which we shall refer to as the base code. To obtain the rest of the codes in this family, choose any sequence of m distinct pairs of positive integers, (c_i, t_i), with 1≦i≦m, such that 1≦c₁≦c₂≦ . . . ≦c_m≦c, and 1≦t₁≦t₂≦ . . . ≦t_m≦t. Let H_qc(c_i, t_i) be the c_i×t_i subarray of the base array H_qc(c,t) of circulants obtained by deleting the last t−t_i columns and the last c−c_i rows of b×b circulant matrices. Therefore, each matrix H_qc(c_i, t_i) is a c_i×t_i array of b×b circulant matrices. Let C(c_i, t_i) be the null space of the matrix H_qc(c_i, t_i). It then follows from the definition given in the last section that C(c_i, t_i) is a binary Quasi-Cyclic Low Density Parity Check code of blocklength equal to t_ib. Therefore, C(c,t), C(c₁, t₁), C(c₂, t₂), . . . , C(c_m, t_m) form a family of m+1 binary Quasi-Cyclic Low Density Parity Check codes that has single universal encoder and universal decoder implementations.

[0065] The following simple example illustrates the universal coding concept when m=1 to obtain a family of two codes.

• • [0066] Consider a case where c=3 and t=4 and c₁=2 and t₁=3. Suppose the parity check matrix of the base code is the following 3×4 array of 3×3 circulants:

[0067] $H\left(3,4\right)=\left[\begin{array}{cccccccccccccccccc}0& 0& 1& & & 0& 0& 0& & & 1& 0& 0& & & 0& 1& 0\\ 1& 0& 0& & & 0& 0& 0& & & 0& 1& 0& & & 0& 0& 1\\ 0& 1& 0& & & 0& 0& 0& & & 0& 0& 1& & & 1& 0& 0\\ & & & & & & & & & & & & & & & & & \\ 0& 1& 0& & & 1& 0& 0& & & 0& 0& 0& & & 0& 0& 1\\ 0& 0& 1& & & 0& 1& 0& & & 0& 0& 0& & & 1& 0& 0\\ 1& 0& 0& & & 0& 0& 1& & & 0& 0& 0& & & 0& 1& 0\\ & & & & & & & & & & & & & & & & & \\ 1& 0& 0& & & 0& 1& 0& & & 0& 0& 1& & & 0& 0& 0\\ 0& 1& 0& & & 0& 0& 1& & & 1& 0& 0& & & 0& 0& 0\\ 0& 0& 1& & & 1& 0& 0& & & 0& 1& 0& & & 0& 0& 0\end{array}\right]$

• • [0068]  and the parity check matrix derived by deleting the last row and the last column of 3×3 circulants from H(3,4) is:

[0069] $H\left(2,3\right)=\left[\begin{array}{ccccccccccccc}0& 0& 1& & & 0& 0& 0& & & 1& 0& 0\\ 1& 0& 0& & & 0& 0& 0& & & 0& 1& 0\\ 0& 1& 0& & & 0& 0& 0& & & 0& 0& 1\\ & & & & & & & & & & & & \\ 0& 1& 0& & & 1& 0& 0& & & 0& 0& 0\\ 0& 0& 1& & & 0& 1& 0& & & 0& 0& 0\\ 1& 0& 0& & & 0& 0& 1& & & 0& 0& 0\end{array}\right]$

• • [0070]  Both binary Quasi-Cyclic Low Density Parity Check codes are regular with equal column and row weights. The parity check matrix H(3,4) has rank 7, so its null space is a (12,5) code C(3,4) of code rate equal to 5/12, while the parity check matrix H(2,3) is of full rank 6, so its null space is a (9,3) code C(2,3) of code rate equal to ⅓.
    Efficient Channel Encoder Implementations for Binary Quasi-Cyclic Low Density Parity Check Codes

[0071] Although a binary Quasi-Cyclic Low Density Parity Check code is specified as the null space of a parity check matrix H_qc of the form given by equation (7), the corresponding generator matrix G_qc must be determined to implement channel encoders for these codes that employ equation (3) to map message blocks u into codewords v. This universal forward error-correction coding system includes the description of a general approach to determine a generator matrix in systematic-circulant form (similar to equation (6)), as well as the development of digital circuit architectures for implementing the corresponding encoders. Various encoding circuit architectures are designed to allow a tradeoff between encoder circuit complexity in terms of chip area and encoding speed for VLSI IC implementations. We present two methods for constructing the generator matrices of binary Quasi-Cyclic Low Density Parity Check codes in systematic-circulant form from their parity-check matrices for two different cases. The first, Case I, is when the rank r_H of the parity-check matrix H_qc given by equation (7) is equal to the number cb of rows of H_qc and there exists a c×c subarray in H_qc with rank r_H. The second case, Case II, is when r_H<cb, or when r_H=cb and there does not exist a c×c subarray in H_qc with rank r_H.

Single-Stage Encoder Implementation for Case I

[0072] Consider a binary Quasi-Cyclic Low Density Parity Check code C_qc given by the null space of a parity-check matrix H_qc of the form given by equation (7). Suppose the rank r_H of H_qc is equal to cb. We assume that the columns of circulants of H_qc are arranged in such a way that the rank of the following c×c subarray of H_qc:

[0073] $\begin{array}{cc}D=\left[\begin{array}{cccc}{A}_{1,t-c+1}& A_{1,t-c+2}& \dots & A_{1,t}\\ A_{2,t-c+1}& A_{2,t-c+2}& \dots & A_{2,t}\\ ⋮& ⋮& \ddots & ⋮\\ A_{c,t-c+1}& A_{c,t-c+2}& \dots & A_{c,t}\end{array}\right],& \left(8\right)\end{array}$
is equal to cb, the same as the rank r_H of H_qc. We also assume that the first (t−c)b columns of H_qc correspond to the (t−c)b information bits. Then the desired generator matrix of the code C_qc has the following systematic form (similar to equation (6)):

[0074] $\begin{array}{cc}\begin{array}{c}{G}_{\mathrm{qc}}=\left[\begin{array}{c}{G}_1\\ G_2\\ ⋮\\ G_{t-c}\end{array}\right]\\ =\left[\begin{array}{cccccccc}I& O& \dots & O& G_{1,1}& G_{1,2}& \dots & G_{1,c}\\ O& I& \dots & O& G_{2,1}& G_{2,2}& \dots & G_{2,c}\\ ⋮& ⋮& \ddots & ⋮& ⋮& ⋮& \ddots & ⋮\\ O& O& \dots & I& G_{t-c,1}& G_{t-c,2}& \dots & G_{t-c,c}\end{array}\right]\\ =\left[I_{\left(t-c\right)b}P\right],\end{array}& \left(9\right)\end{array}$
where I is a b×b identity matrix, O is a b×b zero matrix, and G_i,j with 1≦i≦t−c and 1≦j≦c is a b×b circulant. The generator matrix G_qc with the form given by equation (9) is said to be in systematic-circulant (SC) form. It consists of two parts, the left part I_(t−c)b and the right part P. The left part I_(t−c)b of G_qc with (t−c)(b×b)-dimension identity matrices on its main diagonal is actually a (t−c)b×(t−c)b identity matrix, and the right part P of G_qc is a (t−c)×c array of b×b circulants. In coding theory, the right part P of G_qc is called the P-matrix that corresponds to the parity-check section of a codeword in systematic form. We say that G_qc is in systematic-circulant form because its P-matrix is an array of circulants. The systematic-circulant form allows us to encode a binary Quasi-Cyclic Low Density Parity Check code with simple shift-register circuits.

[0075] The necessary and sufficient condition for G_qc to be a generator matrix of C_qc is that H_qcG_qc^T=[O], where [O] is a cb×(t−c)b zero matrix. For 1≦i≦t−c and 1≦j≦c, let g_i,j be the generator of the circulant G_i,j. Once we know the set of the g_i,j's, we can form the set of all of the circulants G_i,j's of G_qc. Therefore, G_qc is completely characterized by a set of c(t−c) circulant generators, which are called the generators of the code C_qc.

[0076] Let u=(1 0 . . . 0) be the unit b-tuple with a “1” at the first position and let 0=(0 0 . . . 0) be the all-zero b-tuple. For 1≦i≦t−c, the first row of the submatrix G_i in equation (9) is
g_i=(0 . . . 0u0 . . . 0g_i,1g_i,2 . . . g_i,c),  (10)
where the unit b-tuple u is at the i-th position of g_i. Then, in order for G_qc to be a generator matrix of the code C_qc, we must have H_qcg^T=0 for 1≦i≦t−c. Let z_i=(g_i,1 g_i,2 . . . g_i,c) (be the last c sections of g_i) and M_i=[A_1,i^T . . . A_c,i^T]^T, (be the i-th column of circulants of H_qc). Then H_qcg^T=0 gives the following equality:
M_iu^T+Dz_i^T=0  (11)
Since D is a square matrix and has full rank, it is nonsingular and has an inverse D⁻¹. Then it follows from equation (11) that:
z_i^T=D⁻¹M_iU^T  (12)
Solving equation (12) for 1≦i≦t−c, we obtain z₁, z₂, . . . , z_t−c. From z₁, z₂, . . . , z_t−c, we obtain all the generators, g_i,j's, of the circulants in G_qc. Then G_qc can be readily constructed.

[0077] An encoding circuit for the code C_qc can be devised based on the generators of the circulants in the P-matrix of G_qc. Let a=(a₁, a₂, . . . , a_(t−c)b) be the information sequence of (t−c)b bits to be encoded. Divide this sequence into (t−c) sections of equal length, a=(a₁, a₂, . . . , a_(t−c)), where for 1≦i≦t−c, the i-th section a_i consists of b consecutive information bits, a_i=(a_(i−1)b+1, a_(i−1)b+2, . . . , a_ib). Then the codeword for the information sequence a is v=aG_qc, which has the following systematic form: v=(a, p₁, p₂, . . . , p_c), where for 1≦j≦c, p_j=(p_j,1,p_j,2, . . . , p_j,b) is a section of b parity-check bits. It follows from v=a G_qc that:

[0078] $\begin{array}{cc}{p}_j=\sum _{i=1}^{t-c}{a}_i{G}_{i,j}& \left(13\right)\end{array}$
for 1≦j≦c. For 0≦l≦b, let g_i,j^(l) be the l-th (right) cyclic shift of the generator g_i,j, with g_i,j⁽⁰⁾=g_i,j^(b)=g_i,j. Then for 1≦i≦t−c:
a_iG_i,j=a_(i−1)b+1g_i,j⁽⁰⁾+a_(i−1)b+2g_i,j⁽¹⁾+ . . . +a_ibg_i,j^(b−1).  (14)

[0079] It follows from equations (13) and (14) that the j-th parity check section p_j can be computed, step by step, as the information sequence a is shifted into the encoder. For 1≦k<t−c, at the k-th step, the accumulated sum, s_k,j=a₁G_1,j+a₂G_2,j+ . . . +a_kG_k,j is formed and stored in a register (called an accumulator). At the (k+1)-th step, the partial sum a_k+1G_k+1,j is computed from equation (14) and added to s_k,j to form the next accumulated sum s_k+1,j. At the end of (t−c)-th step, the accumulated sum s_t−c,j gives the j-th parity section p_j.

[0080] Based on the above encoding process and the expression given by equation (14), the j-th parity check section p_j can be formed with a Shift-Register-Adder-Accumulator circuit as shown in FIG. 3. At the beginning of the first step, g_1,j⁽⁰⁾=g_1,j is stored in the feedback shift-register B and the contents of the (accumulator) register A are set to zero. When the information bit a₁ is shifted into the encoder and the channel, the product a₁g_1,j⁽⁰⁾ is formed at the outputs of the AND-gates and is added to the contents stored in the register A (zero at this time). The sum is then stored in the register A. The feedback shift-register B is shifted once to the right. The new content in B is g_1,j⁽¹⁾. When the next information bit a₂ is shifted into the encoder, the product a₂g_1,j⁽¹⁾ is formed at the outputs of the AND-gates. This product is then added to the sum a₁g_1,j⁽⁰⁾ in the accumulator register A. The sum a₁g_1,j⁽⁰⁾+a₂g_1,j⁽¹⁾ is then stored in A. The above shift-add-store process continues. When the information bit a_b has been shifted into the encoder, register A stores the partial sum a₁G_1,j, which is the contribution to the parity section p_j from the information section a₁. At this time, the generator g_2,j of the circulant G_2,j is loaded into B. The shift-add-store process repeats. When the information section a₂ has been completely shifted into the encoder, register A contains the accumulated sum a₁G_1,j+a₂G_2,j, which is the contribution to the parity section p_j from the first two information sections, a₁ and a₂. The above process repeats until the entire information sequence a has been shifted into the encoder. At this time, register A contains the parity section p_j. To form c parity sections, we need c Shift-Register-Adder-Accumulator circuits, one for computing each parity section.

[0081] A block diagram for the entire Shift-Register-Adder-Accumulator based Quasi-Cyclic Low Density Parity Check serial encoder circuit is shown in FIG. 4. The information sequence a is encoded serially. All the c parity sections are formed at the same time in parallel and then shifted into the channel serially. The encoding circuit consists of c Shift-Register-Adder-Accumulator circuits with a total of 2cb flip-flops, cb AND-gates, and cb two-input XOR-gates (or modulo-2 adders). The encoding is accomplished in linear time with complexity linearly proportional to the number of parity check bits, cb of the code. The encoding is accomplished in (t−c)b clock cycles where (t−c)b is the length of the information sequence.

[0082] A Shift-Register-Adder-Accumulator based Quasi-Cyclic Low Density Parity Check parallel encoder circuit that completes encoding in cb clock cycles can be implemented with t−c feedback shift-registers, each with b flip-flops as shown in FIG. 5. All of the (t−c)b information bits are applied to the encoder in parallel. For 1≦i≦t−c and 1≦j≦c, let h_i,j be the first column of the circulant G_i,j. For 0≦l≦b, let h_i,j^(l) denote the l-th downward cyclic-shift of h_i,j. It is clear that h_i,j⁽⁰⁾=h_i,j^(b)=h_i,j. Then for 0≦l≦b, the l-th parity check bit p_j,l of the j-th parity section p_j is given by:
p_j,l=a₁h_1,j^(l−1)+a₂h_2,j^(l−1)+ . . . +a_t−ch_t−c,j^l−1).  (15)

[0083] From this expression given by equation (15), we see that p_j,l can be formed with (t−c)b two-input AND-gates and (t−c)b−1 two-input XOR-gates. The parity-check bits are generated serially, bit by bit, and one section at a time. For 1≦j≦c, in order to form the b parity bits of the j-th parity section p_j, the columns, h_1,j, . . . h_t−c,j are loaded into the t−c feedback shift-registers in parallel, and the first parity check bit p_j,1 of p_j is formed. Then cyclically shift these feedback shift-registers b−1 times to generate the other b−1 bits of p_j. With this implementation, encoding is completed in cb clock cycles. The total number of flip-flops required is equal to (t−c)b. The total number of XOR-gates required is equal to (t−c)b−1 and the total number of AND-gates required is equal to (t−c)b. The encoder complexity is linearly proportional to the number (t−c)b of information bits.

[0084] If all the parity sections are generated in parallel at the same time, a circuit that completes encoding in b clock cycles can be implemented. In this case, c(t−c) feedback shift-registers are needed. To start the encoding, all the first columns h_i,j's of the c(t−c) circulants in the P-matrix of G_qc are loaded into the feedback shift-registers in one clock cycle, and the first bits, p_1,1, p_2,1, . . . , p_c,1, of all the c parity sections are formed. Then by cyclically shifting all the feedback registers b−1 times in parallel, the other c(b−1) parity bits can be generated. In this way, the encoding is completed in b clock cycles. This implementation requires a total of c(t−c)b flip-flops, c((t−c)b−1) XOR-gates, and c(t−c)b AND-gates. Other encoding circuits with encoding speeds between cb or (t−c)b and b clock cycles can be implemented in an obvious similar manner. This offers a wide range of trade-offs between encoding speed and encoding complexity.

Two Stage Encoder Implementation for Case I

[0085] A two-stage encoder can also be implemented. Assume that the first b×b circulant A_1,t−c+1 of the array D given by equation (8) has rank b. This can be achieved by arranging the columns and rows of circulants of H_qc such that D has rank cb. It follows that D⁻¹ can be formed based on the circulants in D. It is known that the inverses, products, and sums of circulants are also circulants. Consequently, D⁻¹ is also a c×c array of b×b circulants.

[0086] $\begin{array}{cc}{D}^{-1}=\left[\begin{array}{ccc}{B}_{1,1}& \dots & B_{1,c}\\ ⋮& \ddots & ⋮\\ B_{c,1}& \dots & B_{c,c}\end{array}\right].& \left(16\right)\end{array}$

[0087] It follows from equations (10), (12), and (16) that for 1≦i≦t−c, we have:

[0088] $\begin{array}{cc}\left[\begin{array}{c}{G}_{i,1}^T\\ ⋮\\ G_{i,c}^T\end{array}\right]=\left[\begin{array}{ccc}{B}_{1,1}& \dots & B_{1,c}\\ ⋮& \ddots & ⋮\\ B_{c,1}& \dots & B_{c,c}\end{array}\right]·\left[\begin{array}{c}{B}_{1,i}\\ ⋮\\ B_{c,i}\end{array}\right]& \left(17\right)\end{array}$

[0089] For 1≦j≦c, let B_j=[B_j,1 . . . B_j,c] (denote the j-th row of D⁻¹). Multiplying out the right side of equation (17), we obtain the circulants G_i,j's in G_qc:

[0090] $\begin{array}{cc}{G}_{i,j}=M_i^T{B}_j^T=\sum _{k=1}^c{A}_{k,i}^T{B}_{j,k}^T,& \left(18\right)\end{array}$
for 1≦i≦t−c and 1≦j≦c. It follows from equations (9) and (18) that the generator matrix of the code C_qc can be put in the following SC-form:

[0091] $\begin{array}{cc}{G}_{\mathrm{qc}}=\left[\begin{array}{cccccccc}I& O& \dots & O& M_1^T{B}_1^T& M_1^T{B}_2^T& \dots & M_1^T{B}_c^T\\ ⋮& ⋮& \ddots & ⋮& ⋮& ⋮& \ddots & ⋮\\ O& O& \dots & I& M_{t-c}^T{B}_1^T& M_{t-c}^T{B}_2^T& \dots & M_{t-c}^T{B}_c^T\end{array}\right].& \left(19\right)\end{array}$

[0092] Again, let a=(a₁, a₂, . . . , a_t−c) be the information sequence to be encoded and v=(a, p₁, p₂, . . . , p_c) be its codeword. From equation (19) and v^T=G_qc^Ta^T, we find the j-th parity section p_j is:

[0093] $\begin{array}{cc}{p}_j^T=B_j\sum _{k=1}^{t-c}{M}_k{a}_k^T=B_j\left[\begin{array}{cccc}{M}_1& M_2& \dots & M_{t-c}\end{array}\right]a^T.& \left(20\right)\end{array}$

[0094] From equation (20), we can compute the j-th parity section p_j in two stages. First, we compute the cb-bit vector:
y^T=[M₁M₂ . . . M_t−c]a^T.  (21)
and then compute the j-th b-bit parity section p_j=B_jy^T. Divide the vectory into c sections, y=(y₁ y₂ . . . y_c) where for 1≦k≦c, the k-th section y_k=(y_k,1, y_k,2, . . . , y_k,b). Recall that for 1≦i≦t−c, M_i is the i-th column of circulants of H_qc given by equation (7). It follows from equation (21) that the k-th section y_k is given by:

[0095] $\begin{array}{cc}{y}_k^T=\sum _{i=1}^{t-c}{A}_{k,i}{a}_i^T.& \left(22\right)\end{array}$

[0096] For 1≦l≦b, let a_i^(l) denote the l-th (left) cyclic-shift of a_i (i.e., cyclically shifting each component of a_i to the left l places). From equation (22), we find that for 1≦l≦b, the l-th bit of y_k can be expressed as follows:

[0097] $\begin{array}{cc}{y}_{k,l}=\sum _{m=1}^{t-c}{q_{k,m}\left(a_m^{\left(l-1\right)}\right)}^T,& \left(23\right)\end{array}$
where q_k,i is the generator (first row) of the circulant A_k,i, and (a_i^(l−1))^T is the transpose of a_i^(l−1) for 1≦i≦t−c. In equation (23), we have expressed the bit y_k,l in terms of the cyclic-shifts of the information sections, a₁, a₂, . . . , a_t−c. Assume that the weight of each generator q_k,i is w. Then each term in equation (23) is the sum of w information bits. Based on equation (23), y can be formed with a circuit that is the upper part of the two-stage Quasi-Cyclic Low Density Parity Check encoder circuit shown in FIG. 6. All the t−c information sections are read into the t−c feedback shift-registers, FR₁, FR₂, . . . , FR_t−c, in one clock cycle. As soon as the information sections have been read into these feedback shift-registers, the bits y_1,1, y_2,1, . . . , y_c,1 are formed based on equation (23) and appear at the outputs of the c banks of XOR-gates. These bits are then shifted into c buffer registers, BR₁, BR₂, . . . , BR_c, as shown in the lower half of the circuit in FIG. 6. Cyclically shifting FR₁, FR₂, . . . , FR_t−c (shift to left) in parallel b−1 times, we generate all the other bits of y. At the end of the b-th clock cycle, all the c sections of y are stored in BR₁, BR₂, . . . , BR_c. This completes the first stage of encoding. This encoding stage requires a total of tb flip-flops and (t−c)w−1 XOR-gates.

[0098] The next stage is to form the c parity sections based on p_j^T=B_jy^T. This can be done using another c banks of XOR-gates. If the parity-check bits of each parity section are generated serially one bit at a time, we simply cyclically shift the buffer registers, BR₁, BR₂, . . . , BR_c, b times (left shift). The parity-check bits are generated in the same manner as the bits of y-vector. In this way, the number of XOR-gates required in each bank is of the order of cb/2 (we assume that the average row weight of each circulant in B_j is b/2). Consequently, the total number of XOR-gates used to form the parity bits is in the order of c² b/2, denoted O(c²b/2). This two-stage encoding circuit completes the encoding of (t−c)b information bits in 2b clock cycles, and requires a total of tb flip-flops and a total of O(c²b/2)+(t−c)w−1 XOR-gates. Note that the above two-stage encoding implementation is based on the circulants A_i,j in the c×c subarray D of the parity-check matrix H_qc.

[0099] If we generate two bits of each section y_k at a time and two parity bits of each parity section p_j at a time, we can complete the encoding in b clock cycles. In this case, the total number of XOR-gates required to form the cb parity bits is O(c²b)+2((t−c)w−1). The total number of flip-flops required is still equal to tb. Since each circulant in the parity check matrix H_qc is a sparse matrix and w is normally very small, say equal to 1 or 2, then 2((t−c)w−1) is much smaller than c²b; hence, the total number of XOR-gates used in the encoding circuit is O(c²b). In summary, for high-speed encoding, the complexity of the two-stage encoding is linearly proportional to the code length tb. Table I gives the speeds and complexities of various encoding circuits where the parity-check matrix H_qc given by equation (7) is a c×t array of b×b circulants A_i,j. Other encoding circuits can be implemented to provide various trade-offs between speed and complexity.

[0100]

TABLE I
	Encoding
	speed
	(Clock		Two-input	Two-input
Encoding scheme	cycles)	Flip-flops	XOR-gates	AND-gates
Shift Register Adder	(t − c) b	2cb	cb	cb
Accumulator (1)
Shift Register Adder	cb	(t − c) b	(t − c) b − 1	(t − c) b
Accumulator (2)
Two-stage	b	tb	O (c2b)	0

Encoder Implementations for Case II

[0101] In the last two sections, we considered the simple case for which the rank r_H of the parity-check matrix H_qc of a binary Quasi-Cyclic Low Density Parity Check code given by equation (7) is equal to the number of rows of H_qc, i.e., cb, and there exists a c×c subarray D in H_qc with rank r_H. Now we consider the case for which r_H<cb, or when r_H=cb, and there does not exist a c×c subarray D in H_qc with rank r_H. For this case, we first find the least number of columns of circulants in H_qc, say l with c≦l≦t, such that these l columns of circulants form a c×l subarray D* whose rank is equal to the rank r_H of H_qc. We permute the columns of circulants of H_qc to form a new c×t array H_qc* of circulants such that the last (or the right most) l columns of circulants of H_qc* form the array D*. Let:

[0102] $\begin{array}{cc}{D}^{*}=\left[\begin{array}{cccc}{A}_{1,t-l+1}& A_{1,t-l+2}& \dots & A_{1,t}\\ A_{2,t-l+1}& A_{2,t-l+2}& \dots & A_{2,t}\\ ⋮& ⋮& \ddots & ⋮\\ A_{c,t-l+1}& A_{c,t-l+2}& \dots & A_{c,t}\end{array}\right].& \left(24\right)\end{array}$
Then the desired generator matrix corresponding to the parity check matrix H_qc* is a (tb−r_H)×tb matrix and has the following form:

[0103] $\begin{array}{cc}{G}_{\mathrm{qc}}^{*}=\left[\frac{G}{Q}\right],& \left(25\right)\end{array}$
which consists of two submatrices G and Q. The G submatrix is a (t−l)×t array of the following form:

[0104] $\begin{array}{cc}G=\left[\begin{array}{ccccccc}I& O& \dots & O& G_{1,1}& \dots & G_{1,l}\\ O& I& \dots & O& G_{2,1}& \dots & G_{2,l}\\ ⋮& ⋮& \ddots & ⋮& ⋮& \ddots & ⋮\\ O& O& \square & I& G_{t-l,1}& \dots & G_{t-l,l}\end{array}\right],& \left(26\right)\end{array}$
where I is a b×b identity matrix, O is a b×b zero matrix, and G_i,j is a b×b circulant for 1≦i≦t−l and 1≦j≦1. The matrix G is in SC-form and can be obtained by solving equation (11) by setting the lb−r_H linearly dependent elements in z_i=(g_i,1 g_i,2 . . . g_i,l) to zeros with 1≦i≦t−l (these elements correspond to the linearly dependent columns of D*), where g_i,j is the generator of circulant G_i,j with 1≦j≦l.

[0105] The submatrix Q of G_qc* is an (lb−r_H)×tb matrix whose rows are linearly independent and also linearly independent of the rows of the submatrix G of G_qc*. For G_qc* to be a generator matrix of the code C_qc that is the null space of H_qc*, Q must satisfy the condition H_qc*Q^T=[O] where [O] is a cb×(lb−r_H) zero matrix. To obtain the Q submatrix of G_qc*, let d₁, d₂, . . . , d_l be the number of linearly dependent columns in the 1st, 2nd, . . . , l-th columns of circulants in D* respectively, so that

[0106] $\sum _{i=1}^l{d}_i=\mathrm{lb}-r_H.$
Due to the cyclic structure of circulants described above, the last b−d_i columns of the i-th column of circulants in D* can be regarded as being the linearly independent columns. Then the first d₁, d₂, . . . , d_l columns of the 1st, 2nd, . . . , l-th columns of circulants of D* are linearly dependent columns. Let:

[0107] $\begin{array}{cc}Q=\left[\begin{array}{cccccccc}{O}_{1,1}& O_{1,2}& \dots & O_{1,t-l}& Q_{1,1}& Q_{1,2}& \dots & Q_{1,l}\\ ⋮& ⋮& \ddots & ⋮& ⋮& ⋮& \ddots & ⋮\\ O_{l,1}& O_{l,2}& \dots & O_{l,t-l}& Q_{l,1}& Q_{l,2}& \dots & Q_{l,l}\end{array}\right]& \left(27\right)\end{array}$
where each O_i,j is a d_i×b zero matrix for 1≦i≦l, and 1≦k≦t−l and Q_i,j is a d_i×b matrix over GF(2) for 1≦j≦l. Each non-zero submatrix Q_i,j is a partial circulant obtained by cyclically shifting the first row of Q_i,j (one place to the right) d_i−1 times to form the other d_i−1 rows. Therefore, Q also has a circulant structure. For 1≦i≦l, let q_i=(0 0 . . . 0 q_i,1 q_i,2 . . . q_i,ib) be the first row of the i-th row of submatrices, [O_i,1 . . . O_i,t−l Q_i,1 . . . Q_i,l], of Q, which has the following structure: (1) the first (t−l)b components are zeros; and (2) the lb−r_H bits of w_i=(q_i,1 q_i,2 . . . q_i,lb) that correspond to the linearly dependent columns of D*, called the dependent bits, have the form, (0₁ . . . 0_i−1 u_i 0_i+1 . . . 0_l) where for s≠i, 0_s is a zero d_s-tuple and u_i=(1, 0, . . . , 0) is a unit d_i-tuple. Based on the structure of w_i, there are r_H unknown components of w_i, the same number as the rank of D*. The condition H_qc*Q^T=[O] gives the following equation for 1≦i≦l:

[0108] $\begin{array}{cc}{D}^{*}·w_i^T=\left[\begin{array}{cccc}{A}_{1,t-l+1}& A_{1,t-l+2}& \dots & A_{1,t}\\ A_{2,t-l+1}& A_{2,t-l+2}& \dots & A_{2,t}\\ ⋮& ⋮& \ddots & ⋮\\ A_{c,t-l+1}& A_{c,t-l+2}& \dots & A_{c,t}\end{array}\right]·\left[\begin{array}{c}{q}_{i,1}\\ q_{i,2}\\ ⋮\\ q_{i,\mathrm{bl}}\end{array}\right]=0& \left(28\right)\end{array}$
By solving equation (28), we find w_i=(q_i,1 q_i,2 . . . q_i,lb) for 1≦i≦l. Divide the vector w_i into l sections, denoted w_i,1, w_i,2, . . . , w_i,l, each consisting of b consecutive components of w_i. For 1≦j≦l, Q_i,j is obtained by using w_i,j as the first row and then cyclically shifting it d_i−1 times to form the other d_i−1 rows. We form the matrix Q from the Q_i,j's with 1≦i,j≦l.

[0109] Based on the generator matrix G_qc* given by equation (25), an encoder with two sub-encoders can be implemented. The first sub-encoder is implemented based on the submatrix G, and the second one is implemented based on the submatrix Q. An information sequence a of length (tb−r_H) bits is divided into two parts, a⁽¹⁾ and a⁽²⁾, where a⁽¹⁾ consists of the first (t−l)b information bits and a⁽²⁾ consists of the last lb−r_H information bits. The first sub-encoder encodes a⁽¹⁾ into a codeword in the subcode C⁽¹⁾ generated by G, and the second sub-encoder encodes a⁽²⁾ into a codeword in the subcode C⁽²⁾ generated by Q. Adding the outputs of the two sub-encoders, we obtain the codeword for the information sequence a.

[0110] The first sub-encoder based on the submatrix G of G_qc* can be implemented in exactly the same way as described for the single stage encoder implementation of Case I. To encode the second part a⁽²⁾ of the information sequence a into a codeword in the subcode C⁽²⁾ generated by the submatrix Q of Q_qc*, we divide a⁽²⁾ into l sections, a₁⁽²⁾, a₂⁽²⁾, . . . , a_i⁽²⁾ with d₁, d₂, . . . , d_l bits, respectively. Then the codeword for a⁽²⁾ is of the form:
v⁽²⁾=(0 0 . . . 0v₁⁽²⁾ . . . v_l⁽²⁾),  (29)
which consists of t−l zero-sections and l non-zero sections, v₁⁽²⁾, . . . , v_l⁽²⁾, with each section consisting of b bits. For 1≦j≦l:

[0111] $\begin{array}{cc}{v}_j^{\left(2\right)}=\sum _{m=1}^l{a}_m^{\left(2\right)}{Q}_{m,j}.& \left(30\right)\end{array}$
Since each Q_i,j in Q with 1≦i,j≦l is a partial circulant with d_i rows, the second sub-encoder can be implemented with l Shift-Register-Adder-Accumulator circuits of the type shown in FIG. 3. In the encoding procedure, the j-th Shift-Register-Adder-Accumulator circuit uses a₁⁽²⁾, a₂⁽²⁾, . . . , a_l⁽²⁾ as the inputs has the contents w_i,j, w_2,j, . . . , w_l,j stored in the shift-register B in turn cyclically shifted d₁, d₂, . . . , d_l times, respectively. At the end of the shifts, v_j⁽²⁾ is stored in the accumulator register A. If the first sub-encoder is also implemented with l Shift-Register-Adder-Accumulator circuits, these same l Shift-Register-Adder-Accumulator circuits can be used to encode the second part a⁽²⁾ of the information sequence a (after encoding of a⁽¹⁾).

[0112] With the above encoding, the output codeword for the information sequence a is not completely systematic. Only the first (t−l)b bits are identical to information bits.

Universal Encoder for Families of Structurally Compatible Binary Quasi-Cyclic Low Density Parity Check Codes

[0113] Consider the structurally compatible families of binary Quasi-Cyclic Low Density Parity Check codes described previously. An encoder can be designed for the base code in this family using the encoder implementation techniques described above. Since the parity check matrix of each code in this structurally compatible family is obtained by deleting columns and rows of circulant matrices in the base code parity check matrix, the encoder of the base code can be used to serve as an encoder for each code of the family with appropriate circuit blocks disabled. We illustrate this by considering the two codes given previously in Example 2. Recall that the parity check matrix H(3,4) of the base code C(3,4) is given by:

[0114] $H\left(3,4\right)=\left[\begin{array}{cccccccccccccccccc}0& 0& 1& & & 0& 0& 0& & & 1& 0& 0& & & 0& 1& 0\\ 1& 0& 0& & & 0& 0& 0& & & 0& 1& 0& & & 0& 0& 1\\ 0& 1& 0& & & 0& 0& 0& & & 0& 0& 1& & & 1& 0& 0\\ & & & & & & & & & & & & & & & & & \\ 0& 1& 0& & & 1& 0& 0& & & 0& 0& 0& & & 0& 0& 1\\ 0& 0& 1& & & 0& 1& 0& & & 0& 0& 0& & & 1& 0& 0\\ 1& 0& 0& & & 0& 0& 1& & & 0& 0& 0& & & 0& 1& 0\\ & & & & & & & & & & & & & & & & & \\ 1& 0& 0& & & 0& 1& 0& & & 0& 0& 1& & & 0& 0& 0\\ 0& 1& 0& & & 0& 0& 1& & & 1& 0& 0& & & 0& 0& 0\\ 0& 0& 1& & & 1& 0& 0& & & 0& 1& 0& & & 0& 0& 0\end{array}\right]$
and the derived structurally compatible code C(2,3) that is obtained by deleting the last row and the last column of 3×3 circulants has parity check matrix H(2,3) given by:

[0115] $H\left(2,3\right)=\left[\begin{array}{ccccccccccccc}0& 0& 1& & & 0& 0& 0& & & 1& 0& 0\\ 1& 0& 0& & & 0& 0& 0& & & 0& 1& 0\\ 0& 1& 0& & & 0& 0& 0& & & 0& 0& 1\\ & & & & & & & & & & & & \\ 0& 1& 0& & & 1& 0& 0& & & 0& 0& 0\\ 0& 0& 1& & & 0& 1& 0& & & 0& 0& 0\\ 1& 0& 0& & & 0& 0& 1& & & 0& 0& 0\end{array}\right]$
Using the methods described above, we find the generator matrix G(3,4) in circulant form corresponding to the parity check matrix H(3,4) to be:

[0116] $\begin{array}{c}G\left(3,4\right)=\left[\begin{array}{cccc}I& G_{1,1}& G_{1,2}& G_{1,3}\\ 0& Q_{1,1}& Q_{1,2}& Q_{1,3}\end{array}\right]\\ =\left[\begin{array}{cccccccccccccccccc}1& 0& 0& & & 0& 1& 1& & & 1& 0& 0& & & 1& 0& 0\\ 0& 1& 0& & & 1& 0& 1& & & 0& 1& 0& & & 0& 1& 0\\ 0& 0& 1& & & 1& 1& 0& & & 0& 0& 1& & & 0& 0& 1\\ & & & & & & & & & & & & & & & & & \\ 0& 0& 0& & & 1& 0& 1& & & 0& 1& 1& & & 1& 1& 0\\ 0& 0& 0& & & 1& 1& 0& & & 1& 0& 1& & & 0& 1& 1\end{array}\right]\end{array}$

[0117] Note that Q_1,1, Q_1,2, and Q_1,3 are partial circulants, not full circulants. Moreover, using the methods described above, we find the generator matrix G(2,3) in circulant form corresponding to the parity check matrix H(2,3) to be:

[0118] $\begin{array}{c}G\left(2,3\right)=\left[\begin{array}{ccc}I& G_{1,1}& G_{1,2}\end{array}\right]\\ =\left[\begin{array}{ccccccccccccc}1& 0& 0& & & 0& 0& 1& & & 0& 1& 0\\ 0& 1& 0& & & 1& 0& 0& & & 0& 0& 1\\ 0& 0& 1& & & 0& 1& 0& & & 1& 0& 0\end{array}\right]\end{array}$

[0119] Consider the generator matrix G(3,4) first for the code C(3,4). Suppose that the information sequence of 5 bits to be encoded is a=(a₁, a₂)=(a₁a₂a₃, a₄a₅) and the information sequence a is divided into two sections, a₁ and a₂. Then the codeword for the information sequence a is v=aG(3,4), which has the following form: v=(p₁,p₂,p₃,a₁) where p_i=(p_i1p_i2p_i3) is a section of 3 parity-check bits. Let g_i,j be the first row of G_i,y, and let q_i,j be the first row of Q_i,j as described previously. Moreover, denote g_i,j^(k) to be the k-th cyclic shift of g_i,j. Then:
p_j=a₁g_1,j⁽⁰⁾+a₂g_1,j⁽¹⁾+a₃g_1,j⁽²⁾+a₄q_1,j⁽⁰⁾+a₅q_1,j⁽¹⁾

[0120] Based on this expression, an encoder circuit for code C(3,4) can be obtained as shown in FIG. 7. This circuit consists of three Shift-Register-Adder-Accumulator circuits. The j-th Shift-Register-Adder-Accumulator circuit corresponds to the j-th column of circulants of the generator matrix G(3,4) and is used to produce the j-th section of parity-check bits p_j. For example, consider the leftmost Shift-Register-Adder-Accumulator circuit corresponding to the first column of circulants of generator matrix G(3,4). At the start, g_1,1⁽⁰⁾=(011) is stored in the 3-bit feedback shift-register B1 and the contents of the 3-bit accumulator register A1 are set to zero. When the information bit a₁ is shifted into the encoder, the product a₁g_1,1⁽⁰⁾ is formed at the outputs of the AND-gates and is added to the contents stored in the register A1 (zero at this time). The sum is then stored in the register A1. The feedback register B1 is shifted once to the right. The new contents of B1 are then g_1,1⁽¹⁾. When the next information bit a₂ is shifted into the encoder, the product a₂g_1,1⁽¹⁾ is formed at the outputs of the AND-gates. This product is then added to the sum a₁g_1,1⁽⁰⁾ in the accumulator register A1. The sum a₁g_1,1⁽⁰⁾+a₂g_1,1⁽¹⁾ is then stored in A1. The above shift-add-store process continues until the last bit of section a₁ enters the encoder; after which the register A1 stores the partial sum a₁G_1,1, which is the contribution to the parity section p₁ from the information section a₁. At this time, the generator q_1,1⁽⁰⁾=(101) of the circulant Q_1,1 is loaded into B1. The shift-add-store process repeats. When the information section a₂ has been completely shifted into the encoder, register A1 contains the accumulated sum p_j=a₁g_1,1⁽⁰⁾+a₂g_1,1⁽¹⁾+a₃g_1,1⁽²⁾+a₄q_1,1⁽⁰⁾+a₅q_1,1⁽¹⁾. At the same time, register A2 and A3 contain the parity section p₂ and p₃, respectively. The encoding process ends after all the parity-check bits have been formed.

[0121] The encoder circuit for the code C(3,4) shown in FIG. 7 can also be used as an encoder for the code C(2,3). The only modification is to turn off the 3^rd Shift-Register-Adder-Accumulator circuit and update the contents stored in the feedback shift registers B1 and B2 using G(2,3). FIG. 9 shows the encoder circuit for the code C(2,3).

Channel Decoding Algorithms for Binary Regular Low Density Parity Check Codes

[0122] Binary regular Low Density Parity Check codes can be efficiently decoded in various ways. Even though many regular Low Density Parity Check codes have been devised primarily for Soft-Input Soft-Output (SISO) iterative decoding based on belief propagation, such as Sum-Product Algorithm decoding, other decoding methods of less complexity can also be employed. These include the hard-decision One-Step Majority-Logic (OSML) and Bit Flipping (BF) methods that require only simple logical operations in implementations. OSML decoding has the least decoding delay and very high decoding speed can be achieved. A (γ, ρ)-regular Low Density Parity Check code decoded with OSML decoding can correct any error pattern with └γ/2┘ or fewer random errors. Therefore, for a code to be effective with the OSML decoding, γ must be relatively large. While BF decoding can result in better performance than OSML, the soft-decision decoding scheme such as Sum-Product Algorithm decoding provides the best error probability performances. However, Sum-Product Algorithm decoding requires extensive computations; hence, they require highly complexity implementations. Intermediate in complexity between the hard-decision and soft-decision methods are the weighted OSML and weighted BF decoding methods. Weighted OSML and weighted BF decoding are reliability-based decoding methods that require some real-number computations besides logical operations. They improve the error performance of OSML and BF decoding at a cost of some additional computational complexity and offer a good trade-off between error performance and decoding complexity. The binary Quasi-Cyclic Low Density Parity Check codes used in this universal forward error-correction coding system have the significant advantage of being able to employ any of the above decoding algorithms with good error performance and to implement channel decoders of varying complexity. This provides the capability of realizing useful trade-offs between decoder implementation complexity and error performance for many applications.

[0123] The following sections describe the concept of Tanner graphs, which are useful for understanding the structural properties of Low Density Parity Check codes as well as iterative decoding methods. We describe a new weighted BF decoding method called Double-Weighted Bit Flipping (DWBF) decoding. Double-Weighted Bit Flipping decoding has an error performance that can approach that of Sum-Product Algorithm decoding for the binary Quasi-Cyclic Low Density Parity Check codes of this universal forward error-correction coding system and yet has roughly an implementation complexity similar to that of the standard weighted Bit Flipping decoding method.

Tanner Graphs

[0124] Tanner graphs represent general linear codes by bipartite graphs that are useful for analyzing the structure of Low Density Parity Check codes as well as for representing message passing in iterative decoding algorithms such as the Sum-Product Algorithm, Bit Flipping, and weighted Bit Flipping methods.

[0125] Consider a binary (γ, ρ)-regular Low Density Parity Check code of blocklength n specified as the null space of a parity check matrix H with J rows and n columns. Let h₁, h₂, . . . , h_J be the rows of H where h_j=(h_j,0, h_j,1, . . . , h_j,n−1) for 1≦j≦J. It follows from equation (5) that a n-tuple v=(v₀, v₁, . . . , v_n−1) is a codeword if and only if the inner product:

[0126] $\begin{array}{cc}{s}_j=v·h_j^T=\sum _{l=0}^{n-1}{v}_l{h}_{j,l}=0& \left(31\right)\end{array}$
for 1≦j≦J. The sum given by equation (31) is called a parity-check sum (or simply check sum), which is simply a linear sum of a subset of code bits. A code bit v_l is said to be checked by the check sum s_j=v·h_j^T (or the row h_j) if h_j,l=1.

[0127] A graph can be constructed to display the relationship between the code bits and the check sums that check on them. This graph consists of two levels of vertices. The first level consists of n vertices, which represent the n code bits of the code. These vertices, denoted v₁, v₂, . . . , v_n, are called the code bit (or variable) vertices (or nodes). The second level consists of J vertices which represent the J check sums s₁, s₂, . . . , s_J that the code bits must satisfy. These vertices are called the check sum vertices (or nodes). A code bit vertex v_l is connected to a check sum vertex s_j by an edge, denoted (v_l, s_j), if and only if the code bit v_l is contained in the check sum s_j (or checked by the check sum s_j). No two code bit vertices are connected and no two check sum vertices are connected. This graph is a bipartite graph called the Tanner Graph of the code. The number of edges that are connected to (or incident at) a code bit vertex v_l, called the degree of v_l, is simply the number of check sums that contain v_l. The number of edges that are incident at the check sum vertex s_j, called the degree of s_j, is simply the number of code bits that are checked by the check sum s_j. For a binary regular Low Density Parity Check code, the degrees of all the code bit vertices are the same and the degrees of all the check sum vertices are the same. Such a Tanner Graph is said to be regular.

• • [0128] Consider a sample binary linear code with parity check matrix:

[0129] $H=\left[\begin{array}{ccccc}1& 1& 1& 1& 0\\ 1& 1& 1& 0& 1\\ 0& 0& 0& 1& 1\end{array}\right]$

• • [0130]  The Tanner Graph is shown in FIG. 8. The variable (or codeword) nodes in this Tanner Graph correspond to the codeword bits and are represented by the circles labeled v₁, . . . , v₅. The check-sum nodes correspond to the rows of the parity check matrix and are represented by the circles labeled c₁, c₂, c₃.

[0131] A cycle in a graph of vertices and edges is defined as a sequence of connected edges that starts from a vertex and ends at the same vertex, and satisfies the condition that no vertex (except the initial and the final vertex) appears more than once. The number of edges on a cycle is called the length of the cycle. The length of the shortest cycle in a graph is called the girth of the graph. The Tanner Graph of a linear block code contains no cycles of length 2 and no cycles of odd lengths. Therefore, the girth of the Tanner Graph of a linear block code is at least 4.

[0132] The error performance for soft-decision iterative Sum-Product Algorithm decoding of a linear code very much depends on cycles of short lengths in its Tanner Graph. These short cycles, especially cycles of length 4, make successive decoding iterations highly correlated; hence, they severely limit decoding performance. Therefore, to use the Sum-Product Algorithm for decoding, it is important to design codes without short cycles in their Tanner Graphs, especially cycles of length 4. The Tanner Graphs of binary (γ, ρ)-regular Low Density Parity Check codes are regular. Since the row and column weights of H are ρ and γ, respectively, the degrees of each check sum vertex and each code bit vertex in the Tanner Graph are ρ and γ, respectively. It follows from the Row-Column constraint on the columns and rows of the parity check matrix H of a binary Low Density Parity Check code that no two-code bits are checked simultaneously by two-check sums. This implies that the Tanner Graph of a binary Low Density Parity Check code does not contain cycles of length 4. However, they may contain cycles of length 6. Hence, the girth of the Tanner Graph of a binary regular or irregular Low Density Parity Check code, specified by a Row-Column constrained parity-check matrix, is at least 6. The binary Quasi-Cyclic Low Density Parity Check codes described above satisfy the Row-Column constraint; therefore, their Tanner Graphs have a girth of at least 6.

Standard Decoding Algorithms

[0133] For illustrative purposes, we describe in this section decoding methods only for Binary Phase Shift Keying (BPSK) modulation over Additive White Gaussian Noise channels. Decoding for other communication channels (storage medium) can be addressed similarly.

[0134] Suppose a binary (γ, ρ)-regular Low Density Parity Check code with J×n parity check matrix H is used for over an Additive White Gaussian Noise channel with zero mean and power spectral density N₀/2. Assume coherent BPSK signaling with unit energy. A codeword v=(v₀, v₁, . . . , v_n−1) is mapped into a bipolar sequence x=(x₀, x₁, . . . , x_n−1) before its transmission, where x_l=(v_l−1)=+1 for v_l=1 and x_l=−1 for v_l=0 with 0≦l≦n−1. Let y=(y₀, y₁, . . . , y_n−1) be the soft-decision received sequence at the output of the demodulator matched filter. For 0≦l≦n−1, y_l=±1+n_l where n_l is a Gaussian random variable with zero mean and variance N₀/2. Let z=(z₀, z₁, . . . , z_n−1) be the binary hard-decision received sequence obtained from y as follows: z_l=1 for y_l>0 and z_l=0 for y_l≦0. Let h₁, h₂, . . . , h_J be the rows of H where h_j=(h_j,0, h_j,1, . . . , h_j,n−1) for 1≦j≦J. Then:
s=(s₁,s₂, . . . s_J)=z·H^T  (32)
gives the syndrome of the received sequence z, where the j-th syndrome component s_j is given by the check sum:

[0135] $\begin{array}{cc}{s}_j=z·h_j=\sum _{l=0}^{n-1}{z}_l{h}_{j,l}& \left(33\right)\end{array}$
The received vector z is a codeword if and only if s=0. If s≠0, then errors in z are detected. A non-zero syndrome component s_j indicates a parity failure. The total number of parity failures is equal to the number of non-zero syndrome components in s. Let:
e=(e₀,e₁, . . . e_n−1)=(v₀,v₁, . . . v_n−1)+(z₀,z₁, . . . z_n−1)  (34)
Then e is the error pattern in z. This error pattern e and the syndrome s satisfy the condition:

[0136] $\begin{array}{cc}s=\left(\begin{array}{cccc}{s}_1,& s_2,& \dots & s_J\end{array}\right)=e·H^T\mathrm{where}\text{:}& \left(35\right)\\ s_j=e·h_j=\sum _{l=0}^{n-1}{e}_l{h}_{j,l}& \left(36\right)\end{array}$
for 1≦j≦J.
One-Step Majority-Logic Decoding

[0137] One-Step Majority-Logic (OSML) decoding of binary (γ, ρ)-regular Low Density Parity Check codes is as follows. A code bit v_l is said to be checked by the check sum s_j=v·h_j^T if h_j,l=1. Let A1 be the set of rows in H that check on the code bit v_l. Let S_l denote the set of check sums formed by the rows in A_l. It follows from the Row-Column constraint property of H for binary (γ, ρ)-regular Low Density Parity Check codes that the code bit v_l is contained in every check sum in S_l, and any of the other n−1 code bits is contained in at most one check sum in S_l. The check sums in S_l (or the rows in A_l) are said to be orthogonal on the code bit v_l. The check sums in S_l are called the orthogonal check sums on code bit v_l, and the rows in A_l are called the orthogonal vectors on v_l. For 0≦l≦n−1, each code bit v_l is checked by exactly γ orthogonal check sums. So denote:
A_l={h₁⁽ⁱ⁾, h₂^(l), . . . h_γ^(l)}  (37)
as the set of γ rows in H that are orthogonal on this bit position l; that is, the l-th component of each row in A_l is 1, and no two rows in A_l have a common 1 in any other position. We form the following set of syndrome equations based on the rows in A_l:

[0138] $\begin{array}{cc}{S}_l=\left\{s_j^{\left(l\right)}=e·h_j^{\left(l\right)}:h_j^{\left(l\right)}\in A_l\mathrm{for}1\le j\le \gamma \right\}\mathrm{where}\text{:}& \left(38\right)\\ s_j^{\left(l\right)}=e·h_j^{\left(l\right)}=\sum _{i=0}^{n-1}{e}_i{h}_{j,i}^{\left(l\right)}.& \left(39\right)\end{array}$
An error digit e_l is said to be checked by the check sum S_l if the coefficient h_i,l=1. Each check sum in S_l checks the error bit e_l, and any other error bit in e is checked by at most one check sum in S_l. Therefore, S_l gives a set of γ check sums orthogonal on the error digit e_l.

[0139] Suppose there are └γ/2┘ or fewer errors in the error vector e=(e₀, e₁, . . . , e_n−1) (i.e., └γ/2┘ or fewer components of e are 1). If e_l=1, then other non-zero error digits can distribute among at most └γ/2┘−1 check-sums orthogonal on e_l. Hence, at least γ−└γ/2┘+1, or more than half of the check sums orthogonal on e_l, are equal to e_l=1; however, if e_l=0, the non-zero error digits can distribute among at most └γ/2┘ check-sums. Hence, at least γ−└γ/2┘, or at least half of the check sums orthogonal on e_l are equal to e_l=0. Thus, the value of e_l is equal to the value assumed by a clear majority of the parity check sums orthogonal on e_l; if no value is assumed by a clear majority of the parity check sums (i.e., there is a tie), the error digit e_l is zero. Based on the preceding fact, an algorithm for decoding e_l can be formulated as follows. The error digit e_l is decoded as 1 if a clear majority of the parity check sums orthogonal on e_l takes on the value 1; otherwise, e_l is decoded as 0. Correct decoding of e_l is guaranteed if there are └γ/2┘ or fewer errors in the error vector e. If it is possible to form γ parity check sums orthogonal on e_l, it is possible to form y parity check sums orthogonal on any error digit because of the symmetry of the code. The decoding of the other error digits is identical to the decoding of the error digit e_l. This decoding algorithm is called One-Step Majority-Logic (OSML) decoding. The binary (γ, ρ)-regular Low Density Parity Check code is capable of correcting any error pattern with └γ/2┘ or fewer errors using OSML decoding and, as a result, its minimum distance is greater than or equal to γ+1.

Bit Flipping Decoding

[0140] Bit Flipping (BF) decoding of binary (γ, ρ)-regular Low Density Parity Check codes is as follows. When detectable errors occur during the transmission, there will be parity failures in the syndrome s=(s₁, s₂, . . . s_J), and some of the syndrome bits are equal to 1. BF decoding is based on the change of the number of parity failures in {z·h_k:1≦j≦J} when a bit in the received sequence z is changed.

[0141] First, the decoder computes all the parity check sums based on equation (33) and then changes any bit in the received vector z that is contained in more than some fixed number δ of unsatisfied parity check equations (i.e., with non-zero check sums). Using these new values, the parity check sums are recomputed, and the process is repeated until the parity check equations are all satisfied (i.e., all the check sums are equal to zero). This is then an iterative decoding algorithm. The parameter δ, called threshold, is a design parameter that should be chosen to optimize the error performance while minimizing the number of computations of parity check sums. The value of δ depends on the code parameters ρ, γ, the code minimum distance d_min, and the Signal-To-Noise Ratio.

[0142] If decoding fails for a given value of δ, then the value of δ can be reduced to allow further decoding iterations. For error patterns with a number of errors less than or equal to the error correcting capability of the code, the decoding will be completed in one or a few iterations. Otherwise, more decoding iterations are needed. Therefore, the number of decoding iterations is a random variable and is a function of the channel Signal-To-Noise Ratio. A limit may be set on the number of iterations. When this limit is reached, the decoding process is terminated to avoid excessive computations. Due to the nature of binary Low Density Parity Check codes, the above decoding algorithm corrects many error patterns with a number of errors exceeding the error-correcting capability of the code.

[0143] A very simple implementation of the BF decoding algorithm is given below:

• • [0144] Step 1: Compute the parity check sums (syndrome bits). If all the parity check equations are satisfied (i.e., all the syndrome bits are zero), stop the decoding.
  • [0145] Step 2: Find the number of unsatisfied parity check equations for each code bit position, denoted f_i, i=0, 1, . . . , n−1.
  • [0146] Step 3: Identify the set of bits for which f_i is the largest.
  • [0147] Step 4: Flip the bits in this set.
  • [0148] Step 5: Repeat steps 1 to 4 until all the parity check equations are satisfied (for this case, we stop the iteration in step 1) or when a predefined maximum number of iterations is reached.

[0149] BF decoding requires only logical operations. The number of logical operations N_BF performed for each decoding iteration is linearly proportional to Jρ (or nγ), say N_BF=K_BFJρ, where the constant K_BF depends on the implementation of the BF decoding algorithm. Typically, the value of K_BF is less than 3. The simple BF decoding algorithm can be improved by using adaptive thresholds δ's. Of course, this improvement is achieved at the expense of more computations. Binary Quasi-Cyclic Low Density Parity Check codes perform well with BF decoding because a large number of check sums orthogonal on each code bit can be formed when the code blocklength n is large.

Weighted One-Step Majority-Logic and Weighted Bit Flipping Decoding

[0150] The simple hard-decision One-Step Majority-Logic (OSML) and Bit Flipping (BF) decoding methods can be improved to achieve better error performance by including some reliability information (or measure) of the received symbols in the decoding decisions. Of course, additional decoding complexity is required to achieve such performance improvements. Consider the soft-decision received sequence y=(y₀, y₁, . . . , y_n−1). For the Additive White Gaussian Noise channel, a simple measure of the reliability of a received symbol y_l is its magnitude, |y_l|: the larger the magnitude |y_l|, the higher the reliability of the hard-decision digit z_l. Many reliability-based algorithms based on this reliability measure have been devised for decoding linear block codes. In the following, this reliability measure is used to modify both the OSML and the BF decoding methods.

[0151] Again, consider a Low Density Parity Check code specified by a parity check matrix H with J rows, given by {h₁, h₂, . . . h_J}. For 0≦l≦n−1 and 1≦j≦J, define:

[0152] $\begin{array}{cc}{y_j}_{\min }^{\left(l\right)}=\min \left\{y_i:0\le i\le n-1,h_{j,i}^{\left(l\right)}=1\right\}\mathrm{and}& \left(40\right)\\ E_l=\sum _{s_j^{\left(l\right)}\in S_l}\left(2s_j^{\left(l\right)}-1\right)·{y_j}_{\min }^{\left(l\right)}& \left(41\right)\end{array}$
where S_l is the set of check sums s_j^(l) orthogonal on bit-position l. The value E_l is a weighted check sum that is orthogonal on the code bit position l. Let e=(e₀, e₁, . . . , e_n−1) be the error pattern to be decoded. Then the OSML decoding algorithm can be modified based on the weighted check sum E_l as follows:

[0153] $\begin{array}{cc}{e}_l=\{\begin{array}{cc}1,& \mathrm{for}{E}_l>0,\\ 0,& \mathrm{for}{E}_l\le 0,\end{array}& \left(42\right)\end{array}$
for 0≦l≦n−1. This modified OSML algorithm is called weighted One-Step Majority Logic (OSML) decoding.

[0154] The decision rule given by equation (42) can also be used in BF decoding. In this case, the decoding is carried out as follows:

• • [0155] Step 1 Compute the check sums. If all the parity check equations are satisfied, stop the decoding.
  • [0156] Step 2 Compute E_l based on (41), for 0≦l≦n−1.
  • [0157] Step 3 Find the bit position l for which E_l is the largest.
  • [0158] Step 4 Flip the bit z_l.
  • [0159] Step 5 Repeat Steps 1 to 4. This process of bit flipping continues until all the parity check equations are satisfied or a preset maximum number of iterations is reached.
    This modified BF algorithm is called weighted Bit Flipping (BF) decoding.

[0160] The above weighted OSML and weighted BF decoding algorithms require soft-decision channel outputs and also require real addition operations to compute the weighted check sums, E_l's to make decisions. The resulting computational complexities of both weighted OSML and weighted BF decoding methods are dominated by the total number of real additions needed to decode a received sequence. From equation (41), we can readily see that for weighted OSML decoding, the number of real additions required for decoding a received sequence is equal to K_OSML(Jρ+nγ), where K_OSML is a constant. However, for weighted BF decoding, the number of real additions needed for each decoding iteration is equal to K_OSML(Jρ+nγ). Since Jρ (or nγ) is the total number of “1” entries in the parity check matrix H of the code, the computational complexities of both weighted OSML and BF decoding methods are linearly proportional to the total number of “1” entries in H.

Sum-Product Algorithm Decoding

[0161] The Sum-Product Algorithm is an iterative decoding algorithm based on belief propagation, which is extremely efficient for decoding Low Density Parity Check codes. Like the MAP (maximum a posteriori probability) decoding algorithm, it is a symbol-by-symbol Soft-Input Soft-Output (SISO) iterative decoding algorithm. It processes the received symbols iteratively to improve the reliability of each decoded code symbol based on the parity check sums computed from the hard-decisions of the received symbols and the parity check matrix H of the code. The reliability of a decoded symbol can be measured by its marginal posteriori probability, its Log-Likelihood Ratio, or the value of its corresponding received symbol. The computed reliability measures of code symbols at the end of each decoding iteration are used as inputs for the next iteration. The decoding iteration process continues until a certain stopping condition is satisfied. Then, based on the computed reliability measures of code symbols, hard decisions are made.

[0162] Again, we consider a binary (γ, ρ)-regular Low Density Parity Check code C of blocklength n specified by a parity check matrix H with J rows, given by {h₁, h₂, . . . h_J}. For 1≦j≦J, define the following index set for h_j:
B(h_j)={l:h_j,l=1, 0≦l≦n−1},  (43)
which is called the support of h_j. The implementation of Sum-Product Algorithm decoding is based on the computation of the marginal a posteriori probabilities, P(v_l|y)'s, for 0≦l≦n−1 Then the Log-Likelihood Ratio for each code bit is given by:

[0163] $\begin{array}{cc}L\left(v_l\right)=\log \frac{P\left(V_l=1|y\right)}{P\left(v_l=0|y\right)}.& \left(44\right)\end{array}$
Let p_l⁰=P(v_l=0) and p_l¹=P(v_l=1) be the prior probabilities of v_l=0 and v_l=1, respectively. For 0≦l≦n−1, 1≦j≦J, and each h_j∈A_i, where A_l is the set of rows of H that are orthogonal to the l-th code bit, let q_j,l^x,(i) be the conditional probability that the transmitted code bit v_l has value x (0 or 1), given the check-sums computed based on the check vectors in A_l\h_j at the i-th decoding iteration. For 0≦l≦n−1, 1≦j≦J, and h_j∈A_l, let σ_j,l^x,(i) be the conditional probability that the check-sum s_j is satisfied (i.e. s_j=0), given v_l=x (0 or 1) and the other code bits in B(h_j) have a separable distribution {q_j,t^vt,(i): t∈B(h_j)\l}, i.e.:

[0164] $\begin{array}{cc}{\sigma }_{j,l}^{x,\left(i\right)}=\sum _{\left\{v_t:t\in B\left(h_j\right)\backslash l\right\}}P\left(s_j=0|v_l=x,\left\{v_t:t\in B\left(h_j\right)\backslash l\right\}\right)·\prod _{t\in B\left(h_j\right)\backslash l}{q}_{j,t}^{v_t,\left(i\right)}.& \left(45\right)\end{array}$
The computed values of σ_j,l^x,(i) are then used to update the values of q_j,l^x,(i+1) as follows:

[0165] $\begin{array}{cc}{q}_{j,l}^{x,\left(i+1\right)}={\alpha }_{j,l}^{\left(i+1\right)}{p}_l^x\prod _{h_t\in A_l\backslash h_j}{\sigma }_{j,l}^{x,\left(i\right)}& \left(46\right)\end{array}$
where α_j,l⁽ⁱ⁺¹⁾ is chosen such that q_j,l^0,(i+1)+q_j,i^l,(i+1)=1. The computed values of q_j,l^x(i+1) are then used to update the values of σ_j,l^x,(i+1) using equation (45). The updating between q_j,l^x,(i) and σ_j,l^x,(i) is carried out iteratively during the decoding process.

[0166] At the i-th iteration step, the pseudo-posterior probabilities are given by:

[0167] $\begin{array}{cc}{P}^{\left(i\right)}\left(v_l=x|y\right)={\alpha }_l^{\left(i\right)}{p}_l^x\prod _{h_j\in A_l}{\sigma }_{j,l}^{x,\left(i-1\right)},& \left(47\right)\end{array}$
where α_lⁱ is chosen such that P⁽ⁱ⁾(v_l=0|y)+P⁽ⁱ⁾(v_l=1|y)=1. Based on these probabilities, we can form the vector z⁽ⁱ⁾=(z₀⁽ⁱ⁾, z₁⁽ⁱ⁾, . . . z_n−1⁽ⁱ⁾) as the candidate decoded codeword with:

[0168] $\begin{array}{cc}{z}_l^{\left(i\right)}=\{\begin{array}{cc}1,& \mathrm{for}{P}^{\left(i\right)}\left(v_l=1|y\right)>0.5\\ 0,& \mathrm{otherwise}.\end{array}& \left(48\right)\end{array}$
Then re-compute z⁽ⁱ⁾·H^T. If z⁽ⁱ⁾·H^T=0, stop the decoding iteration process, and output z⁽ⁱ⁾ as the decoded codeword.

[0169] The Sum-Product Algorithm decoding method then consists of the following steps:

• • [0170] Initialization: Set i=0 and set the maximum number of iterations to I_max. For every pair (j,l) such that h_j,l=1 with 1≦j≦J and 0≦l≦n−1, set q_j,l^0,(0)=p_l⁰ and q_j,l^1,(0)=p_l¹.
  • [0171] Step 1: For 0≦l≦n−1, 1≦j≦J, and each h_j∈A_l, compute the probabilities σ_j,l^0,(i) and σ_j,l^1,(i). Go to Step 2.
  • [0172] Step 2: For 0≦l≦n−1, 1≦j≦J, and each h_j∈A_l, compute the values of q_j,l^0,(i+1) and q_j,l^1,(i+1) and the values of P⁽ⁱ⁺¹⁾(v_i=0|y) and P⁽ⁱ⁺¹⁾(v_l=1|y). Form z⁽ⁱ⁺¹⁾ and test z⁽ⁱ⁺¹⁾·H^T. If z⁽ⁱ⁺¹⁾·H^T=0 or the maximum iteration number I_max is reached, go to Step 3. Otherwise, set i:=i+1 and go to Step 1.
  • [0173] Step 3: Output z⁽ⁱ⁺¹⁾ as the decoded codeword and stop the decoding process.

[0174] In order to implement the Sum-Product Algorithm decoding algorithm, real number additions, subtractions, multiplications, divisions, as well as evaluations of exponential and logarithm functions are needed. The last four types of operations are more complex than addition and subtraction. For this reason, we simply ignore the number of additions and subtractions in analyzing the computational complexity of this algorithm. From equations (45) to (47), we find that the number of multiplications and divisions needed in each iteration of the Sum-Product Algorithm decoding algorithm is of the order O(2Jρ+4nγ), and the number of exponential and logarithm function evaluations needed for each iteration of decoding is of the order O(n). We see that the resulting complexity can be prohibitively high in particular for high-speed applications. Therefore, full Sum-Product Algorithm decoding may not be practical for these types of applications.

Two-Stage Hybrid Decoding

[0175] The Sum-Product Algorithm decoding method is computationally intensive, as each decoding iteration requires many real number computations. A large number of iterations may be needed to achieve desired error performance objectives, resulting in a large number of computations and a long decoding delay that is not desirable in high-speed applications. However, for binary Quasi-Cyclic Low Density Parity Check codes, this difficulty can be overcome by using a two-stage hybrid soft/hard decoding scheme. In the first stage, the binary Quasi-Cyclic Low Density Parity Check code is decoded using Sum-Product Algorithm decoding with a fixed number of iterations that is small, say, equal to I. At the completion of the I-th iteration, hard decisions of decoded symbols are made based on their Log-Likelihood Ratios. This results in a binary sequence z of estimated code bits. This sequence z is then decoded using simple OSML decoding. This two-stage hybrid decoding works well for binary (γ, ρ)-regular Quasi-Cyclic Low Density Parity Check codes with large γ because they have large minimum distances, and Sum-Product Algorithm decoding of these codes converges very fast. Simulation results for many codes show that the performance gap between 5 iterations and 100 iterations is within 0.2 dB. Therefore, at the first stage, we may set the number of iterations for the Sum-Product Algorithm decoding to 5 or less (in many cases, 2 iterations are enough). The resulting estimated code sequence z may still contain a small number of errors. These errors will be corrected by the OSML decoding at the second stage due to the large majority-logic error correcting capability of binary (γ, ρ)-regular Quasi-Cyclic Low Density Parity Check codes. The two-stage hybrid soft/hard decoding scheme offers a good trade-off between error performance and decoding complexity. Furthermore, it reduces decoding delay.

New Double-Weighted Bit Flipping Decoding

[0176] Since BF decoding is a hard-decision decoding algorithm, it has a significant performance degradation compared to iterative soft-decision Sum-Product Algorithm decoding. Weighted BF decoding has the potential of closing this performance gap by using soft-decision reliability information in decoding. A modified weighted BF procedure, called LP-WBF decoding, can achieve a performance within 1 dB of the Sum-Product Algorithm decoding at a BER of 10⁻⁶. A further improvement is by weighting the check-sums. This method is called the Weighted-Sum Weighted Bit Flipping (WS-WBF) algorithm. The WS-WBF method needs to find a threshold T and a constant integer K in its implementation to achieve a better performance than the LP-WBF algorithm.

[0177] In this universal forward error-correction coding system, a new approach is developed to weigh the reliability of the check-sums. Instead of finding a good combination of T and K by computer search as is necessary for the WS-WBF approach, this new approach sets the reliability information embedded in the check-sums as a probability function of the received sequence. We call this new decoding algorithm Double-Weighted Bit Flipping (DWBF) decoding. Simulation results for the (1023, 781) FG-Low Density Parity Check code show that the performance of this code using DWBF decoding is superior to the best results achieved using WS-WBF decoding.

[0178] Suppose a binary (γ,ρ)-regular Low Density Parity Check code with J×n parity check matrix H with J rows, given by {h₁, h₂, . . . h_J} where h_j=(h_j,0, h_j,1, . . . , h_jn−1), for 1≦j≦J, is used for over an Additive White Gaussian Noise channel with zero mean and power spectral density N₀/2. We assume that coherent BPSK signaling with unit energy is used and let y=(y₀, y₁, . . . , y_n−1) be the soft-decision received sequence at the output of the demodulator matched filter. The Double-Weighted Bit Flipping decoding algorithm consists of the following initialization and iteration steps.

[0179] Initialization Step:

• • [0180] Denote z=(z₀, z₁, . . . , z_n−1) to be the hard decisions sequence obtained from y, where:

[0181] $z_j=\{\begin{array}{cc}1,& \mathrm{for}{y}_j>0,\\ 0,& \mathrm{for}{y}_j\le 0,\end{array}.$

• • [0182] Next compute the syndrome s=(s₀, s₁, . . . , s_n−1) for the sequence z given by s=zH^T. If all parity equations are satisfied, then stop the decoding. Otherwise, s≠0. Then weighted check sums that incorporate a reliability measure for the hard-decision sequence z must be computed next to decide which bit to flip for the next iteration step. Define r=(r₀, r₁, . . . , r_n−1), where r_j=|y_j|. The standard weighted BF decoding algorithm described above used r as the reliability measure or metric for the hard-decision sequence z to arrive at the weighted check sums given by equation (41). We shall use a different weighting in the DWBF algorithm to compute these weighted check sums. For each check-sum s_j, we first need to record the largest and the smallest values among the received soft-decision sequence y that is related to check-sum s_j, where 1≦j≦J. For 1≦j≦J, denote K(j)={0≦i≦n−1: h_j,i=1} and let U_j=max{|y_i|: iεK(j)} and L_j=min{|y_i|: iεK(j)} be the largest and the smallest soft-decision samples respectively corresponding to the check-sum s_j.

[0183] Iteration Step:

• • [0184] To choose which bit to flip, we need to calculate a weighted check sum T_l for every bit position l, 0≦l≦n−1. The LP-WBF decoding algorithm uses the following weighted check sum:

[0185] $\begin{array}{cc}{T}_l=\sum _{j\in M\left(l\right)}{T}_{j,l}& \left(49\right)\end{array}$

• • [0186]  where M(l)={1≦j≦J: h_j,l=1} and where:

[0187] $\begin{array}{cc}{T}_{j,l}=\{\begin{array}{cc}y_l-\frac{L_j}{2},& \mathrm{if}{s}_j=0\\ y_l-\left(U_j+\frac{L_j}{2}\right),& \mathrm{if}{s}_j=1.\end{array}& \left(50\right)\end{array}$

• • [0188] The disadvantage of the LP-WBF decoding algorithm is that it only considers the reliability of bit j while ignoring the reliability of all the other bits in the check-sum s_j. To overcome this deficiency, the DWBF decoding algorithm takes into account the reliability of all the other bits in the check-sum s_j explicitly by using the following weighted check sum:

[0189] $\begin{array}{cc}{T}_l=\sum _{j\in M\left(l\right)}{T}_{j,l}{R}_{j,l}\mathrm{where}& \left(51\right)\\ R_{j,l}={\left(1+\exp \left(\frac{-4\underset{i\in N\left(j\right)\backslash l}{\min }y_i}{N_0}\right)\right)}^{-1}& \left(52\right)\end{array}$

• • [0190]  and where N(j)={i: h_j,i=1}
  • [0191] Then we flip the bit z_j in z with the smallest T_j value. Recompute the syndrome s=zH^T for this bit-flipped sequence z. If s=0, stop the decoding. Otherwise, repeat this iteration step if the number of iterations is less than the preset maximum allowable number of iterations. The decoding is terminated when it reaches its preset maximum allowable number of iterations.
    Universal Decoder for Families of Structurally Compatible Binary Quasi-Cyclic Low Density Parity Check Codes

[0192] Consider a structurally compatible family of binary Quasi-Cyclic Low Density Parity Check codes obtained using a base code C(c,t) that is the null space of a parity check matrix H_qc(c, t), which is a c×t array of b×b circulants as described above. Suppose (c_i, t_i), with 1≦i≦m, are distinct pairs of positive integers such that 1≦c₁≦c₂≦ . . . ≦c_m≦c, and 1≦t₁≦t₂≦ . . . ≦t_m≦t. Let H_qc(c_i, t_i) be the c_i×t_i subarray of the base array H_qc(c,t) of circulants obtained by deleting the last t−t_i columns and the last c−c_i rows of b×b circulant matrices, and let C(c_i, t_i) be the binary Quasi-Cyclic Low Density Parity Check code given by the null space of H_qc(c_i, t_i). So C(c,t), C(c₁, t₁), C(c₂, t₂), . . . , C(c_m, t_m) form the structurally compatible family of codes. A single universal decoder that can be used to decode all the codes in this family was devised in this universal forward error-correction coding system.

[0193] Consider the various decoding algorithms described above. The core of the OSML and weighted OSML decoding methods is check-sum computation, which is based on the parity-check matrix. Thus, the OSML and weighted OSML decoding of the family of structurally compatible binary Quasi-Cyclic Low Density Parity Check codes with parity-check matrices H_qc(c_i, t_i) can be done using the decoder implementation based on the base code H_qc(c, t) by disabling the entries corresponding to deleted rows and columns in H_qc(c, t) to the check-sum. That is, the decoder for the base code serves as the universal decoder for all codes in the structurally compatible family when OSML and weighted OSML decoding is employed. Consider next the Sum-Product Algorithm, BF, weighted BF, and the new Double-Weighted Bit Flipping (DWBF) decoding algorithms. It is clear from our previous discussions that channel decoders for a binary Quasi-Cyclic Low Density Parity Check code based on any of these decoding algorithms can be viewed as respective decoding algorithms on the Tanner Graph corresponding to the parity-check matrix of that code.

[0194] In particular, let V_i and S_i denote the set of deleted columns and the set of deleted rows in obtaining the parity check matrix H_qc(c_i, t_i) for the code C(c_i, t_i) from the parity check matrix H_qc(c, t) of the base code. Then the Tanner Graph T_i of the code C(c_i, t_i) is a subgraph of the Tanner Graph T of the base code C(c,t), which is obtained by: (1) deleting the variable nodes corresponding to the deleted columns in V_i and the edges incident on these deleted variable nodes; and (2) deleting the check-sum nodes corresponding to the deleted rows in S_i and the edges incident on these deleted check-sum nodes. Let D be the decoder built for the base code C(c,t) given by the null space of H_qc(c, t). If we deactivate the (wire) connections in decoder D that correspond to the edges incident on the deleted variable nodes and deleted check-sum nodes, we obtain a subdecoder for decoding the code C(c_i, t_i). Thus, the channel decoder for the base code serves as the universal decoder for all the codes in this structurally compatible family of Quasi-Cyclic Low Density Parity Check codes when the Sum-Product Algorithm, BF, weighted BF, or Double-Weighted Bit Flipping (DWBF) decoding methods are employed.

[0195] For an example, we consider again the codes given in Example 2 (where c=3, t=4 and c₁=2, t₁=3): the (12,5) base code C(3,4) with parity-check matrix H(3,4), and the subcode C(2,3) with parity-check matrix H(2,3) obtained by deleting the last row and last column of circulants in H(3,4). These matrices are given below for reference:

[0196] $H\left(3,4\right)=\left[\begin{array}{cccccccccccccccccc}0& 0& 1& & & 0& 0& 0& & & 1& 0& 0& & & 0& 1& 0\\ 1& 0& 0& & & 0& 0& 0& & & 0& 1& 0& & & 0& 0& 1\\ 0& 1& 0& & & 0& 0& 0& & & 0& 0& 1& & & 1& 0& 0\\ & & & & & & & & & & & & & & & & & \\ 0& 1& 0& & & 1& 0& 0& & & 0& 0& 0& & & 0& 0& 1\\ 0& 0& 1& & & 0& 1& 0& & & 0& 0& 0& & & 1& 0& 0\\ 1& 0& 0& & & 0& 0& 1& & & 0& 0& 0& & & 0& 1& 0\\ & & & & & & & & & & & & & & & & & \\ 1& 0& 0& & & 0& 1& 0& & & 0& 0& 1& & & 0& 0& 0\\ 0& 1& 0& & & 0& 0& 1& & & 1& 0& 0& & & 0& 0& 0\\ 0& 0& 1& & & 1& 0& 0& & & 0& 1& 0& & & 0& 0& 0\end{array}\right],H\left(2,3\right)=\left[\begin{array}{ccccccccccccc}0& 0& 1& & & 0& 0& 0& & & 1& 0& 0\\ 1& 0& 0& & & 0& 0& 0& & & 0& 1& 0\\ 0& 1& 0& & & 0& 0& 0& & & 0& 0& 1\\ & & & & & & & & & & & & \\ 0& 1& 0& & & 1& 0& 0& & & 0& 0& 0\\ 0& 0& 1& & & 0& 1& 0& & & 0& 0& 0\\ 1& 0& 0& & & 0& 0& 1& & & 0& 0& 0\end{array}\right].$

[0197] The Tanner Graph T for the code C(3,4) corresponding to the parity-check matrix H(3,4) is shown in FIG. 10. In this figure, the Tanner Graph T₁ for the code C(2,3) corresponding to the parity-check matrix H(2,3) is the sub-graph of T, shown by the dotted black variable nodes, dotted black check-sum nodes, and the dotted black edges. Implementation of iterative decoding, such as the Sum-Product Algorithm, DWBF, weighted BF, and BF decoding methods on the Tanner Graph T can be used to decode the base code C(3,4) corresponding to the parity-check matrix H(3,4). The Low Density Parity Check code C(2,3) corresponding to the parity-check matrix H(2,3) can be decoded by disabling the solid black variable nodes, solid black check-sum nodes, and solid black edges. This demonstrates that a single universal decoder implantation can be used to decode both codes. The same conclusion also applies to OSML and weighted OSML decoding.

General Finite Field Construction of Binary Quasi-Cyclic Low Density Parity Check Codes

[0198] A systematic method is required for generating binary Quasi-Cyclic Low Density Parity Check codes of different code rates and different blocklengths that are capable of achieving given error performance requirements. This universal forward error-correction coding system has devised a general construction method for generating well-performing binary Quasi-Cyclic Low Density Parity Check codes with a wide range of blocklengths and wide choice of coding rates that are suitable to use in the universal coding scheme. The construction method is described in the following sections. The first construction method, including examples that yield good codes, is based on a Galois field GF(q) with q elements where q is the power of a prime number. The second construction method, including corresponding examples, is based on Galois fields GF(q) where q is a prime number. Both construction methods can be employed to construct a structurally compatible family of binary Quasi-Cyclic Low Density Parity Check codes of various lengths, rates, and error performances for various channel conditions and data rates. Codes in this family can be encoded using one universal encoder and decoded with one universal decoder.

Location Vector Representations of Finite Field Elements

[0199] Consider the Galois field GF(q) with q elements where q is a power of a prime number. Let α be a primitive element of GF(q). Then the following q powers of α: α^∞=0 α⁰=1, α, α², . . . , α^q−2 form all the elements of GF(q). The field GF(q) consists of two groups, the additive and multiplicative groups. All the q elements of GF(q) under the addition operation form the additive group of GF(q), and the q−1 non-zero elements of GF(q) under the multiplication operation form the multiplicative group of GF(q). For each non-zero element αⁱ with 0≦i≦q−2, form a (q−1)-tuple over GF(2):
z(αⁱ)=(z₀,z₁, . . . ,z_q−2),
whose components correspond to the q−1 non-zero elements of GF(q), where the i-th component z_i=1 and all the other q−2 components are equal to 0. This (q−1)-tuple is referred to as the location-vector of αⁱ with respect to the multiplicative group of GF(q). We call z(αⁱ) the M-location-vector of αⁱ. The M-location vector z(0) of the zero element 0 of GF(q) is defined as the all-zero (q−1)-tuple, (0, 0, . . . , 0).

[0200] Let δ be a non-zero element of GF(q), the location vector z(αδ) of αδ is the cyclic-shift (one place to the right) of the location vector z(δ) of δ. Form a (q−1)×(q−1) matrix A over GF(2) with the M-locations-vectors of δ, αδ, α²δ, . . . , α^q−2δ as rows. Then A is a (q−1)×(q−1) circulant permutation matrix.

Construction of Row-Column Constrained Arrays of Circulant Permutation Matrices

[0201] Consider the Galois field GF(q) where q is a power of a prime number. Let α be a primitive element of GF(q). Then the powers of α: α^∞=0, α⁰=1, α, α², . . . , α^q−2, give all the elements of GF(q) and α^q−1=1. Let X be any non-zero element of GF(q). For any i ∈{−∞, 0, 1, . . . , q−2}, it is clear that αⁱX+0, αⁱX+1, αⁱX+α, . . . , αⁱX+α^q−2 are all different and form all the q elements of GF(q). Form the following q×q matrix over GF(q):

[0202] $\begin{array}{cc}\begin{array}{c}G=\left[\begin{array}{c}{g}_{-\infty }\\ g_0\\ g_1\\ ⋮\\ g_{q-2}\end{array}\right]\\ =\left[\begin{array}{ccccc}0X+0& 0X+1& 0X+\alpha & \dots & 0X+{\alpha }^{q-2}\\ X+0& X+1& X+\alpha & \dots & X+{\alpha }^{q-2}\\ \alpha X+0& \alpha X+1& \alpha X+\alpha & \dots & \alpha X+{\alpha }^{q-2}\\ ⋮& ⋮& ⋮& \ddots & ⋮\\ {\alpha }^{q-2}X+0& {\alpha }^{q-2}X+1& {\alpha }^{q-2}X+\alpha & \dots & {\alpha }^{q-2}X+{\alpha }^{q-2}\end{array}\right]\end{array}& \left(53\right)\end{array}$