Constant voltage circuit

[0001] 1. Field of the Invention

[0002] The present invention generally relates to a constant voltage circuit of a whole category of electronic equipment aboard a computerized personal organizer, a handset, a voice recognition device, a voice memory device, and a computer, etc.

[0003] 2. Discussion of the Background

[0004] At present, energy saving has been actively promoted to protect environment. For battery-powered electrical equipment, such as mobile phones, digital cameras, etc., energy saving is especially important to prolong battery life. Such portable equipment typically uses a constant voltage circuit.

[0005] In constant voltage circuits, in order to quickly respond to fluctuations in output voltage, a bias electrical current, which is hereinafter simply referred to as bias current, in a differential amplifier circuit is typically increased.

[0006] However, increasing the bias current causes the constant voltage circuit to consume a greater amount of electrical current.

[0007] In view of the foregoing, in a known method, the bias current in the differential amplifier circuit is increased in proportion to the output voltage.

[0008] However, phase compensation is difficult in this method because the bias current of the differential amplifier continuously changes. Further, response speed is relatively slow when the output electrical current changes abruptly.

[0009] FIG. 1 is a circuit diagram illustrating a known constant voltage circuit that increases bias current of a differential amplifier circuit unit when an output electrical current reaches a predetermined or given value.

[0010] As shown in FIG. 1, a constant voltage circuit 100 includes an output transistor M101, PMOS (P-channel Metal Oxide Semiconductor) transistors M102, M103, and M107, NMOS (N-channel Metal Oxide Semiconductor) transistors M104, M105, and M106, a comparator CMP, and resistors R101, R102, and R103.

[0011] The constant voltage circuit 100 supplies a drain current of the PMOS transistor M107 that is in proportion to a drain current of the output transistor M101 to the resistor R103. The comparator CMP outputs a high level signal when a decrease in a voltage of the resistor R103 exceeds a reference voltage Vs.

[0012] When the comparator CMP outputs the high level signal, the NMOS transistor M106 turns on, which adds a constant current ib from a current source to a bias current ia of the differential amplifier circuit, thus increasing the bias current.

[0013] Although the constant voltage circuit 100 shown in FIG. 1 can respond more quickly to abrupt changes in the output electrical current, it is difficult to maintain a high degree of accuracy of the resistor R103 when the constant voltage circuit 100 is an integrated circuit (IC). Consequently, it is difficult to set the output electrical current accurately when the bias current is switched.

[0014] The output electrical current when the bias current is switched can be set accurately using a resistor capable of trimming as the resistor R103. However, using such a resistor will increase the cost because an IC chip having a broader area and capable of supporting a trimming process are necessary.

[0015] Another known constant voltage circuit detects an output electrical current value based on differences in voltage between both input terminals of a differential amplifier circuit and increases the bias current of the differential amplifier when the voltage difference exceeds a predetermined voltage.

[0016] In this constant voltage circuit, because changes in temperature and variations in production process conditions can cause the voltage between a gate and a source of a MOS (Metal Oxide Semiconductor) transistor to fluctuate, it is difficult to set a relation between the output electrical current and the voltage difference between the two input terminals of the differential amplifier circuit accurately.

[0017] Further, this constant voltage circuit includes two more differential amplifier circuits in order to measure the voltage difference between the two input terminals of the first differential amplifier circuit, and detects the predetermined voltage using input offset voltage of those two differential amplifier circuits.

[0018] However, it is difficult to accurately set the output electrical current at which the bias current is switched similarly to the constant voltage circuit 100 shown in FIG. 1, because the input offset voltage described above fluctuates depending on temperature and production process conditions.

[0019] In view of the foregoing, in one illustrative embodiment of the present invention, a constant voltage circuit is configured to convert voltage input to an input terminal and output a predetermined constant voltage from an output terminal. The constant voltage circuit includes an output transistor, a differential amplifier circuit, a current mirror circuit, and a voltage comparator. The output transistor outputs an electrical current that corresponds to a control signal input thereto to the output terminal. The current mirror circuit serves as a load of a pair of input transistors included in the differential amplifier circuit. The voltage comparator compares a voltage at a control electrode of a transistor included in the current mirror circuit and a voltage of the control signal. The differential amplifier circuit controls a bias electrical current supplied to the pair of input transistors according to a comparison result generated by the voltage comparator and outputs the control signal according to a difference between a comparative voltage proportional to the voltage output from the output terminal and a predetermined reference voltage.

[0024] In describing preferred embodiments illustrated in the drawings, specific terminology is employed for the sake of clarity. However, the disclosure of this patent specification is not intended to be limited to the specific terminology so selected and it is to be understood that each specific element includes all technical equivalents that operate in a similar manner.

[0025] Referring now to the drawings, wherein like reference numerals designate identical or corresponding parts throughout the several views thereof, and particularly to FIG. 2, an example of a constant voltage circuit according to an illustrative embodiment of the present invention is described.

[0026] Referring to FIG. 2, a constant voltage circuit 1 serves as a series regulator that converts an input voltage V_in that is input to an input terminal IN into a predetermined or given constant voltage to be output from an output terminal OUT as an output voltage V_out.

[0027] As shown in FIG. 2, the constant voltage circuit 1 further includes a reference voltage generating circuit 2, resistors R1 and R2, an output transistor M1, a differential amplifier circuit 3, and a hysteresis comparator 4.

[0028] The reference voltage generating circuit 2 generates a predetermined or given reference voltage V_ref and outputs the reference voltage V_ref to the differential amplifier circuit 3.

[0029] The resistors R1 and R2 are connected in series between the output terminal OUT and a ground voltage Vss and serve as a voltage divider that divides the output voltage V_out so as to generate a divided voltage V_fb. A potential at a node N1 between the resistor R1 and the resistor R2 is output as the divided voltage V_fb and used as a reference voltage to detect the output voltage V_out.

[0030] The output transistor M1 can be a PMOS transistor, for example, and regulates an electrical current i_out that is output to the output terminal OUT according to a signal input to a gate of the output transistor M1. The electrical current i_out is hereinafter referred to as the output current i_out. A source of the output transistor M1 connects to the input terminal IN at an identical or similar potential, and a drain thereof connects to the output terminal OUT at an identical or similar potential.

[0031] The differential amplifier circuit 3 controls the output transistor M1 so that the divided voltage V_fb is equalized at or close to the reference voltage V_ref, and operates in conjunction with the hysteresis comparator 4 as a differential amplifier circuit unit.

[0032] As shown in FIG. 2, the differential amplifier circuit 3 includes PMOS transistors M2 and M3; NMOS transistors M4, M5, and M6; and constant current sources 11 and 12. The constant current sources 11 and 12 supply predetermined or given constant electrical currents i₁ and i₂, respectively.

[0033] The reference voltage V_ref is input to an inverting input terminal of the differential amplifier circuit 3, and the divided voltage V_fb is input to a non-inverting input terminal thereof. An output terminal of the differential amplifier circuit 3 connects to the gate of the output transistor M1.

[0034] The NMOS transistors M4 and M5 are input transistors that operate in conjunction as a differential pair. A gate of the NMOS transistor M4 functions as an inverting input terminal to which the reference voltage V_ref is input, and a gate of the NMOS transistor M5 functions as a non-inverting input terminal to which the divided voltage V_fb is input.

[0035] The PMOS transistors M2 and M3 form a mirror circuit that serves as a load of the differential pair. Sources of the PMOS transistors M2 and M3 connect to the input voltage V_in at an identical or similar potential. Gates of the PMOS transistors M2 and M3 and a drain of the PMOS transistor M2 connect to each other at an identical or similar potential.

[0036] The drain of the PMOS transistor M2 further connects to a drain of the NMOS transistor M5 at an identical or similar potential. A drain of the PMOS transistor M3 connects to a drain of the NMOS transistor M4 at an identical or similar potential, forming a connection that serves as the output terminal of the differential amplifier circuit 3 and connects to the gate of the output transistor M1.

[0037] Sources of the NMOS transistors M4 and M5 connect to each other at an identical or similar potential, and the constant current source 11 is located between a node between the sources of the NMOS transistors M4 and M5 and the ground potential Vss. The constant current source 11 is connected in parallel to the NMOS transistor M6 and the constant current source 12, which are connected serially.

[0038] A drain of the NMOS transistor M6 connects to each of the sources of the NMOS transistors M4 and M5 at an identical or similar potential, and a source of the NMOS transistor M6 connects to the constant current source 12. A gate of the NMOS transistor M6 connects to an output terminal of the hysteresis comparator 4.

[0039] The hysteresis comparator 4 functions as a voltage comparator in the differential amplifier circuit unit. A non-inverting input terminal of the hysteresis comparator 4 connects to the gate of the PMOS transistor M2 at an identical or similar potential, and an inverting input terminal thereof connects to the gate of the output transistor M1 at identical or similar potential.

[0040] In the configuration described above, when a voltage at the gate (gate voltage) of the output transistor M1 decreases to a voltage lower than a gate voltage of the PMOS transistor M2, the hysteresis comparator 4 raises an output signal to high, turning the NMOS transistor M6 on.

[0041] When the NMOS transistor M6 is on, a bias current supplied to the NMOS transistors M4 and M5 increases from the constant electrical current i₁ to a sum of the constant electrical current i₁ and i₂.

[0042] Voltages between the gate and source of each of the output transistor M1 and the PMOS transistor M2 are described below.

[0043] The voltages between the gate and source of the output transistor M1 and the PMOS transistor M2 are hereinafter referred to as gate/source voltages V_gs1 and V_gs2, respectively, and are respectively expressed by formulas 1 and 2 shown below:
V_gs1=V_th+(2×i_d1/β1)0.5  (1)
V_gs2=V_th+(2×i_di/β2)0.5  (2)
wherein Vth represents a threshold voltage of the PMOS transistor M2, i_d1 represents an electrical current at the drain (hereinafter drain electrical current) of the output transistor M1, which is close to the output current i_out, and i_d2 represents a drain electrical current of the PMOS transistor M2.

[0044] Further, β1 and β2 described above are respectively defined as follows:
β1=μ×COX×W1/2×L1  (3)
β2=μ×COX×W2/2×L2  (4)
wherein μ represents mobility, COX represents a gate oxide film capacity, W1 represents a width of the gate of the output transistor M1, L1 represents a length of the gate of the output transistor M1, W2 represents a width of the gate of the PMOS transistor M2, and L2 represents a length of the gate of the PMOS transistor M2.

[0045] FIG. 3 illustrates an example of relations between the drain electrical current i_d1 of the output transistor Ml, the gate/source voltage V_gs1 of the output transistor M1, and the gate/source voltage V_gs2 of the PMOS transistor M2.

[0046] It is to be noted that the gate/source voltages V_gs1 and V_gs2 are shown with reference to the input voltage V_in.

[0047] Further, it is to be noted that, alternatively, the output current i_out can be used instead of the drain electrical current id1 of the output transistor M1 because they are substantially equal to each other.

[0048] In FIG. 3, a dashed line indicates the gate/source voltage V_gs1 of the output transistor M1, and a solid line indicates the gate/source voltage V_gs2 of the PMOS transistor M2.

[0049] When the drain electrical current i_d1 is 0 ampere, V_gs1=V_th and V_gs2=V_th+(2×id1/β2)0.5, and thus V_gs1<V_gs2.

[0050] Because a voltage at the source (source voltage) of each of the output transistor M1 and the PMOS transistor M2 is identical or similar to the input voltage V_in, when the drain electrical current i_d1 increases, the gate/source voltage V_gs1 increases and the gate/source voltage V_gs2 decreases.

[0051] Then, when the voltage at the gate (gate voltage) of the output transistor M1 increases and the gate voltage of the PMOS transistor M2 decreases to an extent that the gate/source voltage V_gs1 equals the gate/source voltage V_gs2, the hysteresis comparator 4 switches its output signal. Thus, when the output signal of the hysteresis comparator 4 is high, the NMOS transistor M6 turns on.

[0052] The bias current of the differential amplifier circuit 3 increases according to the mechanism described above.

[0053] It is assumed that the drain electrical current i_d1 of the output transistor M1 and the drain electrical current i_d2 under the conditions described above are i_d1a and i_d2a, respectively. Because the gate/source voltage V_gs1 equals the gate/source voltage V_gs2, formula 5 shown below can be obtained from formulas 1 and 2 described above.
V_th+(2×i_d1a/β1)0.5=V_th+(2×i_d2a/β2)0.5   (5)

[0054] When identical elements are deleted from both sides of formula 5, formula 6 shown below is obtained.
(i_d1a/β1)0.5=(i_d2a/β2)0.5  (6)

[0055] Further, when β1 and β2 described in formula 3 and 4 are applied to formula 6, formula 7 shown below is obtained.
i_d1a/(W1/L1)=i_d2a/(W2/L2)  (7)

[0056] From formula 7, formula 8 that defines the drain electrical current i_d1a of the output transistor M1 is obtained as shown below.
i_d1a=i_d2a×(W1/L1)/(W2/L2)  (8)

[0057] The gate voltage of the output transistor M1 is identical or similar to a drain voltage of the PMOS transistor M3, and the drain voltage and the gate voltage of the PMOS transistor M2 are identical or similar to each other.

[0058] Therefore, when the gate/source voltage V_gs1 is identical or similar to the gate/source voltage V_gs2, the drain voltage of the PMOS transistor M2 is identical or similar to that of the PMOS transistor M3. Further, because the gates of the PMOS transistors M2 and M3 connect to each other and are at an identical or similar voltage, the drain electrical current of the PMOS transistor M2 is identical or similar to that of the PMOS transistor M3.

[0059] Because the PMOS transistors M2 and M3 form a current mirror circuit as described above, when a sum of their drain electrical currents is identical or similar to the constant current i₁, that is, when the NMOS transistor M6 is off, the drain electrical current id2a of the PMOS transistor M2 is half the constant current i₁ (i₁/2) when the gate-source voltage V_gs1 equals the gate-source voltage V_gs2(V_gs1=V_gs2).

[0060] By applying this value to formula 8 described above, the drain electrical current id1a at which the bias current is increased is expressed by formula 9 shown below.
i_d1a=(i₁/2)×(W1×L2)/(W2×L1)  (9)

[0061] It is to be noted that a bias current of an amplifier circuit used in a semiconductor device is typically settable with a higher degree of accuracy, and a width and a length of a gate of a MOS transistor is settable with a higher degree of accuracy.

[0062] Thus, the right side of formula 9 can be set with a higher degree of accuracy, and the drain electrical current id1a at which the bias current of the differential amplifier circuit 3 is increased can be set with a higher degree of accuracy.

[0063] Further, because the drain electrical current id1 substantially equals to the output current i_out, the constant voltage circuit 1 according to the present embodiment can set the output electrical current at which the bias current is increased with a higher degree of accuracy.

[0064] It is to be noted that, when the bias current of the differential amplifier circuit 3 increases, the drain electrical current id2 of the PMOS transistor M2 increases according to the increase in that bias current.

[0065] Therefore, the gate/source voltage V_gs2 of the PMOS transistor M2 changes as indicated by a downward arrow shown in FIG. 3. Hereinafter, the amount of change in the gate/source voltage V_gs2 is referred to as a voltage change amount ΔV. Subsequently, the voltage at the non-converting input terminal of the hysteresis comparator 4 decreases.

[0066] The hysteresis comparator 4 provides a hysteresis voltage V_os shown in FIG. 3 in order to prevent the output signal from being switched due to the decrease in the voltage at the non-converting input terminal of the hysteresis comparator 4.

[0067] The constant voltage circuit 1 can operate reliably because of the hysteresis characteristic of the hysteresis comparator 4 the described above.

[0068] It is to be noted that, although a comparator without hysteresis characteristics is usable instead of the hysteresis comparator 4, the hysteresis comparator 4 is preferable for reliable operation of the constant voltage circuit 1.

[0069] As shown in FIG. 3, the hysteresis voltage V_os is set to a voltage slightly higher than the voltage change amount ΔV. When the drain electrical current id1 decreases, the hysteresis comparator 4 turns the output signal low when a sum of the gate/source V_gs1 and the hysteresis voltage V_os (V_gs1+V_os) is equal to or less than the gate/source V_gs2.

[0070] Subsequently, the NMOS transistor M6 turns off, and the bias current of the differential amplifier circuit 3 is equal or similar to the constant electrical current i₁, which causes the gate/source voltage V_gs2 of the PMOS transistor to increase as indicated by an upward arrow shown in FIG. 3. In this state, the voltage change amount ΔV is equal or similar to the hysteresis voltage V_os.

[0071] As described above, the constant voltage circuit 1 according to the present embodiment can set the value of the output current i_out at which the bias current of the differential amplifier circuit 3 is increased based on the bias current (constant current i₁), and the widths and lengths of the gates of the MOS transistors, which are parameters settable with a higher degree of accuracy.

[0072] Therefore, in the present embodiment, electrical current consumption can be reduced, response speed to abrupt changes in the output electrical current can be increased, and the value of the output current at which the bias current of the differential amplifier circuit is increased can be set more accurately.

[0073] Numerous additional modifications and variations are possible in light of the above teachings. It is therefore to be understood that, within the scope of the appended claims, the disclosure of this patent specification may be practiced otherwise than as specifically described herein.

[0074] This patent specification is based on Japanese Patent Application No. 2007-235372, filed on Sep. 11, 2007 in the Japan Patent Office, the entire contents of which are hereby incorporated by reference herein.