CCFL controller with multi-function terminal

[0001] This application claims priority from U.S. Provisional Patent Application Ser. No. 61/055,989 filed May 25, 2008, entitled “CCFL Controller with Multi-Function Terminal”, the entire contents of which is incorporated herein by reference.

[0002] The invention relates generally to integrated circuits, and in particular to a cold cathode fluorescent lamp controller exhibiting a multi-function terminal.

[0003] Cold Cathode Fluorescent Lamps (CCFL) are extensively used today as backlights for computer liquid crystal displays (LCD) and LCD televisions. In certain embodiments CCFL lamps are driven in a push pull configuration such that current flows alternatively in each direction to ensure long life and uniform operation. A CCFL driver, and a controller operative with such a driver preferably provides a pair of complementary drive signals which are out of phase with each other. Typically, a CCFL driver requires a pair of driving signals which are 180° out of phase with each other, however this is not meant to be limiting in any way and 90° phase difference is also required in some particular applications.

[0004] Systems that use a plurality of CCFL lamps for a single display require synchronization between the CCFL drivers so as to avoid interference caused by non-synchronized operation. Further synchronization is often required with a system display signal, such as a video scanning signal, associated with a horizontal scanning frequency, so as to avoid a water wave effect. Such synchronization is required for single and multiple CCFL driver systems and thus requires an input terminal for receipt of any synchronization signal. Synchronization is typically accomplished with a phase locked loop which typically requires an external filtering capacitor accessed via another input terminal.

[0005] Ignition of a CCFL, also known as striking, requires a high voltage applied for a short period of time to ionize the gas within the fluorescent tube. Once ignition has been achieved a lower voltage is sufficient to maintain the CCFL in an on condition, known as the run state. CCFLs are often driven by a converter circuit, responsive to a CCFL controller, operative to convert an input DC signal to the AC waveform required to drive the CCFL in either the strike mode or the operating mode.

[0006] U.S. Pat. No. 6,979,959 issued Dec. 27, 2005 to Henry, the entire contents of which is incorporated herein by reference, is addressed to a lamp inverter with a continuous strike voltage exhibiting a frequency sweep generator. The frequency sweep generator sweeps the frequency of the lamp inverter to a striking frequency corresponding to a striking lamp voltage and then maintains the striking frequency until the lamp strikes. In certain embodiments, the frequency sweep generator is responsive to a voltage across an external capacitor, whose charge over time increases resulting in the sweeping of the frequency of the sweep generator. Such a capacitor is typically user selected, and of a value too large to be economically integrated within an integrated circuit. Thus, striking using a swept frequency requires an additional input terminal.

[0007] An integrated circuit providing the electronic control for striking and running the CCFL is termed hereinafter a CCFL controller.

[0008] A soft start function is also typically supported, which prevents start up over shoot during the strike mode. Such an over shoot is typically the result of an error amplifier indicating that substantially no current is flowing during strike mode until the lamp lights, and thus calling for increased on time for a pulse width modulation circuit. In the absence of a soft start function, upon ignition of the lamp a maximal amount of current will flow without limitation until the error amplifier senses the overflow and acts to reduce the current flow. Such a soft start function typically thus requires a timing capacitor, with yet additional associated input terminal.

[0009] In the event of an error condition being sensed by the CCFL controller, it would be advantageous to supply an error signal which may be sensed by the system electronics. Such an error signal requires yet another associated terminal.

[0010] In electronics the cost of each terminal of integrated circuit adds cost. Thus, it would be desirable to provided a multi-function terminal arranged to serve in place of at least some of the dedicated terminals of the prior art.

[0011] According to certain embodiments of the present invention, a cold cathode fluorescent lamp controller is provided exhibiting a multi-function terminal and operative alternately in a strike mode and a run mode. In certain embodiments the controller comprises: a phase locked loop arranged for synchronization of an oscillator, associated with the controller, with an external signal, the phase locked loop comprising a capacitor coupled to the multi-function terminal; and a soft start circuit arranged to limit drive current immediately after reset of the controller responsive to a signal at the multi-function terminal.

[0012] In one particular embodiment the cold cathode fluorescent lamp controller further comprises a frequency sweeping circuit operative to sweep the frequency of the drive signal output during the strike mode. The frequency sweeping circuit is preferably operative to sweep the frequency responsive to a signal at the multi-function terminal

[0013] In one particular embodiment, the cold cathode fluorescent lamp controller further comprises an error detection circuit, operative to detect an error in operation such as a failure of the lamp to be ignited or a persistent over current or over voltage condition. In the event of an error condition, an error signal is asserted at the multi-function terminal. Thus, in such an embodiment the multi-function terminal is further an output terminal of the cold cathode fluorescent lamp controller.

[0014] Additional features and advantages of the invention will become apparent from the following drawings and description.

[0023] The present embodiments enable a cold cathode fluorescent lamp controller exhibiting a multi-function terminal and operative alternately in a strike mode and a run mode. In certain embodiments the controller comprises: a phase locked loop arranged for synchronization of an oscillator, associated with the controller, with an external signal, the phase locked loop comprising a capacitor coupled to the multi-function terminal; and a soft start circuit arranged to limit drive current immediately after reset of the controller responsive to a signal at the multi-function terminal.

[0024] In one particular embodiment the cold cathode fluorescent lamp controller further comprises a frequency sweeping circuit operative to sweep the frequency of the drive signal output during the strike mode. The frequency sweeping circuit is preferably operative to sweep the frequency responsive to a signal at the multi-function terminal

[0025] In one particular embodiment, the cold cathode fluorescent lamp controller further comprises an error detection circuit, operative to detect an error in operation such as a failure of the lamp to be ignited or a persistent over current or over voltage condition. In the event of an error condition, an error signal is asserted at the multi-function terminal. Thus, in such an embodiment the multi-function terminal is further an output terminal of the cold cathode fluorescent lamp controller.

[0026] Before explaining at least one embodiment of the invention in detail, it is to be understood that the invention is not limited in its application to the details of construction and the arrangement of the components set forth in the following description or illustrated in the drawings. The invention is applicable to other embodiments or of being practiced or carried out in various ways. Also, it is to be understood that the phraseology and terminology employed herein is for the purpose of description and should not be regarded as limiting.

[0027] FIG. 1 illustrates a high level functional block diagram of an embodiment of a CCFL controller 10, with associated inverters 20 and a CCFL 30 in accordance with certain embodiments. CCFL controller 10 comprises: a control logic 50 comprising therein a power on reset functionality 60; a frequency sweeping functionality 70; an oscillator 80; a synchronization functionality 90; an error amplifier and error logic functionality 100; a soft start functionality 110; a driver 120; and a bias circuit 130 generating a regulated voltage VDD. CCFL controller 10 further exhibits a plurality of terminals denoted respectively C-R, SYNC, COMP, BRT, ISNS, MFT, AOUT, BOUT, VDDT, VIN and ENABLE, with terminal MFT being a multi-function terminal.

[0028] Control logic 50 operates CCFL controller 10 in one of 2 modes, a strike mode and a run mode, with the modes being implemented responsive to a pair of outputs denoted STRIKE and RUN. In one embodiment, a single output is provided with its complement being taken as the second output. For example, in one embodiment a single RUN output is provided, and in the absence of an active signal on the RUN output a STRIKE mode is understood. In another embodiment a single STRIKE output is provided, and in the absence of an active signal on the STRIKE output a RUN mode is understood.

[0029] Each of multi-function terminal MFT and terminal COMP have coupled thereto a respective external capacitor to ground, denoted respectively C_MFT and C_COMP. Terminal C-R has coupled thereto a first end of a resistor R_EX, whose second end is coupled to regulated voltage VDD, and a first end of a capacitor C_EX, whose second end is coupled to a ground terminal, or other common point.

[0030] The term ground, as used throughout this document, is directed towards a common point, which need not necessarily be coupled to physical ground or a chassis ground.

[0031] The STRIKE output of control logic 50 is coupled to an input of frequency sweeping functionality 70 and to an input of soft start functionality 110. The RUN output of control logic 50 is coupled to an input of synchronization functionality 90.

[0032] The output of frequency sweeping functionality 70 is coupled as a control input to oscillator 80, and an input of frequency sweeping functionality 70 is coupled to multi-function terminal MFT. Respective connections of synchronization functionality 90 are coupled to an external synchronization signal via terminal SYNC, to multi-function terminal MFT and to an input of oscillator 80. Oscillator 80 is coupled to terminal C-R and to an input of driver 120. Inputs of error amplifier and error logic functionality 100 are respectively coupled to each of terminal COMP, terminal BRT and terminal ISNS, one output of error amplifier and error logic functionality 100 is coupled to an input of driver 120 and to soft start functionality 110 and one output of error amplifier and error logic functionality 100, denoted ERROR is coupled to an input of control logic 50 and to multi-function terminal MFT.

[0033] Driver 120 exhibits a pair of outputs coupled respectively via terminals AOUT and BOUT to inputs of respective inverters 20. Inverters 20 are arranged to drive alternately both ends of CCFL 30.

[0034] Bias circuit 130 exhibits a control input terminal coupled to the ENABLE terminal, a power input terminal coupled to the VIN terminal, and an output terminal exhibiting regulated voltage VDD coupled to the VDDT terminal. Bias circuit 130 is operative responsive to an active signal at the ENABLE terminal to generate a regulated voltage VDD appearing at terminal VDDT from an input voltage appearing at terminal VIN. Terminal VDDT is preferably externally supplied with a low ESR decoupling capacitor, connected to ground, of not less than 1 μF with low impedance traces. In an alternative embodiment (not shown) an external regulated voltage can be supplied to terminal VDD, which is then connected directly to the voltage input pin VIN thereby overriding the internal voltage regulator.

[0035] The above listing of terminals is not meant to be limiting in any way. In one embodiment additional terminals are provided for one or more of: a ground connection; a voltage sense input arranged to sense a voltage condition associated with the output, preferably associated with CCFL 30; a lamp strike time and/or fault protection time RC timing circuit; a burst dimming frequency RC timing circuit; and a burst dimming control input operative to select a continuous analog brightness control mode responsive to a first range of input values, a direct duty cycle control mode responsive to a second range of input values, and a disable input responsive to a third range of values.

[0036] In particular embodiments each of power on reset functionality 60, frequency sweeping functionality 70, synchronization functionality 90, error amplifier and error logic functionality 100 and soft start functionality 110 are implemented in dedicated circuitry, denoted respectively power on reset circuitry 60, frequency sweeping circuitry 70, synchronization circuitry 90, error amplifier and error logic circuitry 100 and soft start circuitry 110, however this is not meant to be limiting in any way. In other embodiments one or more of power on reset functionality 60, frequency sweeping functionality 70, synchronization functionality 90, error amplifier and error logic functionality 100 and soft start functionality 110 are implemented by general purpose logic or electronic circuits, such as a micro-controller, micro-computer or programmable gate array without exceeding the scope of the invention. For ease of understanding, an implementation of an embodiment of the functional block diagram of controller 10 will be described below in relation to specific circuitry of FIGS. 2-5.

[0037] In operation, power on reset functionality 60 of control logic 50 senses a power on reset condition, and ensures that all circuitry of control logic 50 is functioning prior to beginning operation. Additionally, in one embodiment power on reset functionality 60 further acts to discharge capacitor C_MFT, via a switch (not shown) to ground. Control logic 50 then asserts the STRIKE mode, preferably by asserting an active signal on the STRIKE output.

[0038] Frequency sweeping functionality 70 is operative in the STRIKE mode to sweep the frequency of oscillator 80 responsive to a signal at multi-function terminal MFT. In one embodiment, a current source is provided as part of one of soft start functionality 110 and frequency sweep functionality 70, operative to charge capacitor C_MFT at a controlled rate thereby providing a controlled frequency sweep. Sweeping the frequency of oscillator 80 advantageously seeks the resonant frequency of the circuit containing CCFL 30 so as to provide an appropriate striking voltage across CCFL 30 for ignition.

[0039] Soft start functionality 110 is operative in the STRIKE mode to limit the input received by driver 120 from error amplifier and error logic functionality 100. In particular, error amplifier and error logic functionality 100 is operative to compare a brightness request signal appearing at terminal BRT with a current sense signal, coupled to represent current through CCFL 30, appearing at terminal ISNS, and control the duty cycle of the outputs of driver 120 so as to compensate for any undercurrent condition. During STRIKE mode, until ignition of CCFL 30 occurs, no appreciable current is sensed at ISNS, and thus error amplifier and error logic functionality 100 would signal driver 120 to output at a maximum duty cycle. Unfortunately, upon ignition of CCFL 30, an overshoot condition may then occur. This overshoot condition is controlled by soft start functionality 110 as described above. In one embodiment the BRT terminal represents an analog brightness control input.

[0040] In one embodiment, during the STRIKE mode, error amplifier and error logic functionality 100 is further operative to sense a voltage component across CCFL 30, to monitor the current through CCFL 30 sensed via terminal ISNS, and to monitor the duration of the STRIKE mode. In the event that the STRIKE mode duration exceeds a predetermined value, the voltage exceeds a predetermined limit for a predetermined maximum time period, or the current sensed via terminal ISNS exceeds a predetermined limit for a predetermined maximum time period, an error condition is noted on output ERROR, which is preferably output at multi-function terminal MFT to be sensed by an external control circuitry (not shown). Control logic 50 is further operative to shut down operation responsive to an active signal appearing on the ERROR output of error amplifier and error logic functionality 100.

[0041] In the event that ignition of CCFL 30 is sensed by control logic 50, control logic 50 asserts the RUN mode, preferably by asserting an active signal on the RUN output, and de-asserting an active signal from the STRIKE output. Soft start functionality 110 and frequency sweeping functionality 70 shut down responsive to the RUN mode and synchronization functionality 90 becomes active. Synchronization functionality 90 is operative to detect a synchronization signal appearing at terminal SYNC, and if present, to synchronize the operation of oscillator 80 to the synchronization signal at terminal SYNC. In one embodiment, synchronization functionality 90 is embodied in a phase locked loop (PLL). Synchronization functionality 90 is coupled to multi-function terminal MFT, and utilizes capacitor C_MFT as a low pass filter to reduce response to transients and noise.

[0042] In one embodiment, during RUN mode, error amplifier and error logic functionality 100 is further operative to sense a voltage component across CCFL 30 and to monitor the current through CCFL 30 sensed via terminal ISNS. In the event that the voltage exceeds a predetermined limit for a predetermined maximum time period, or the current sensed via terminal ISNS exceeds a predetermined limit for a predetermined maximum time period, an error condition is noted on output ERROR, which is preferably output at multi-function terminal MFT to be sensed by an external control circuitry (not shown). Control logic 50 is further operative to shut down operation responsive to an active signal appearing on the ERROR output of error amplifier and error logic functionality 100.

[0043] FIG. 2 illustrates a high level schematic diagram of an embodiment of CCFL controller 10 of FIG. 1 in accordance with certain embodiments comprising: a plurality of switches denoted SW₁, SW₂, SW₃, SW₄ and SW₅, each arranged to be closed electronically responsive an active input signal; a plurality of AND gates denoted respectively AND₁, AND₂ and AND₃, a plurality of flip flops denoted respectively FF₁, FF₂, FF₃ and FF₄ of which flip flop FF₁ is an S-R type and flip flops FF₂, FF₃ and FF₄ are D types; a plurality of op-amps denoted respectively AMP₁ and AMP₂; a plurality of buffers denoted BUFF; a current mirror denoted CM; a plurality of FET switches, denoted respectively Q₁, Q₂ and Q₃; a current source denoted CS; a plurality of transconductance amplifiers denoted respectively GM₁ and GM₂; a plurality of comparators denoted respectively COMP₁, COMP₂ and COMP₃; an exclusive OR gate denoted EXOR; a diode D₁; and a synchronization signal detection logic 150. Terminals C-R, SYNC, AOUT, BOUT, ISNS, BRT, COMP and MFT are further illustrated, as described above in relation to FIG. 1, including their respective capacitors, (C_EX, C_COMP, C_MFT) and resistor (R_EX).

[0044] Terminal SYNC is coupled to the input of synchronization signal detection logic 150 and to the clocking input of flip flop FF₄. The output of synchronization signal detection logic 150, denoted NO SYNC, is coupled via an inverter to a first input of AND gate AND₁. The Q bar output of flip flop FF₄ is coupled to the D input of flip flop FF₄, and the Q output of flip flop FF₄ is coupled to a first input of exclusive OR gate EXOR.

[0045] Terminal C-R is coupled to: the inverting input of comparator COMP₂; the non-inverting input of comparator COMP₁; a first end of switch SW₁; a first end of switch SW₂; and the drain of FET switch Q₁. The source of FET switch Q₁ is coupled to ground, and the gate of FET switch Q₁ is coupled to the Q output of flip flop FF₁. As described above in relation to FIG. 1, terminal C-R has further coupled thereto a first end of resistor R_EX, whose second end is coupled to regulated voltage VDD and a first end of capacitor C_EX, whose second end is coupled to a ground terminal.

[0046] The inverting input of comparator COMP₁ is coupled to a predetermined voltage point, particularly 2.5 Volts, although other values may be selected as required. The non-inverting input of comparator COMP₂ is coupled to a predetermined voltage point, particularly 0.5 Volts, although other values may be selected as required. The output of comparator COMP₁ is connected to the set input of flip flop FF₁ and the output of comparator COMP₂ is connected to the reset input of flip flop FF₁.

[0047] The Q bar output of flip flop FF₁ is coupled to the clocking input of flip flop FF₂. The Q bar output of flip flop FF₂ is coupled to the D input of flip flop FF₂, and to a first input of AND gate AND₂. The Q output of flip flop FF₂ is coupled to the clocking input of flip flop FF₃ and to a first input of AND gate AND₃. The Q bar output of flip flop FF₃ is coupled to the D input of flip flop FF₃, and the Q output of flip flop FF₃ is coupled to the second input of exclusive OR gate EXOR.

[0048] The output of exclusive OR gate EXOR is coupled via a resistor to a first end of switch SW₃. The control input of switch SW₃ is coupled to the RUN output of control logic 50 of FIG. 1. The second end of switch SW₃ is coupled to multi-function terminal MFT, the inverting input of transconductance amplifier GM₁, the non-inverting input of op-amp AMP₁, the drain of FET switch Q₃, the non-inverting input of op-amp AMP₂ and a first end of switch SW₄. As described above in relation to FIG. 1, multi-function terminal MFT is further coupled to a first end of capacitor C_MFT, and the second end of capacitor C_MFT is coupled to ground.

[0049] The source of FET switch Q₃ is coupled to ground, and the gate of FET switch Q₃ is coupled to the ERROR output of error amplifier and error logic functionality 100 of FIG. 1. The control input of switch SW₄ is coupled to the STRIKE output of control logic 50 of FIG. 1, and the second end of switch SW₄ is coupled to the output of current source CS. In one particular embodiment, current source CS is a 2.5 μA current source, which is low enough to ensure, in cooperation with a properly sized capacitor C_MFT a slowly rising voltage during charging of capacitor C_MFT. In one particular embodiment, capacitor C_MFT is constituted of a 0.1 μF capacitor appropriate for use with the 2.5 μA current source of current source CS. The input of current source CS is coupled to regulated voltage VDD.

[0050] The inverting input of op-amp AMP₁ is coupled to the source of FET switch Q₂ and to a first end of a resistor, whose second end is coupled to ground. The output of op-amp AMP₁ is coupled to the gate of FET switch Q₂, and the drain of FET switch Q₂ is coupled to the reference current input of current mirror CM. Current mirror CM is implemented as a pair of FETs, whose drains are commonly coupled to regulated voltage VDD, and whose gates are commonly coupled to the drain of FET switch Q₂. The source of a first one of the FETs of current mirror CM, representing the reference current input, is coupled as described above to the drain of FET switch Q₂. The source of a second one of the FETs of current mirror CM is coupled to a second end of switch SW₁. The control input of switch SW₁ is coupled to the STRIKE output of control logic 50 of FIG. 1.

[0051] The non-inverting input of transconductance amplifier GM₁ is coupled to a fixed voltage reference. In one particular embodiment, the fixed voltage reference is VDD/2, i.e. ½ of the source voltage thereby providing a wide working range for transconductance amplifier GM₁. The output of transconductance amplifier GM₁ is coupled to a second end of switch SW₂. The RUN output of control logic 50 of FIG. 1 is coupled to a second input of AND gate AND₁, and the output of AND gate AND₁ is coupled to the control input of switch SW₂.

[0052] The inverting input of op-amp AMP₂ is coupled to the anode of diode D1 and to a first end of switch SW₅. The output of op-amp AMP₂ is coupled to the cathode of diode D1 and the control input of switch SW₅ is coupled to the STRIKE output of control logic 50 of FIG. 1. A second end of switch SW₅ is coupled to the non-inverting input of comparator COMP₃, the output of transconductance amplifier GM₂, and terminal COMP. The inverting input of comparator COMP₃ is coupled to terminal C-R and the output of comparator COMP₃ is coupled a second input of each of AND gates AND₂ and AND₃. The output of AND gate AND₂ is fed via a respective buffer BUFF to the AOUT terminal, and the output of AND gate AND₃ is fed via a respective buffer BUFF to the BOUT terminal. The non-inverting input of transconductance amplifier GM₂ is connected to terminal BRT and the inverting input of transconductance amplifier GM₂ is connected to terminal ISNS. As described above in relation to FIG. 1, terminal COMP is further coupled to a first end of capacitor C_COMP, and the second end of capacitor C_COMP is coupled to ground.

[0053] Selected portions of the high level schematic diagram of FIG. 2 are repeated in each of FIGS. 3-5, for clarity of understanding, and are referred to in the below discussion on operation.

[0054] FIG. 3 illustrates a high level schematic diagram of frequency sweeping circuitry 70 of the CCFL controller embodiment of FIG. 1 during STRIKE mode and FIG. 4 illustrates a high level schematic diagram of soft start circuitry 110 of the CCFL controller embodiment of FIG. 1 during STRIKE mode. In STRIKE mode, switches SW₁, SW₄ and SW₅ are closed, and switches SW₂, SW₃ are open. Thus, the circuitry associated with the side of SW₂ and SW₃ which are decoupled are not shown in FIGS. 3 and 4.

[0055] Referring to FIG. 3, the combination of FET switch Q₁, resistor R_EX, capacitor C_EX, comparators COMP₁ and COMP₂, and flip flop FF₁ form oscillator 80 producing a saw tooth waveform within boundaries defined on the high side by the voltage at the inverting input to comparator COMP₁ and on the low side by the voltage at the non-inverting input to comparator COMP₂.

[0056] During the STRIKE mode, current source CS begins to charge capacitor C_MFT. The rising voltage is amplified by op-amp AMP₁. The current flow through FET switch Q₂ is responsive to op-amp AMP₁ and acts as a current reference for current mirror CM. Thus, the rising voltage across capacitor C_MFT results in current driven from current mirror CM into capacitor C_EX. The current from current mirror CM adds to the charge on capacitor C_EX received via resistor R_EX, thus increasing the rise time of oscillator 80 resulting in an increased frequency.

[0057] The output of oscillator 80 is divided by 2 by the action of flip flop FF₂. The output of transconductance amplifier GM₂, representing the error component between BRT and ISNS, is compared with the oscillating waveform appearing at terminal C-R, thereby forming a square wave at the output of comparator COMP₃, with half the frequency of oscillator 80 and a duty cycle responsive to the error component. The square wave output of comparator COMP₃ is alternately fed to AOUT and BOUT by AND gates AND₂ and AND₃.

[0058] Referring to FIG. 4, the combination of op-amp AMP₂ and diode D₁ forms a voltage clamp coupled to the output of transconductance amplifier GM₂. Transconductance amplifier GM₂ represents the error amplifier portion of error amplifier and error logic functionality 100 of FIG. 1. The voltage clamp limits the voltage appearing at the non-inverting input of comparator COMP₃ to be no more than a voltage level responsive to the voltage appearing across capacitor C_MFT. The operation of the voltage clamp can be understood as follows: in the event that the voltage at the non-inverting input of comparator COMP₃ rises above the voltage at the non-inverting input of op-amp AMP₂, the output of op-amp AMP₂ will become negative, and diode D₁ will conduct thereby reducing the voltage appearing at the non-inverting input of comparator COMP₃. In the event that the voltage at the non-inverting input of comparator COMP₃ is below the voltage at the non-inverting input of op-amp AMP₂, diode D₁ does not conduct, and the voltage at the non-inverting input of op-amp AMP₂ is unaffected by the clamp. Thus, soft start functionality 110 is provided by limiting the amplitude of the output of the error amplifier, thereby limiting the duty cycle appearing at outputs AOUT and BOUT, responsive to the slowly rising voltage appearing across capacitor C_MFT at multi-function terminal MFT.

[0059] FIG. 5 illustrates a high level schematic diagram of synchronization functionality 90 of the CCFL controller embodiment of FIG. 1 during RUN mode implemented as a PLL. In RUN mode, switches SW₁, SW₄ and SW₅ are open, and switches SW₂, SW₃ are closed. Thus, the circuitry associated with the side of SW₁, SW₄ and SW₅ which are decoupled are not shown in FIG. 5. As described above in relation to FIG. 3, oscillator 80 produces a saw tooth waveform at terminal C-R. A negative edge appears at the clocking input of flip flop FF₂ substantially contemporaneously with the falling edge of the saw tooth waveform at terminal C-R. In one embodiment each of flip flops FF₂, FF₃ and FF₄ are triggered by falling edges, and the operation will be described in relation thereto, however this is not meant to be limiting in any way, and positive edge triggered or level triggered flip flops may be utilized without exceeding the scope.

[0060] Flip flop FF₂ is arranged to divide the frequency appearing at the clock input of flip flop FF₂ by 2 by feeding the Q bar input to the D input. Similarly, flip flop FF₃ is arranged to divide the frequency appearing at the clock input of flip flop FF₃ by 2 by feeding the Q bar input to the D input. Thus the Q output of flip flop FF₃ is thus at ¼ the frequency of oscillator 80, i.e. ¼ of the frequency of the saw tooth waveform appearing at terminal C-R. As described above in relation to FIG. 3, terminals AOUT and BOUT exhibit a signal with a base frequency of ½ of the frequency of the saw tooth waveform appearing at terminal C-R. The external sync signal appearing at terminal SYNC is derived from an AOUT or BOUT signal of a similar CCFL controller. The SYNC signal is thus divided by 2 by the operation of flip flop FF₄, arranged to divide the frequency appearing at the clock input of flip flop FF₄ by 2 by feeding the Q bar input to the D input.

[0061] The outputs of flip flops FF₃ and FF₄ are coupled to respective inputs of exclusive OR gate EXOR, which exhibits at the output thereof a positive pulse whose width is a function of the difference between the signal appearing at terminal SYNC and the output of flip flop FF₂. The output is filtered by capacitor C_MFT, and coupled to the inverting input of transconductance amplifier GM₁. The non-inverting input of transconductance amplifier GM₁ is coupled to a fixed voltage point. In one particular embodiment, the fixed voltage point is VDD/2 thereby providing a wide working range for transconductance amplifier GM₁, as described above. It is to be understood that the voltage at multi-function terminal MFT during RUN mode is thus approximately equal to the fixed voltage point coupled to the non-inverting input of transconductance amplifier GM₁.

[0062] The difference between the voltage at multi-function terminal MFT, filtered by capacitor C_MFT, and the fixed voltage point, is amplified and output as current into, or taken from, capacitor C_EX. Thus, any difference between the signal appearing at terminal SYNC and oscillator 80 is compensated for by adjusting the rise time of the saw tooth waveform through transconductance amplifier GM₁.

[0063] Synchronization signal detection logic 150 is operative to detect the existence of, or absence of, a valid synchronizing signal at terminal SYNC. In the absence of a valid synchronizing signal at terminal SYNC, synchronization signal detection logic 150 asserts the NO SYNC output. AND gate AND₁ functions to disconnect synchronizing functionality 90 in either STRIKE mode or in the absence of a detected valid synchronizing signal responsive to the NO SYNC output.

[0064] FIG. 6 illustrates a high level flow chart of the operation of control logic 50 and the error logic of error amplifier and error logic functionality 100 of CCFL controller 10 of FIG. 1 according to certain embodiments of the inventions. In stage 1000, a power on reset is detected, preferably by power on reset functionality 60. Preferably, capacitor C_MFT is discharged. In stage 1010, STRIKE mode is entered, i.e. an asserted STRIKE output is exhibited.

[0065] In stage 1020, capacitor C_MFT, at multi-function terminal MFT, begins to charge through current source CS at a controlled rate. In stage 1030, the frequency of oscillator 80 is swept responsive to the voltage across capacitor C_MFT appearing at multi-function terminal MFT, as described in relation to frequency sweeping functionality 70 and in relation to FIG. 3. In stage 1040, which in one embodiment is contemporaneous with stage 1030, the on time of AOUT and BOUT are clamped responsive to the voltage appearing at multi-function terminal MFT, as described above in relation to soft start functionality 110 and in relation to FIG. 4.

[0066] In stage 1050, the time since the inception of stage 1010 is compared with a predetermined time out. In the event that lamp strike is detected prior to expiration of the predetermined time out, in stage 1060, RUN mode is entered, i.e. an asserted RUN output is exhibited.

[0067] In stage 1070, the signal appearing at terminal SYNC is examined, as described above in relation to synchronization signal detection logic 150 of FIG. 5. In the event that a valid synchronization is detected, in stage 1080, synchronization functionality 90, as described in relation to each of FIG. 1 and FIG. 5, is operated to synchronize oscillator 80 with the signal appearing at terminal SYNC.

[0068] In the event that in stage 1070 a valid synchronization is not detected, or upon initiation of stage 1080, in stage 1090 the current and optionally the voltage associated with CCFL 30 are monitored. In stage 1100, the monitored current and or voltage are compared with predetermined limits, which may be exceeded for a predetermined time, denoted T_max. In the event that one of the monitored current, or optionally monitored voltage, has exceeded the allowed range for more than T_max, in stage 1110, an error is detected, and the ERROR output of error amplifier and error detection functionality 100 is asserted. The ERROR output is coupled to the gate of FET switch Q₃, as described above in relation to FIG. 2, driving multi-function terminal MFT towards ground. It is to be noted that multi-function terminal MFT in normal operation exhibits a voltage of around VDD/2, as described above in relation to FIG. 5, and thus the lower voltage may be sensed by external monitoring equipment to indicate a fault condition on CCFL controller 10.

[0069] In the event that in stage 1100 none of the monitored current, or optionally monitored voltage, has exceeded the allowed range for more than T_max, stage 1090 is repeated.

[0070] In the event that in stage 1050 lamp strike is not detected prior to expiration of the predetermined time out, stage 1100 as described above is performed.

[0071] Optionally, stage 1090 may be further performed in STRIKE mode, as described above in relation to FIGS. 3 and 4.

[0072] Thus the present embodiments enable a cold cathode fluorescent lamp controller exhibiting a multi-function terminal and operative alternately in a strike mode and a run mode. In certain embodiments the controller comprises: a phase locked loop arranged for synchronization of an oscillator, associated with the controller, with an external signal, the phase locked loop comprising a capacitor coupled to the multi-function terminal; and a soft start circuit arranged to limit drive current immediately after reset of the controller responsive to a signal at the multi-function terminal.

[0073] In one particular embodiment the cold cathode fluorescent lamp controller further comprises a frequency sweeping circuit operative to sweep the frequency of the drive signal output during the strike mode. The frequency sweeping circuit is preferably operative to sweep the frequency responsive to a signal at the multi-function terminal.

[0074] In one particular embodiment, the cold cathode fluorescent lamp controller further comprises an error detection circuit, operative to detect an error in operation such as a failure of the lamp to be ignited or a persistent over current or over voltage condition. In the event of an error condition, an error signal is asserted at the multi-function terminal. Thus, in such an embodiment the multi-function terminal is further an output terminal of the cold cathode fluorescent lamp controller.

[0075] Unless otherwise defined, all technical and scientific terms used herein have the same meanings as are commonly understood by one of ordinary skill in the art to which this invention belongs. Although methods similar or equivalent to those described herein can be used in the practice or testing of the present invention, suitable methods are described herein.

[0076] All publications, patent applications, patents, and other references mentioned herein are incorporated by reference in their entirety. In case of conflict, the patent specification, including definitions, will prevail. In addition, the materials, methods, and examples are illustrative only and not intended to be limiting.

[0077] It will be appreciated by persons skilled in the art that the present invention is not limited to what has been particularly shown and described hereinabove. Rather the scope of the present invention is defined by the appended claims and includes both combinations and subcombinations of the various features described hereinabove as well as variations and modifications thereof which would occur to persons skilled in the art upon reading the foregoing description.