Power noise detecting device and power noise control device using the same

[0001] The present application claims priority under 35 U.S.C. §119(a) to Korean application number 10-2008-0078808, filed on Aug. 12, 2008, filed in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety as set forth in full.

[0002] 1. Technical Field

[0003] The embodiments described herein relate to a semiconductor device, and more particularly, to a power noise detecting device and a power noise control device using the same.

[0004] 2. Related Art

[0005] A power distribution network (PDN) is configured between a semiconductor integrated circuit (IC) device and an external apparatus to supply power to the semiconductor IC device from the external apparatus through the power distribution network. Parasitic components, such as capacitances, inductances, resistances, and the like, exist on the power distribution network. Accordingly, the parasitic components may have an negative influence on the proper operation of the semiconductor IC device. For example, the parasitic components may cause noise to be generated in the supplied power. Accordingly, a circuit is design to minimize the above-described parasitic components. One method includes use of a decoupling capacitor installed between power lines at a predetermined interval. However, the installation of the decoupling capacitor for reducing the parasitic components causes another parasitic component called an Equivalent Series Resistance (ESR) to be generated.

[0006] If the ESR is small, power distribution performance in a high-frequency region may be improved, but in a resonance frequency region between a semiconductor IC chip and a package covering the chip, as the ESR becomes smaller, the power noise becomes larger. Accordingly, it is necessary to optimize the ESR by considering various operational environments of the semiconductor IC. As a result, it is necessary to accurately detect the power noise.

[0007] However, since the semiconductor IC is commonly designed only to minimize the ESR, there is a problem in that the power noise cannot be reduced to a desired level. Furthermore, an analog/digital converter or a delay line is commonly used to detect the power noise for the purpose of controlling the ESR. However, a large circuit area is required to implement the analog/digital converter or the delay line, which causes a loss in layout area while increasing power consumption.

[0008] A power noise detecting device and a power noise control device using the same capable of accurately detecting power noise and minimizing the power noise by implementing a simple circuit are described herein.

[0009] In one aspect, a power noise detecting device includes a plurality of power lines, and a power noise detecting part configured to detect power noise by rectifying voltages of the plurality of power lines and converting the rectified voltages into effective voltages.

[0010] In another aspect, a power noise control device includes a variable resistor part connected to a plurality of power lines to vary a resistance value according to a resistance value adjustment code signal, a power noise detecting part converting power noise of the power lines into an effective voltage to output the effective voltage, and a power noise control part varying the resistance value adjustment code signal according to a result acquired by comparing the effective voltage with a target code conversion voltage acquired by converting a target code signal.

[0011] These and other features, aspects, and embodiments are described below in the section “Detailed Description.”

[0017] FIG. 1 is a schematic circuit diagram of an exemplary power noise detecting device according to one embodiment. In FIG. 1, a power noise detecting device 1 can be configured to include power lines 110 and 120 via a chip circuit part 220, and a power noise detecting part 230 for detecting the noise of power applied through the power lines 110 and 120, which can be installed in/on a semiconductor chip, such as a semiconductor IC 200.

[0018] A power distribution network 100 can be connected to the semiconductor IC 200 via the power lines 110 and 120. In addition, a decoupling capacitor Cdc, a parasitic resistance component, i.e., an Equivalent Series Resistance (ESR) generated by the decoupling capacitor Cdc, and the chip circuit part 220 can be interconnected between the power lines 110 and 120.

[0019] The chip circuit part 220 can represent a portion or an entirety of a circuit configuration including various signal processing circuits, memory cells, and the like constituting the semiconductor IC 200.

[0020] The power noise detecting part 230 can rectify voltages at both ends of the power lines 110 and 120, and can convert the rectified voltages into effective voltages and output the effective voltages. For example, the power noise detecting part 230 can include a power noise level adjusting unit 231, a rectification unit 232, and an effective voltage detecting unit 233.

[0021] The power noise level adjusting unit 231 can reduce the level of power noise applied to both ends of the power lines 110 and 120 to a level required for detecting the power noise. For example, the power noise level adjusting unit 231 can include first and second distribution resistors Rd1 and Rd2 connected to both ends of the power lines 110 and 120. Here, the first and second distribution resistors Rd1 and Rd2 can have substantially the same resistance value.

[0022] The rectification unit 232 can full-wave rectify and output the power noise level adjusting unit 231. Here, the rectification unit 232 can function by considering a parasitic capacitance value to minimize the distortion of the power noise. For example, the rectification unit 232 can be configured to include a bridge diode of which two input ends can be connected to both ends of the first distribution resistor Rd2.

[0023] The effective voltage detecting unit 233 can output an Root Menu Square (RMS) value of an output signal of the rectification unit 232, such as an effective voltage VNRMS. For example, the effective voltage detecting unit 233 can include a primary filter or a secondary filter formed by combining resistors and capacitors with each other.

[0024] FIG. 2 is a power noise waveform diagram demonstrating exemplary operation for each component of the device of FIG. 1 according to one embodiment. An exemplary operation of a power noise detecting device will now be described with reference to FIG. 2.

[0025] In FIG. 2, the power noise of the power lines 110 and 120 can swing around the level of a power voltage VDD like a node A. However, since the level of the power voltage VDD can drop to one-half due to the power noise level adjusting unit 231, the power noise can also swing at a level corresponding to one-half of the original level like a node B. The power noise of the node B can be full-wave rectified by the rectification unit 232 like a node C. The full-wave rectified signal of the node C can be output as the effective voltage VNRMS by the effective voltage converting unit 233. Accordingly, the power noise detecting device 1 can detect the degree of the power noise according to the level of the effective voltage VNRMS.

[0026] FIG. 3 is a schematic block diagram of another exemplary power noise control device according to one embodiment. In FIG. 3, a power noise control device 2 can detect power noise and can reduce the power noise by controlling a resistance value of a variable resistor configured to substitute for a parasitic resistance component (ESR) according to a detection result. Accordingly, the power noise control device 2 can use the power noise detecting 1 (in FIG. 1) as a configuration for detecting the power noise.

[0027] As shown in FIG. 3, the power noise control device 2 can be configured to include power lines 110 and 120, a variable resistor part 210, a chip circuit part 220, a power noise detecting part 230, and a power noise control part 240.

[0028] The variable resistor part 210 can be configured to vary the resistance value, i.e., the ESR according to a resistance value control code signal ‘ESRCODE<0:N>’. For example, the variable resistor part 210 can be connected between a decoupling capacitor Cdc and the power line 120. Here, the ESR that is generated due to the decoupling capacitor Cdc can exist at a position connected with the variable resistor part 210, wherein the ESR is not intentionally configured by a circuit design but can be a parasitic component. For example, the ESR can be varied by the capacitance of the decoupling capacitor Cdc. The ESR can function as an index for increasing and decreasing the power noise, and although it can be varied, and the ESR cannot be considered to be actively controlled. Accordingly, the variable resistor part 210 can be connected to the decoupling capacitor Cdc to actively control the ESR. As a result, the ESR can be controlled according to the resistance value control code signal ‘ESRCODE<0:N>’.

[0029] The chip circuit part 220 can represent a portion or an entirety of a circuit configuration including various signal processing circuits, the memory cells, and the like constituting the semiconductor IC 200.

[0030] The power noise detecting part 230 can rectify the voltages at both ends of the power lines 110 and 120, and can convert the rectified voltages into the effective voltages to detect the power noise. For example, the power noise detecting part 230 can include the power noise level adjusting unit 231, the rectification unit 232, and the effective voltage detecting unit 233.

[0031] The power noise level adjusting unit 231 can reduce the level of the power noise supplied to both ends of the power lines 110 and 120 to a level advantageous for detecting the power noise. For example, the power noise level adjusting unit 231 can be configured to include the first and second distribution resistors Rd1 and Rd2 connected to both ends of the power lines 110 and 120. Here, the first and second distribution resistors Rd1 and Rd2 can have substantially the same resistance value.

[0032] The rectification unit 232 can full-wave rectify and output the output of the power noise level adjusting unit 231. Here, the rectification unit 232 can function by considering the parasitic capacitance value to minimize the distortion of the power noise. For example, the rectification unit 232 can be configured to include the bridge diode of which two input ends are connected to both ends of the first distribution resistor Rd2.

[0033] The effective voltage detecting unit 233 can output the effective voltage VNRMS of the output signal of the rectification unit 232. For example, the effective voltage detecting unit 233 can include the primary filter or the secondary filter formed by combining the resistors and the capacitors with each other.

[0034] The power noise control part 240 can compare the effective voltage VNRMS with a target code conversion voltage VTARCODE acquired by converting a target code signal ‘TARCODE<0:N>’ to output a comparison result signal ‘UPDN’. For example, the power noise control part 240 can vary the resistance value adjustment code signal ‘ESRCODE<0:N>’ according to the comparison result signal ‘UPDN’.

[0035] The power noise control part 240 can include a digital/analog converting unit 241, a comparison unit 242, and a code generating unit 243.

[0036] The digital/analog converting unit 241 can convert the target code signal ‘TARCODE<0:N>’ into the target code conversion voltage VTARCODE to output the target code conversion voltage VTARCODE. In addition, the comparison unit 241 can compare the effective voltage VNRMS and the target code conversion voltage VTARCODE to output the comparison result signal ‘UPDN’.

[0037] Variation of a potential difference of the rectification unit 232 can be supplied to the target code conversion voltage VTARCODE by connecting any one of the output terminals of the rectification unit 232 to a ground terminal of the digital/analog converting unit 241, such that the target code conversion voltage VTARCODE and the effective voltage VNRMS can be compared with each other by the comparison unit 241 in the same environment.

[0038] The code generating unit 243 can increase or decrease the resistance value adjustment code signal ‘ESRCODE<0:N>’ according to the comparison result signal ‘UPDN’ to output the resistance value adjustment code signal ‘ESRCODE<0:N>’. For example, the code generating unit 243 can include a counter.

[0039] FIG. 4 is a schematic circuit diagram of an exemplary variable resistor part capable of being implemented in the device of FIG. 3 according to one embodiment. In FIG. 4, the variable resistor part 210 can include a plurality of transistors M0 to MN commonly connected to the decoupling capacitor Cdc, and a plurality of resistors R0 to RN connected between the plurality of transistors M0 to MN and the power line 120. In the variable resistor part 210, the number of resistors connected to turned-ON transistors among the plurality of resistors R0 to RN can be increased or decreased according to a code value of the resistance value adjustment code signal ‘ESRCODE<0:N>’, resulting in varying the total resistance value. The total resistance value based on the resistors connected to the turned-ON transistors among the plurality of resistors R0 to RN can serve to function as the ESR. Here, the ESR can be actively controlled.

[0040] An exemplary operation of a power noise control device will now be described with reference to FIG. 2. As shown in FIG. 2, a result acquired by detecting the power noise in the power noise detecting part 230 can be output as the effective voltage VNRMS.

[0041] The digital/analog converting unit 241 can convert the target code signal ‘TARCODE<0:N>’ into an analog voltage. For example, the target code signal ‘TARCODE<0:N>’ can be converted and output as a target code conversion voltage VTARCODE. In the target code signal ‘TARCODE<0:N>’, the resistance value of the variable resistor part 210, i.e., the ESR value is set to an optimum value to minimize the power noise, may be set by a mode register set, and the value of the code may be changed, through a test process.

[0042] The comparison unit 242 can compare the effective voltage VNRMS with the target code conversion voltage VTARCODE to output the comparison result signal ‘UPDN’ at a high level or a low level. For example, the comparison unit 242 can output the comparison result signal ‘UPDN’ by varying a logical level of the comparison result signal ‘UPDN’ according to whether or not the effective voltage VNRMS is higher than the target code conversion voltage VTARCODE.

[0043] The code generating unit 243 can increase or decrease the code value of the resistance value adjustment code signal ‘ESRCODE<0:N>’ according to the comparison result signal ‘UPDN’ to output the code value. Accordingly, the ESR value of the variable resistor part 210 can be changed according to the resistance value adjustment code signal ‘ESRCODE<0:N>’.

[0044] Until the effective voltage VNRMS output according to the changed ESR value is lower than the target code conversion voltage VTARCODE, the power noise detecting operation of the power noise detecting section 230 and the ESR control operation of the power noise control section 240 can be repeated. Accordingly, it is possible to minimize the power noise by optimizing the intentionally designed ESR.

[0045] The exemplary optimization operation of the ESR can be performed by a method including continuously performing the ESR optimization operation during operation of the semiconductor IC, by a method of periodically performing the ESR optimization operation, and/or by a method of performing the ESR optimization operation at the time when the semiconductor IC is powered up. For example, the ESR optimization can be implemented by the various methods by adding an additional circuit component for cutting-off a current depending on an additional enable signal to components of each of the power noise detecting part 230 and the power noise control part 240 and differentiating an activation section of an enable signal.

[0046] While certain embodiments have been described above, it will be understood that the embodiments described are by way of example only. Accordingly, the device and method described herein should not be limited based on the described embodiments. Rather, the devices and methods described herein should only be limited in light of the claims that follow when taken in conjunction with the above description and accompanying drawings.