Method of MRAM fabrication with zero electrical shorting

[0001] 1. Field of the Invention

[0002] This invention relates to the fabrication of a magnetic random access memory (MRAM) device using a magnetic tunneling junction (MTJ) cell and more particularly to a method of its fabrication that results in the elimination of electrical shorting.

[0003] 2. Description of the Related Art

[0004] The magnetic tunneling junction (MTJ) device, is a form of tunneling magnetoresistive (TMR) device in which the relative orientation of uni-directional magnetic moments in parallel, vertically separated upper and lower magnetized layers, controls the flow of spin-polarized electrons tunneling through a very thin dielectric layer (the tunneling barrier layer) formed between those layers. When injected electrons pass through the upper layer they are spin polarized by interaction with the magnetic moment of that layer. The probability of such an electron then tunneling through the intervening tunneling barrier layer into the lower layer then depends on the availability of states within the lower electrode that the tunneling electron can occupy. This number, in turn, depends on the magnetization direction of the lower electrode. The tunneling probability is thereby spin dependent and the magnitude of the current (tunneling probability times number of electrons impinging on the barrier layer) depends upon the relative orientation of the magnetizations of magnetic layers above and below the barrier layer.

[0005] The MTJ cell can be used as a magnetic read head, in which configuration the magnetic moment of the lower magnetized layer is fixed (pinned) in direction, while the magnetic moment of the upper magnetized layer is free to vary continuously under the action of the magnetic field of a moving magnetic medium (i.e. a disk). In that application, therefore, the MTJ device can be viewed as a kind of variable resistor, since different relative orientations of the magnetic moments will change the magnitude of a current passing through the device.

[0006] When the MTJ cell is used as an information storage element in a magnetoresistive random access memory (MRAM) cell array, the magnetic moment of the upper layer is only allowed to have two orientations, parallel or antiparallel to the fixed magnetic moment of the lower magnetized layer. When used in this way, the cell behaves as a resistor with only two resistance values, high (antiparallel magnetic moment directions) and low (parallel magnetic moment directions), which can then be treated as logical 1 and 0.

[0007] One of the critical challenges in MRAM technology is the patterning of the MTJ stack materials to form an MRAM cell. The term “stack,” as used here, refers to the unpatterned, deposited layered structure of conducting, magnetic and dielectric materials. The phrase, “patterning of the stack,” or the like, as used here, refers to the reduction of the lateral dimensions of the stack to the desired dimensions of the cell and to providing the cell with a desired horizontal cross-sectional shape, typically accomplished by etching away portions of the stack peripherally disposed about an etch mask formed on the upper surface of the stack. Because the prior art MTJ stack includes a very thin tunneling barrier layer, typically a layer of AlOx or MgO approximately 10 to 20 angstroms in thickness, shorting or shunting of the current around the junction is a critical problem. Clearly, imprecise patterning could create shorting pathways along the lateral edges of the cell. In addition, precise control of the size and shape of the MTJ cell during its patterning is increasingly important because these factors affect the magnetic and switching properties of the cell.

[0008] In MRAM devices, the elimination of electrical shorting is vital to successful mass-production manufacturing. Among all MRAM fabrication processes, MTJ etching is perhaps the most troublesome step in terms of providing a limitation on shorting. The root cause of electrical shorting that results from this step is mainly from shorting of the MTJ dielectric tunneling barrier layer at its outside edge (the etched edge), which is partially due to either an unetched “footing” or a re-deposition of the electrically conducting byproducts resulting from the etching process. Although the footing could exist for any horizontal cross-sectional shaped device, the worst case is typically associated with the so-called C-state, which is a concave shape shown in FIGS. 1a and 1b below. This problem has been discussed in the prior art, particularly by Y. K. Ha et al., in Symp. VLSI Techn. Dig., 2004, p. 22; in M. Nakayama et al., IEEE Tran. Mag., Vol. 42, p. 2733. In addition to these discussions, the following prior art also discloses attempts to deal with the discussed problem.

[0009] U.S. Pat. No. 7,211,446 (Gaidis et al) eliminates electrical shorting due to residual material by selectively exposing portions of the free layer, then converting those portions to electrically and magnetically inactive material.

[0010] U.S. Pat. No. 6,984,529 (Stojakovic et al) teaches etching an MTJ stack using 5 etch recipes where a surface oxidation is formed after the third etch recipe and the fifth etch recipe removes redeposited materials.

[0011] U.S. Pat. No. 7,252,774 (O'Sullivan et al) discloses a selective chemical etch method for an MTJ stack.

[0012] U.S. Pat. No. 6,933,155 (Albert et al) lowers electrical shorting by forming polishing resistant structures of SiN in regions around the MTJ stack.

[0013] U.S. Patent Application 2006/0234445 (Yang-Headway) teaches forming SiN spacers on sidewalls of the MTJ stack before CMP to prevent shorting.

[0014] U.S. Patent Application 2004/0205958 (Grynkewich et al) uses sidewall spacers and a masking tab to prevent deposition of metallic particles during etching to reduce electrical shorting.

[0015] Referring to FIG. 1, there is shown a schematic sketch of a side TEM view of two MTJ cell C-state (5) in vertical cross-section having a dimension of several hundreds of nanometers. The cells have been etched by a commonly used prior-art RIE process. An arrow (10) points to the region where the etching process has left a footing.

[0016] Referring to FIG. 2, there is shown a table indicating the failure rates in PPM of MTJ cells due to electrical shorting resulting from prior-art etching methods across 49 sectors of a typical 8″ diameter production wafer. This table is shown for comparison purposes with a later table showing the results of etching processes carried out according to the method of the present invention. Although it might reasonably be assumed that a longer etching process using CF₄ gas would produce a more well defined etch and eliminate both the footing and the residue, this turns out not to be the case. In fact, none of the prior arts disclosed above deal effectively with the problem. Therefore, a new method of patterning an MTJ stack is needed, if a TMJ cell of arbitrary horizontal cross-sectional shape and neither short-circuits nor footings is to be fabricated.

[0017] FIG. 3a is a schematic vertical cross-sectional view of an MTJ stack of a material structure and configuration to be patterned by the method of the present invention. The lower layer (310) is a bottom electrode for the purpose of injecting a current. On this electrode will be formed a magnetically pinned structure that comprises a seed layer (320) of NiCr, an antiferromagnetic layer (320) typically of MnPt which will serve as a pinning layer, an Ru coupled pinned layer (340) that is itself a tri-layered structure of the form CoFe/Ru/CoFe in which the first CoFe layer is pinned by the antiferromagnetic layer (320) and is then coupled to the second CoFe layer across the Ru layer. On this pinned structure is then formed the dielectric tunneling barrier layer (350) as a layer of either AlOx or MgO. On this barrier layer is then formed the magnetically free layer (360) as a layer of CoFe or NiFe. On this free layer is then formed a non-magnetic capping layer (370) as a layer of NiFeHf. On this capping layer is then formed a hard mask layer (380) as a layer of Ta.

[0018] The tunneling barrier layer or junction layer (350) is formed on the pinned layer, typically by first forming a layer of a metal such as aluminum (or magnesium) and then subjecting the aluminum (or magnesium) to oxidation.

[0019] A first object of this invention is to provide a method for RIE patterning of an MTJ stack (such as described above) that substantially reduces or eliminates electrical shorting in the resulting cell.

[0020] A second object of this invention is to provide a method for RIE patterning of an MTJ stack that does not result in the creation of unetched footings around the base of the patterned stack.

[0021] A third object of the present invention is to provide a method for RIE patterning of an MTJ stack that does not result in the re-deposition of etching residue about the base of the stack.

[0022] A fourth object of the present invention is to provide a method of eliminating large standard deviations in the of distributions of sensor resistances.

[0023] A fifth object of the present invention is to meet the previous objects whether the horizontal cross-sectional shape of the patterned cell is convex or concave.

[0024] These objects will be met by a new method for forming MTJ devices by patterning MTJ stacks. The method includes the following briefly described steps:

• • [0025] 1. form the following multilayer MTJ stack:
    • [0026] BE/NiCr/MnPt/CoFe/Ru/CoFe/AlOx/NiFe/NiFeHf/Ta
  • [0027] 2. anneal the stack;
  • [0028] 3. prepare stack for photolithographic patterning using a layer of photoresist over a layer of bottom Anti-Reflection Coating (BARC) over the Ta hard mask layer;
  • [0029] 2. in an RIE chamber apply a CF₄ gas hard mask etch to etch unprotected lateral portions of the Ta hard mask layer, over-etching through the upper layer Ta hard mask into the NiFeHf capping layer;
  • [0030] 3. apply the first step of a continuous high power oxygen process at a 200 W-500 W power level to clean off remaining photoresist and BARC and to clean away any Ta redeposited material;
  • [0031] 4. continue the high powered oxygen process, for between 110 s and 150 s, at a higher power level of between 400 W and 600 W to further etch away the exposed NiFeHf capping layer, the NiFe free layer, the AlOx barrier layer, then stopping approximately midway through the contiguous CoFe pinned layer to make certain that the AlOx barrier layer has been completely etched through, leaving an oxide layer surrounding all exposed surfaces;
  • [0032] 5. in another chamber, etch the remaining unetched layers using a CH₃ OH etchant under high bias power, during which process the remaining Ta hard mask protects the unetched portion of the stack due to etch selectivity between the Ta and the remaining MTJ materials (NiFe, CoFe, MnPt) under the CH₃ OH etchant.

[0043] The preferred embodiment of the present invention is the formation of a patterned MTJ stack using a reactive ion etch (RIE) and the production, thereby, of an MTJ cell that is free of electrical shorting and suitable for use in an MRAM array.

[0044] Referring to FIG. 3a, there is shown a schematic vertical cross-sectional view of a horizontally multi-layered MTJ stack of a material structure, dimensions and configuration to be effectively patterned by the method of the present invention. The lower layer (310) is a bottom electrode for the purpose of injecting a current. On this electrode will be formed a horizontally multi-layered magnetically pinned structure that comprises a seed layer (320) of NiCr formed to a thickness between approximately 30 and 60 Angstroms, an antiferromagnetic layer (330), typically of MnPt formed to a thickness between approximately 120 and 300 Angstroms, but which can be IrMn, MnNi or any intrinsic antiferromagnetic material that can exchange couple with a ferromagnetic material so as to fix the magnetic directions of the entire structure, an Ru coupled layer (340) that is itself a tri-layered structure of the form CoFe/Ru/CoFe in which the first CoFe layer (342), formed to a thickness between approximately 10-30 Angstroms, has its magnetization fixed in space by exchange coupling with the contiguous antiferromagnetic layer (320) and is then, in turn, coupled to the second CoFe (346) layer, also formed to a thickness between approximately 10-30 Angstroms, across the Ru (344) layer, whose thickness is between approximately 7-15 Angstroms. Thus, the multi-layered pinned structure comprises the constituent layers (320), (330), (342), (344) and (346).

[0045] On this multi-layered pinned structure there is then formed the dielectric tunneling barrier layer (350) as a layer of either AlOx or MgO formed to a thickness between approximately 7-20 Angstroms, but which can be dielectric layer formed as a metallic oxide of a different metal. On this barrier layer is then formed the magnetically free layer (360) as a layer of CoFe or NiFe having a thickness between approximately 15-50 Angstroms. On this free layer is then formed a non-magnetic capping layer (370), preferably as a layer of NiFeHf formed to a thickness between approximately 25-80 Angstroms, but which can be a layer of the form NiFeX with X being Hf, Zr, Nb, Ru, Mg Zr or other non-magnetic metal having a sufficiently high concentration to render the NiFeX non-magnetic. On this capping layer is then formed a hard mask layer (380) as a layer of Ta formed to a thickness between approximately 400-600 angstroms.

[0046] Referring now to FIG. 3b, there is shown schematically the stack of FIG. 3a with the addition of a photolithographically patterned layer of BARC (390) (a Bottom Anti-Reflection Coating to improve exposure quality) formed to a thickness of approximately 600 Angstroms on the upper surface of the Ta hard mask (380). The unprotected region (400) laterally disposed about the peripheral edges of this layer will serve to define the portion of the stack to be etched away so as to produce the desired MTJ cell shape. The periphery of the horizontal cross-sectional shape of the patterned layer can be elliptical, convex, concave, or any desired shape, and yet the method to be described below will meet the objects of the invention.

[0047] Referring next to FIG. 3c, there is shown schematically the fabrication of FIG. 3b with the BARC (390), the Ta layer (380) and the magnetic capping layer (370) all having been partially etched away by the application of a CF₄ hard-mask etchant gas applied at a rate of approximately 50 sccm in the RIE chamber. The laterally disposed regions (400) of the BARC and the Ta (not being protected by the patterned photoresist) have been etched away completely, while leaving the non-magnetic capping layer partially thinned (410). The partially thinned region (410) of the non-magnetic capping layer (370) is a result of an over-etching (of between 15% and 40%) of the Ta layer (380) to ensure that the Ta layer is completely etched away laterally, given the non-uniformity of the etching process. The etching gas, while preferably CF₄ can be another carbon fluoride such as C₄F₆ or C₄F₈, or a carbon hydrogen fluoride such as CHF₃.

[0048] Referring now to FIG. 3d, there is shown schematically the fabrication of FIG. 3c after the application of a single continuous high-power O₂ ashing/etching process during which the bias power is applied at two successive levels: a first level between approximately 50 W and 500 W followed by a second level at between approximately 400 W and 600 W for an additional 110-150 seconds.

[0049] During the first power level of the application, the remaining photoresist, the remaining BARC, the remaining lateral portion of the non-magnetic capping layer ((410) in FIG. 4c), along with any hard mask residue left by the CF₄ hard mask etch described above is removed.

[0050] With the continued application of the O₂ gas, now at the higher power of between approximately 400 and 600 W and for an additional time of between approximately 110 and 150 seconds, the lateral portions of the free layer (360) and the barrier layer (350) are removed, leaving only a portion (347) of the laterally disposed extent of the upper layer (346) of the pinned layer.

[0051] The entire exposed surface of the fabrication is now covered by a thin oxidized layer (385) as a result of this O₂ process. This surface includes the upper surface of the Ta hard mask layer (380) as well as the substantially vertical sides formed by the (generally curved) lateral edges of the Ta hard mask layer, the non-magnetic capping layer (370), the free layer (360), the barrier layer (350) and a remaining portion of the upper pinned layer (346).

[0052] In summary, the single-step process comprises the introduction of O₂ gas at approximately 100 sccm under a first bias power of between approximately 200 W and 500 W, followed by the continued O₂ application at a second, higher bias power of between approximately 400 and 600 W for a time between approximately 110 and 150 seconds.

[0053] Referring finally to FIG. 3e, there is schematically shown the fabrication of FIG. 3d after application, at a flow rate of approximately 20 sccm, of a CH₃OH etch that removes the laterally disposed portions of the remaining stack layers: (346), (344), (342), (330) and (320) and, due to an over-etch condition, possibly even a small portion of the bottom electrode (310). The bottom electrode is not coextensive with the cell, but extends further laterally than the patterned cell. Although the cell is substantially formed on the horizontal surface of the bottom electrode, it is understood that the over-etch condition of the etching process can actually leave a small pedestal of the electrode directly beneath the seed layer (320) as shown in the figure. In addition, as can be seen, the portion of oxide layer (385) formed over the top surface of layer (380) has also been removed, leaving only oxide sidewalls (385) remaining to cover the lateral sides of the patterned stack. During this CH₃OH etch process, the oxide sidewalls (385) act as a shield to prevent the formation of any short-circuiting path across the tunneling barrier layer (350) along the substantially vertical side outer surface of the fabrication. This final etching process employs a carbon, hydrogen, oxygen gas as an etching gas, such as CH₃OH (already noted above), C₂H₅OH or a mixture such as CO/NH₃. The over etch can be between approximately 30% and 70%.

[0054] Because there is an etching selectivity greater than 15 between the Ta hard mask (380) and the other layer materials for this etch, the Ta adequately protects the patterned structure while the laterally disposed layers that are not protected by the Ta are removed by the etch. During this entire CH₃OH etch process, the oxide sidewall (385) is protecting the patterned stack from short-circuiting due to redeposit of the etching residue (which is not shown) along the stack sides. Note that to eliminate the formation of footings at the bottom edges of the MTJ cell (where it joins the electrode), the Ta hard mask must not be too thick and the Ta over etch condition should not be too long. The protection against short-circuits depends on how the O₂ etching process conditions are applied, in terms of power and duration as specified above. The higher power phase (400 W-600 W) of the O₂ etching process should etch completely through the tunneling barrier layer, which typically allows the upper pinned layer (346) to be partially etched (see (347) in FIG. 3d).

[0055] It is to be noted that short-circuits of the kind eliminated by the above described process need not have been complete so as to reduce the cell resistance to zero, they could have been only partial, so as to cause resistance variations among a large group of cells. It is precisely these random resistance variations that will produce a large standard deviation in the distribution of cell resistances among a production-lot of cells produced from a wafer. Thus, the method accomplishes the object of reducing such standard deviations.

[0056] Referring to FIG. 4, there is shown (for clarity) a schematic drawing of an actual side TEM view of two cells of the same type as shown schematically in FIG. 1. The cells in FIG. 1 have been formed using a prior art process and show the bottom footings and re-deposition of residue (10), while the cells in FIG. 4 have been formed using the present process and arrows (100) show the smooth cell side shapes and the absence of footings or re-depositions.

[0057] Referring to FIG. 5, there is shown a tabular illustration of the number of failed devices across an 8″ production wafer when the devices are formed using the present method. Compared to a similar tabulation in FIG. 2, for a prior art patterned cell, the reductions of failures due to shorting is quite marked.

[0058] As is finally understood by a person skilled in the art, the preferred embodiments of the present invention are illustrative of the present invention rather than limiting of the present invention. Revisions and modifications may be made to methods, materials, structures and dimensions employed in forming providing a patterned MTJ cell protected from electrical short circuiting due to footings and re-depositions, while still forming and providing such a patterned cell in accord with the spirit and scope of the present invention as defined by the appended claims.