Through-silicon via with air gap

[0001] This invention relates generally to integrated circuits and, more particularly, to a semiconductor device having through-silicon vias.

[0002] Since the invention of the integrated circuit (IC), the semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, which allows more components to be integrated into a given area.

[0003] These integration improvements are essentially two-dimensional (2D) in nature, in that the volume occupied by the integrated components is essentially on the surface of the semiconductor wafer. Although dramatic improvements in lithography has resulted in considerable improvement in 2D IC formation, there are physical limits to the density that can be achieved in two dimensions. One of these limits is the minimum size needed to make these components. Also, when more devices are put into one chip, more complex designs are required.

[0004] In an attempt to further increase circuit density, three-dimensional (3D) ICs have been investigated. In a typical formation process of a 3D IC, two dies are bonded together and electrical connections are formed between each die and contact pads on a substrate. For example, one attempt involved bonding two dies on top of each other. The stacked dies were then bonded to a carrier substrate and wire bonds electrically coupled contact pads on each die to contact pads on the carrier substrate. This attempt, however, requires a carrier substrate larger than the dies for the wire bonding.

[0005] More recent attempts have focused on through-silicon vias (TSVs). Generally, a TSV is formed by etching a vertical via through a substrate and filling the via with a conductive material, such as copper. A dielectric liner, typically tetra-ethyl ortho-silicate (TEOS), is formed along the sidewalls of the via prior to filling the via with the conductive material. The dielectric constant of TEOS, however, is about 4.2, thereby creating a potentially large capacitance. This large capacitance may in turn adversely affect the performance of a resistor-capacitor (RC) circuit.

[0006] Accordingly, there is a need for a better structure of and method of forming TSV structures.

[0007] These and other problems are generally reduced, solved or circumvented, and technical advantages are generally achieved, by embodiments of the present invention, which provides through-silicon vias for a semiconductor device.

[0008] In accordance with an embodiment of the present invention, a semiconductor device is provided. The semiconductor device includes a semiconductor substrate having a through-silicon via extending therethrough. An air gap is interposed between the through-silicon via and the semiconductor substrate.

[0009] In accordance with another embodiment of the present invention, a method of forming a semiconductor device is provided. A semiconductor substrate having a first side and a second side opposite the first side is provided. An opening is formed in the semiconductor device, and a first dielectric layer is formed along sidewalls of the opening. Thereafter, a conductive material is formed in the opening over the first dielectric layer. The second side of the semiconductor substrate is thinned to expose the first dielectric layer, which is then removed. After removing the first dielectric layer, a second dielectric layer is formed on the second side of the semiconductor substrate to seal an air gap in the opening.

[0010] In accordance with yet another embodiment of the present invention, another method of forming a semiconductor device is provided. The method includes providing a semiconductor substrate having a through-silicon via extending from a circuit side partially through the semiconductor substrate, wherein a liner is interposed between the through-silicon via and the semiconductor substrate. A backside of the semiconductor substrate is thinned such that the liner is exposed, and at least a portion of the liner is exposed. At least a portion of the liner is interposed between the through-silicon via and the semiconductor substrate, forming an opening around the through-silicon via on the backside of the semiconductor substrate. A dielectric layer is formed over the opening, leaving a sealed air gap interposed between the through-silicon via and the semiconductor substrate.

[0013] The making and using of the presently preferred embodiments are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.

[0014] The intermediate stages of a method for forming a die having a through-silicon via suitable for use in a three-dimensional integrated circuit (e.g., a stacked die configuration) or a backside bonding configuration are illustrated in FIGS. 1-4. Throughout the various views and illustrative embodiments of the present invention, like reference numerals are used to designate like elements.

[0015] Referring first to FIG. 1, a semiconductor substrate 110 having electrical circuitry 112 formed thereon is shown. The semiconductor substrate 110 may comprise, for example, bulk silicon, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. Generally, an SOI substrate comprises a layer of a semiconductor material, such as silicon, formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer or a silicon oxide layer. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multi-layered or gradient substrate may also be used.

[0016] The electrical circuitry 112 formed on the semiconductor substrate 110 may be any type of circuitry suitable for a particular application. In an embodiment, the circuitry includes electrical devices formed on the substrate with one or more dielectric layers overlying the electrical devices. Metal layers may be formed between dielectric layers to route electrical signals between the electrical devices. Electrical devices may also be formed in one or more dielectric layers.

[0017] For example, the electrical circuitry 112 may include various N-type metal-oxide semiconductor (NMOS) and/or P-type metal-oxide semiconductor (PMOS) devices, such as transistors, capacitors, resistors, diodes, photo-diodes, fuses, and the like, interconnected to perform one or more functions. The functions may include memory structures, processing structures, sensors, amplifiers, power distribution, input/output circuitry, or the like. One of ordinary skill in the art will appreciate that the above examples are provided for illustrative purposes only to further explain applications of the present invention and are not meant to limit the present invention in any manner. Other circuitry may be used as appropriate for a given application.

[0018] Also shown in FIG. 1 is an inter-layer dielectric (ILD) layer 116. The ILD layer 116 may be formed, for example, of a low-K dielectric material, such as phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), SiO_xC_y, Spin-On-Glass, Spin-On-Polymers, silicon carbon material, compounds thereof, composites thereof, combinations thereof, or the like, by any suitable method known in the art, such as spinning, chemical vapor deposition (CVD), and plasma-enhanced CVD (PECVD). It should also be noted that the ILD layer 116 may comprise a plurality of dielectric layers.

[0019] Contacts 118 are formed through the ILD layer 116 to provide an electrical contact to the electrical circuitry 112. The contacts 118 may be formed, for example, by using photolithography techniques to deposit and pattern a photoresist material on the ILD layer 116 to expose portions of the ILD layer 116 that are to become the contacts 118. An etch process, such as an anisotropic dry etch process, may be used to create openings in the ILD layer 116. The openings are, preferably, lined with a diffusion barrier layer and/or an adhesion layer (not shown), and filled with a conductive material. Preferably, the diffusion barrier layer comprises one or more layers of TaN, Ta, TiN, Ti, CoW, or the like, and the conductive material comprises copper, tungsten, aluminum, silver, and combinations thereof, or the like, thereby forming the contacts 118 as illustrated in FIG. 1.

[0020] One or more inter-metal dielectric (IMD) layers 120 and the associated metallization layers (not shown) are formed over the ILD layer 116. Generally, the one or more IMD layers 120 and the associated metallization layers are used to interconnect the electrical circuitry to each other and to provide an external electrical connection. The IMD layers 120 are preferably formed of a low-K dielectric material, such as fluorosilicate glass (FSG) formed by PECVD techniques or high-density plasma chemical vapor deposition (HDPCVD) or the like, and may include intermediate etch stop layers. Contacts 122 are provided in the uppermost IMD layer to provide external electrical connections.

[0021] It should also be noted that one or more etch stop layers (not shown) may be positioned between adjacent ones of the dielectric layers, e.g., the ILD layer 116 and the IMD layers 120. Generally, the etch stop layers provide a mechanism to stop an etching process when forming vias and/or contacts. The etch stop layers are preferably formed of a dielectric material having a different etch selectivity from adjacent layers, e.g., the underlying semiconductor substrate 110, the overlying ILD layer 116, and the overlying IMD layers 120. In an embodiment, etch stop layers may be formed of SiN, SiCN, SiCO, CN, combinations thereof, or the like, deposited by CVD or PECVD techniques.

[0022] Also shown in FIG. 1 is a through-silicon via 124. The through-silicon via 124 may be formed by any appropriate method. For example, openings may be formed extending into the semiconductor substrate 110 by, for example, one or more etching processes, milling, laser techniques, or the like. The openings are preferably lined with a liner, such as a liner 126, that acts as an isolation layer. Preferably, the liner 126 comprises one or more layers of TEOS, but other materials may be used. As will be discussed in greater detail below, portions of the liner 126 will be removed during subsequent processing steps, so a material that is easy to work with and is easy to remove while causing little or no damage to the other structures should be used.

[0023] A protective layer 130, such as a polyimide material, may be formed and patterned over the surface of the liner 126. Thereafter, the openings may be filled with a conductive material, such as copper, tungsten, aluminum, silver, and combinations thereof, or the like, thereby forming the through-silicon via 124. Other materials, including conductive diffusion barrier layers, such as TaN, Ta, TiN, Ti, CoW, or the like, may also be used.

[0024] Contacts 132, such as metal bumps formed of Cu, W, CuSn, AuSn, InAu, PbSn, or the like, are formed in electrical contact with a conductive line 128, and a carrier substrate 134 is attached using an adhesive 136. Generally, the carrier substrate 134 provides temporary mechanical and structural support during subsequent processing steps. In this manner, damage to the semiconductor substrate 110 is reduced or prevented. The carrier substrate 134 may comprise, for example, glass, silicon oxide, aluminum oxide, and the like. The adhesive 136 may be any suitable adhesive, such as an ultraviolet (UV) glue, which loses its adhesive property when exposed to UV lights.

[0025] It should be noted, however, that the material selected for the liner 126 should be selected such that a high-etch selectivity exists between the material used to form the liner 126 and the surrounding materials, e.g., the materials of the semiconductor substrate 110, the through-silicon via 124, and any relevant ILD layer 116, IMD layers 120, and/or etch stop layers. As will be discussed in greater detail below, the liner 126 is removed in subsequent processing steps, and as such, a high-etch rate selectivity allows the removal of the liner 126 with little or no damage to the surrounding layers.

[0026] It should also be noted that the through-silicon via 124 is illustrated as extending into the semiconductor substrate 110 from a top surface of the IMD layers 120 for illustrative purposes only and that other arrangements may be utilized. In another embodiment the through-silicon via 124 may extend from a top surface of the ILD layer 116 or the semiconductor substrate 110. For example, in an embodiment, the through-silicon via 124 is formed by creating openings extending into the semiconductor substrate 110 after forming the contacts 118 by, for example, one or more etching processes, milling, laser techniques, or the like. The openings are also preferably lined with a liner, such as liner 126, that acts as an isolation layer, and filled with a conductive material as discussed above. The IMD layers 120 may then be formed over the through-silicon via and, optionally, external electrical connections may be created to the through-silicon via using the metallization layers.

[0027] The through-silicon via 124 is also illustrated as extending over a top dielectric surface, e.g., the IMD layer 120 for illustrative purposes. In this embodiment, the through-silicon via 124 may be formed of a single conductive layer with the conductive line 128, interconnecting the through-silicon via 124 with the contact 122. In other embodiments, the through-silicon via 124 may not be interconnected with electrical circuitry formed on the semiconductor substrate 110. In this embodiment, the through-silicon via provides an electrical connection to electrical circuitry formed on another substrate (not shown) coupled on either the backside of the substrate or the circuit side of the substrate.

[0028] FIG. 2 illustrates a thinning process performed on a backside of the semiconductor substrate 110 to expose the liner 126 in accordance with an embodiment of the present invention. The thinning process may be performed using an etching process and/or a planarization process, such as a mechanical grinding process or a chemical mechanical polishing (CMP) process. For example, initially a planarizing process, such as grinding or a CMP, may be performed to initially expose the liner 126. Thereafter, one or more wet etching processes having a high etch-rate selectivity between the material of the liner 126 and the semiconductor substrate 110 may be performed, thereby leaving the through-silicon via 124 protruding from the backside of the semiconductor substrate 110 as illustrated in FIG. 2. The etch process may be, for example, a dry etch process using HBr/O₂, HBr/Cl₂/O₂, SF₆/CL₂, SF₆ plasma, or the like. It should be noted, however, that in other embodiments, the through-silicon via 124 may not protrude from the backside of the semiconductor substrate 110.

[0029] FIG. 3 illustrates an etching process to remove at least a portion of the liner 126 in accordance with an embodiment of the present invention. One or more wet etching processes having a high etch-rate selectivity between the material of the liner 126 and the surrounding materials, e.g., the material of the semiconductor substrate 110, the ILD layer 116, the IMD layers 120, the conductive material of the through-silicon via 124, and/or, if present, etch stop layers may be performed. As a result, an air gap 310 surrounding the through-silicon via 124 is formed. One of ordinary skill in the art will appreciate that the dielectric constant of air (about 1.0) is less than the dielectric constant of the liner 126, e.g., less than the dielectric constant of TEOS. Because the dielectric constant is lower, the capacitance is lowered. In an embodiment in which the liner 126 is formed of TEOS, the liner 126 may be removed by etching, for example, using XeF₂ dry etching.

[0030] FIG. 3 also illustrates the embodiment in which the air gap 310 extends for the entire depth of the through-silicon via and extends over the surface of the IMD layers 120. In this embodiment, the air gap 310 continues over the upper surface of the IMD layers 120 (or the ILD layer 116). Other surfaces, such as the contact 122, formed of materials having a high etch selectivity with the material of the liner 126 may cause the etching process to stop. The etching process may also be a timed etch to control the amount of the liner 126 to be removed.

[0031] FIG. 4 illustrates an isolation film 410 formed over the backside of the semiconductor substrate 110 (or a native oxide that may be formed on the surface of the semiconductor substrate 110) in accordance with an embodiment of the present invention. In a preferred embodiment, the isolation film 410 is a dielectric material, such as SiN, an oxide, SiC, SiON, a polymer, or the like, and may be formed by, for example, spin-coating, printing, a CVD process, or the like. The isolation film 410 is preferably formed having a thickness sufficient to cover the opening of the air gap 310 alongside the conductive material of the through-silicon via 124.

[0032] It should be noted that FIG. 4 illustrates a conformal layer for illustrative purposes only, and that other processes may be used. For example, a spin-on process that creates a more planar surface may be used.

[0033] FIG. 5 illustrates exposure of the through-silicon via 124 in accordance with an embodiment of the present invention. The isolation film 410 may be removed using photolithographic techniques in which a patterned mask is formed that protects the isolation film 410 except for the portions overlying the through-silicon via 124. The exposed portions of the isolation film 410 overlying the through-silicon via 124 may then be removed using an etching process. In the embodiment illustrated in FIG. 5, the etching process is continued until the through-silicon via 124 protrudes from the isolation film 410.

[0034] Thereafter, other back-end-of-line (BEOL) processing techniques suitable for the particular application may be performed to complete the semiconductor device. For example, the carrier substrate 134 may be removed, under-bump metallization and contacts may be formed on the circuit side and the backside of the substrate, an encapsulant may be formed, a singulation process may be performed to singulate individual dies, wafer-level or die-level stacking, and the like, may be performed. It should be noted, however, that embodiments of the present invention may be used in many different situations. For example, embodiments of the present invention may be used in a die-to-die bonding configuration, a die-to-wafer bonding configuration, or a wafer-to-wafer bonding configuration.

[0035] Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.