System and method for dropping lower priority packets that are slated for wireless transmission

[0001] This application is a continuation of U.S. patent application Ser. No. 10/253,659, entitled “System and Method for Dropping Lower Priority Packets that are Slated for Transmission,” filed Sep. 25, 2002, which is incorporated by reference herein in its entirety.

[0002] 1. Field of the Invention

[0003] The present invention is generally related to increasing the efficiency of memory space by dropping lower priority packets that are slated for transmission via a communication medium.

[0004] 2. Related Art

[0005] The importance to the modern economy of rapid data access and exchange cannot be overstated. This explains the exponentially increasing popularity of the data access and exchange via cable networks (including coaxial cable or Hybrid fiber coaxial cable), the Internet, intranets, wireless networks, satellites and so forth (i.e., communication mediums). Rapid data access and exchange is partly dependent upon how efficiently bandwidth is allocated to a data provider in order for the data provider to transfer the requested data to a user via one of the communication mediums mentioned above.

[0006] One very desirable solution for rapid data access and exchange is via cable networks and cable modems. Cable modems provide communications on cable networks. In general, a user connects a cable modem to the TV outlet for his or her cable TV, and the cable TV operator connects a cable modem termination system (ACMTS@) in the operator=s headend. The CMTS is a central device for connecting the cable network to a data network like the Internet. The CMTS is a central distribution point for a cable system. Data flows Adownstream@ from the CMTS to the cable modem (i.e., downstream communication). Alternatively, data flows Aupstream@ from the cable modem to the CMTS (i.e., upstream communication).

[0007] A common cable modem standard today is the Data Over Cable Service Interface Specification (ADOCSIS@). DOCSIS defines technical specifications for both cable modems and CMTS. In DOCSIS, packets are slated for transmission to the data provider via downstream communication by storing the packets in memory. Different types of data have different priorities. These different priorities determine the order in which the packets are sent to the data provider. For example, voice data cannot tolerate delay in transmission and thus is given a higher priority over other types of data that can tolerate delay (e.g., data involved in web surfing). Thus, at times lower priority packets back up due to the CMTS receiving higher priority packets before the CMTS can send the lower priority packets to their respective data provider. This backup tends to fill up the memory that is allocated to store the packets. Therefore, what is needed is a way of dropping the oldest and lowest priority packets when memory becomes too full.

[0008] The present invention is a method for dropping low priority packets that are slated for transmission to a cable modem. A central device receives one or more packets to be transferred to one or more data providers, each packet having a priority. Then, based on the priority, a media access controller stores each of the packets in one or more priority queues in a fixed shared memory space in such a way as to maintain the order in which the packets were received in each of the priority queues. The media access controller monitors the number of packets in each of the priority queues and signals an interrupt when a packet threshold is exceeded in one or more of the priority queues. The media access controller then drops lower priority packets in the fixed shared memory space based on the order received to guarantee that there is enough memory to store higher priority packets in the fixed shared memory space.

A. Overview of the Invention

[0016] For illustration purposes, the present invention is described in terms of being utilized with a cable network and DOCSIS. It should be understood that the present invention is independent of the actual physical layerof transmission utilized by DOCSIS (e.g., TDMA, SCDMA, etc.). It should also be understood that the present invention is not limited to use with a cable network and/or DOCSIS. In fact, the present invention may be used with any communication medium, including but not limited to, the Internet, intranets, fiber optic networks, wireless networks and satellite-based networks.

B. System Architecture Overview

[0017] FIG. 1 is a block diagram representing an example operating environment of the present invention. It should be understood that the example operating environment in FIG. 1 is shown for illustrative purposes only and does not limit the invention. Other implementations of the operating environment described herein will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein, and the invention is directed to such other implementations. Referring to FIG. 1, a CMTS 102, a cable modem 104, downstream communication 106 and upstream communication 108, are shown. CMTS 102 further includes a CMTS scheduler 110 and a media access controller (MAC) 112. MAC 112 includes a direct memory access (DMA) unit 116 and a local SDRAM 114. Cable modem 104 includes a cable modem scheduler 118. Each of these components will be briefly described next.

[0018] In general, cable modem 104 forwards or provides data via communications on cable networks. Cable modem 104 receives data from a user that needs to be transferred via a cable network. In order to do this, cable modem 104 requests that CMTS 102 grant to it the necessary bandwidth via a packet.

[0019] As mentioned, cable modem 104 receives data from a user to be transferred via a cable network. In addition, CMTS 102 receives data from the network to be transferred to cable modem 104. Different types of data require different modes of transfer since the importance of timing is different with different types of data. For example, voice data cannot tolerate delays in its transfer. Alternatively, the type of data involved in web surfing can tolerate delays in its transfer.

[0020] In order to ensure the importance of timing is maintained, cable modem 104 assigns different priorities to different types of data. The higher the priority data has, the less of a delay that type of data will experience in its transfer via the cable network. Thus, voice data would be assigned a higher priority than data involved in web surfing.

[0021] Cable modem scheduler 118 is coupled to cable modem 104. In general, cable modem scheduler 118 is responsible for multiplexing the internal traffic, (i.e., requesting the necessary bandwidth that cable modem 104 needs to transfer its current types of data). Cable modem scheduler 118 must take into consideration the different priorities given to the current data to be transferred and to request bandwidth from CMTS 102 accordingly.

[0022] Cable modem scheduler 118 sends bandwidth requests to CMTS 102 via upstream communication 108. At a high level, each bandwidth request may include two fields. The two fields include a data provider identifier (SID) and the amount of required bandwidth. These two fields are briefly described next.

[0023] Each cable modem 104 has a unique SID. CMTS 102 uses this identifier to grant the requested bandwidth via a packet to cable modem 104. The second field is a value indicating the amount of required bandwidth needed to transfer the data. As described above, each type of data is associated with a priority. CMTS 102, CMTS scheduler 110 and MAC 112 will now be described.

[0024] CMTS 102 is a central device for connecting the cable network to a data network. CMTS scheduler 110 is a bandwidth manager. CMTS scheduler 110, as a bandwidth manager, decides how to grant available bandwidth according to the current bandwidth requests. This grant is done via a packet sent onto downstream communication 106 to cable modem 104.

[0025] MAC 112 is responsible for dropping lower priority packets that are slated for transmission to cable modem 104. MAC 112 is also responsible for transferring packets from local SDRAM 114 (via DMA unit 116) to CTMS scheduler 110. Local SDRAM 114 stores the packets. Local SDRAM 114 is described in more detail next with reference to FIG. 2. It is important to note that the present invention is not limited to using SDRAM. Other types of memory including internal SRAM, internal register space, external RAMBUS memory, DDR, and so forth, may also be used by the present invention. The present invention is explained in terms of SDRAM for illustration purposes only.

[0026] Referring to FIG. 2, local SDRAM 114 may include priority queues 202, threshold value registers 204, descriptor count registers 206, a drop begin register 208 and packet drop registers 210. In other embodiments of the invention, threshold value registers 204, descriptor count registers 206, drop begin register 208 and packet drop registers 210 are located externally to local SDRAM 114. Each of these are briefly described next.

[0027] Priority queues 202 are used to organize the received packets for bandwidth requests in such as way as to take into consideration the type of data and the order in which the packets were received.

[0028] Threshold value registers 204 include one register for each of the priority queues 202. Threshold value registers 204 represent the threshold number of packets that are allowed to be stored in its corresponding priority queue without an interrupt being sent to CMTS 102. If the threshold number is exceeded, then the present invention signals an interrupt, as will be described below with reference to FIGS. 3 and 4.

[0029] Descriptor count registers 206 also includes one register for each of the priority queues 202. Descriptor count registers 206 represent the number of outstanding packets currently stored in its corresponding priority queue.

[0030] Drop begin register 208 represents whether the packet drop feature of the present invention is activated by CMTS 102. Note that the packet drop feature of the invention may be implemented in software, hardware, hardware assist such as FPGA or ASIC, or any other way of implementing logic that is able to respond to an interrupt and determine how many packets to drop. If the packet drop feature is activated, then the present invention drops lower priority packets that are slated for transmission. Once the packet drop process is completed, drop begin register 208 is automatically cleared. The packet drop feature of the present invention is described below with reference to FIGS. 3 and 4.

[0031] Finally, packet drop registers 210 includes one register for each of the priority queues 202. Packet drop registers 210 indicate the number of packets to drop from its respective priority queue when the packet drop feature is enabled.

[0032] In an embodiment of the present invention, priority queues 202 are stored in a fixed shared memory space of local SDRAM 114. Thus, if one or more of the queues in priority queues 202 are storing many packets then these queues may be using up all of the shared memory space reserved for priority queues 202 in local SDRAM 114, and thus not allowing memory space for other queues to temporarily store packets until they are sent to cable modem 104. The present invention therefore uses threshold value registers 204 (FIG. 2) to monitor the number of packets stored in each queue and signal an interrupt when the threshold is exceeded. CMTS 102 (i.e., software in an embodiment of the invention) then uses the drop begin register 208 and packet drop registers 210 to drop lower priority packets that are slated for transmission. This frees up the fixed shared memory space, allowing for new packets to be queued or scheduled to be sent to cable modem 104. An example priority queues 202 is described next with reference to FIG. 5.

[0033] FIG. 5 illustrates three priority queues having three different priorities, namely high, medium and low. Note that the present invention is not limited to three priority queues, but may have 1 through n queues with 1 being the highest priority and n being the lowest priority.

[0034] In FIG. 5, queue 502 stores the packets with the highest priority, queue 504 stores the packets with a medium priority and queue 506 stores the packets with the lowest priority. In any event, each queue has its own priority and all packets stored in any one of the queues must have the same priority.

[0035] As illustrated in FIG. 5, queue 502 currently stores three packets, including packets 508-512. Queue 504 stores two packets, including packets 514 and 516. Queue 506 stores seven packets, including packets 518-530. Each packet is indicated as (n,m), where n is the destination SID and m is the packet length in bytes. For example, packet 508 has a priority of high, the cable modem 104 who is to receive packet 508 has a SID of 1 and packet 508 is 64 bytes in length. In addition, packet 508 arrived at CMTS 102 before packet 510, which in turn arrived before packet 512, as indicated by their positions in queue 502. It is important to note that packet 518 may arrive at CMTS 102 (e.g, WAN, Internet, intranets, fiber optic networks, wireless networks and satellite-based networks) before packet 508, but packet 508 is still likely to be sent to cable modem 104 first due to it having a higher priority. Note that the present invention also applies in the upstream with packets arriving from cable modem 104 and being sent out onto the WAN, Internet, and so forth, with low priority packets being dropped if the gateway to the WAN, Internet, and so forth, (or some other point in the path) was clogged such that queues are backed up. The operation of the present invention is described next with references to FIGS. 3 and 4.

C. Operation of the Present Invention

[0036] FIG. 3 is a high level flowchart that describes the efficient management of memory space by dropping lower priority packets that are slated for transmission according to an embodiment of the present invention. In FIG. 3, control starts at step 302. In step 302, CMTS 102 programs threshold value registers 204. As stated above, threshold value registers 204 include one register for each of the priority queues 202. Threshold value registers 204 represent the threshold number of packets that are allowed to be stored in its corresponding priority queue without an interrupt being sent to CMTS 102. Control then passes to step 304.

[0037] In step 304, MAC 112 determines whether the amount of outstanding packets in a given priority queue exceeds its threshold value. This is done by comparing the descriptor count register 206 and the threshold value register 204 for the priority queue. If the amount of outstanding packets exceeds its threshold value (i.e., is using up too much of the shared memory space in local SDRAM 114 that is reserved for priority queues 202), then control passes to step 306. Alternatively, the flowchart in FIG. 3 ends.

[0038] In step 306, MAC 112 sets an interrupt for CMTS 102. When the interrupt is set it indicates to CMTS 102 that local SDRAM 114 is getting full and some lower priority packets should be dropped in order to guarantee there will be enough memory to store higher priority packets. Control then passes to step 308.

[0039] In step 308, in response to the interrupt, CMTS 102 checks the status of priority queues 202 by determining the number of outstanding packets for each priority queue 202 via descriptor count registers 206. Control then passes to step 310.

[0040] In step 310, CMTS 102 makes a decision on the best way to drop packets from the lower priority queues and, if applicable, the number of packets to drop so as to guarantee that the packets that get dropped are in fact lower priority packets and that there is enough memory available for higher priority packets. Once CMTS 102 makes the decision, CMTS 102 indicates the number of packets to drop by writing a value for the number to drop into the appropriate packet drop register 210. As stated above, packet drop registers 210 includes one register for each of the priority queues 202. Packet drop registers 210 indicate the number of packets to drop from its respective priority queue when the packet drop feature is enabled. Control then passes to step 312.

[0041] In step 312, CMTS 102 writes a value to drop begin register 208 indicating that the packet drop feature of the invention is enabled. Control then passes to step 314.

[0042] In step 314, it has been determined by the present invention that local SDRAM 114 is getting full. Here, MAC 112 drops scheduled lower priority packets as indicated by CMTS 102. This frees up the fixed shared memory space, allowing for new packets to be queued or scheduled to be sent to cable modem 104. The flowchart in FIG. 3 ends at this point. How MAC 112 drops scheduled packets as indicated by CMTS 102 is described in more detail next with reference to FIG. 4.

[0043] In FIG. 4, control starts at step 402. In step 402, it is determined whether the number of packets to be dropped is greater than the number of outstanding packets for a particular priority queue. If so, then control passes to step 404. Alternatively, control passes to step 406.

[0044] In step 404, DMA unit 116 drops all of the outstanding packets in the relevant priority queue and continues to drop incoming packets until the number of packets to be dropped is met. For example, in FIG. 5, if the number of outstanding packets to be dropped from queue 506 is eight, then DMA unit 116 would start with the oldest packet (packet 518) and drop packets 518 through 530 (seven packets total). DMA unit 116 would then drop the next packet that is stored in queue 506 to make the total number of packets dropped from queue 506 equal eight.

[0045] In step 406, DMA unit 116 drops the number of packets in the relevant priority queue as indicated by the corresponding packet drop register. The flowchart in FIG. 4 ends at this point.

D. Example Environment of the Present Invention

[0046] CMTS 102, CMTS scheduler 110, cable modem scheduler 118 and MAC 112 may be implemented using computer 600 as shown in FIG. 6. Obviously, more than one of these functional components could be implemented on a single computer 600.

[0047] The present invention may be implemented using hardware, software or a combination thereof and may be implemented in a computer system or other processing system. In fact, in one embodiment, the invention is directed towards one or more computer systems capable of carrying out the functionality described herein. The computer system 600 includes one or more processors, such as processor 604. The processor 604 is connected to a communication bus 606. Various software embodiments are described in terms of this example computer system. After reading this description, it will become apparent to a person skilled in the relevant art how to implement the invention using other computer systems and/or computer architectures.

[0048] Computer system 600 also includes a main memory 608, preferably random access memory (RAM), and can also include a secondary memory 610. The secondary memory 610 can include, for example, a hard disk drive 612 and/or a removable storage drive 614, representing a floppy disk drive, a magnetic tape drive, an optical disk drive, etc. The removable storage drive 614 reads from and/or writes to a removable storage unit 618 in a well known manner. Removable storage unit 618, represents a floppy disk, magnetic tape, optical disk, etc. which is read by and written to by removable storage drive 614. As will be appreciated, the removable storage unit 618 includes a computer usable storage medium having stored therein computer software and/or data.

[0049] In alternative embodiments, secondary memory 610 may include other similar means for allowing computer programs or other instructions to be loaded into computer system 600. Such means can include, for example, a removable storage unit 622 and an interface 620. Examples of such can include a program cartridge and cartridge interface (such as that found in video game devices), a removable memory chip (such as an EPROM, or PROM) and associated socket, and other removable storage units 622 and interfaces 620 which allow software and data to be transferred from the removable storage unit 618 to computer system 600.

[0050] Computer system 600 can also include a communications interface 624. Communications interface 624 allows software and data to be transferred between computer system 600 and external devices. Examples of communications interface 624 can include a modem, a network interface (such as an Ethernet card), a communications port, a PCMCIA slot and card, etc. Software and data transferred via communications interface 624 are in the form of signals which can be electronic, electromagnetic, optical or other signals capable of being received by communications interface 624. These signals 626 are provided to communications interface via a channel 628. This channel 628 carries signals 626 and can be implemented using wire or cable, fiber optics, a phone line, a cellular phone link, an RF link and other communications channels.

[0051] In this document, the terms “computer program medium” and “computer usable medium” are used to generally refer to media such as removable storage device 618, a hard disk installed in hard disk drive 612, and signals 626. These computer program products are means for providing software to computer system 600.

[0052] Computer programs (also called computer control logic) are stored in main memory and/or secondary memory 610. Computer programs can also be received via communications interface 624. Such computer programs, when executed, enable the computer system 600 to perform the features of the present invention as discussed herein. In particular, the computer programs, when executed, enable the processor 604 to perform the features of the present invention. Accordingly, such computer programs represent controllers of the computer system 600.

[0053] In an embodiment where the invention is implemented using software, the software may be stored in a computer program product and loaded into computer system 600 using removable storage drive 614, hard drive 612 or communications interface 624. The control logic (software), when executed by the processor 604, causes the processor 604 to perform the functions of the invention as described herein.

[0054] In another embodiment, the invention is implemented primarily in hardware using, for example, hardware components such as application specific integrated circuits (ASICs). Implementation of the hardware state machine so as to perform the functions described herein will be apparent to persons skilled in the relevant art(s). In yet another embodiment, the invention is implemented using a combination of both hardware and software.

E. Conclusion

[0055] While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example, and not limitation. It will be apparent to persons skilled in the relevant art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention. This is especially true in light of technology and terms within the relevant art(s) that may be later developed. Thus, the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.