Methods and apparatuses that reduce noise in image signals

[0001] The embodiments described herein relate generally to the field of digital image processing, and more specifically to a methods and apparatuses for noise reduction in digital image processing.

[0002] Solid state imaging devices, including charge coupled devices (CCD), complementary metal oxide semiconductor (CMOS) imaging devices, and others, have been used in photo imaging applications. A solid state imaging device circuit includes a focal plane array of pixel cells or pixels as an image sensor, each cell including a photosensor, which may be a photogate, photoconductor, a photodiode, or other photosensor having a doped region for accumulating photo-generated charge. For CMOS imaging devices, each pixel has a charge storage region, formed on or in the substrate, which is connected to the gate of an output transistor that is part of a readout circuit. The charge storage region may be constructed as a floating diffusion region. In some CMOS imaging devices, each pixel may further include at least one electronic device such as a transistor for transferring charge from the photosensor to the storage region and one device, also typically a transistor, for resetting the storage region to a predetermined charge level prior to charge transference.

[0003] In a CMOS imaging device, the active elements of a pixel perform the necessary functions of: (1) photon to charge conversion; (2) accumulation of image charge; (3) resetting the storage region to a known state; (4) transfer of charge to the storage region; (5) selection of a pixel for readout; and (6) output and amplification of a signal representing pixel charge. Photo charge may be amplified when it moves from the initial charge accumulation region to the storage region. The charge at the storage region is typically converted to a pixel output voltage by a source follower output transistor.

[0004] CMOS imaging devices of the type discussed above are generally known as discussed, for example, in U.S. Pat. Nos. 6,140,630, 6,376,868, 6,310,366, 6,326,652, 6,204,524, and 6,333,205, assigned to Micron Technology, Inc.

[0005] One issue in the field of solid state imaging devices is noise reduction, particularly for devices with a small pixel size. As pixel size decreases, the effect of noise on image quality increases. Noise reduction techniques are used to improve the appearance of captured images. One method of noise reduction is to improve the fabrication process, however, such improvements are often cost prohibitive. An alternative solution is to apply noise filters during image processing. One noise reduction technique detects areas devoid of features (i.e., flat-field areas) and averages pixel signals in those areas of the image, as described in U.S. patent application Ser. No. 11/601,390, filed Nov. 17, 2006, which is incorporated herein by reference. This method can be implemented at a low cost in hardware logic, but can produce an unwanted side-effect of creating zipper artifacts, which are often conspicuous to the viewer. Accordingly, there is a need to provide quality, artifact-free flat-field noise reduction while maintaining a low hardware logic cost.

[0034] In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments that may be practiced. These embodiments are described in sufficient detail to enable those of ordinary skill in the art to make and use them, and it is to be understood that structural, logical, or procedural changes may be made to the specific embodiments disclosed.

[0035] Raw imaging data from an imaging device that uses a red, green, blue (RGB) Bayer pattern color filter array (CFA) consists of a mosaic of red, green, and blue pixel values and is often referred to as Bayer RGB data. FIGS. 1A-1D show four possible pixel configurations for a 5×5 portion (kernel) of a pixel array consisting of pixels associated with a Bayer pattern color filter array. FIG. 1A shows a red pixel R at location i, j. FIG. 1B shows a blue pixel B at location i, j. FIG. 1C shows a green pixel G at location i, j, where blue pixels B are alternated with green pixels G on row i. FIG. 1D shows a green pixel G at location i, j, where red pixels R are alternated with green pixels G on row i.

[0036] FIG. 2 illustrates a block diagram of a demosaicing process in accordance with an embodiment. It includes a demosaicing module 10 augmented with flat-field noise reduction (FFNR) module 30 and other associated processing modules. The demosaicing process includes the demosaic module 10, the flat-field noise reduction module 30, an edge detect module 20, a noise reduction module 40, a pixel noise weight module 60, a pixel noise luminance module 70. In addition, a sharpening signal generator 50, and a sharpening module 80 may also be provided. It should be appreciated that FIG. 2 refers to signals generally (e.g., RGB_D, etc.), but when a particular pixel signal p is being referred to, the signal will be referred to with the pixel's location i,j (e.g., RGB_D[i,j], etc.). As shown in FIG. 2, Bayer RGB pixel data (p) is input into the demosaic module 10, the edge detect module 20, and the flat-field noise reduction module 30. The demosaic module 10 takes red, green, or blue Bayer RGB image pixel signal values p_i,j, for example, the red pixel signal value from the red pixel R located at kernel location i, j (FIG. 1A) and outputs a demosaiced signal RGB_D[i,j] with a red component R_D[i,j], a green component G_D[i,j], and a blue component B_D[i,j] based on pixels within the kernel which are adjacent the red pixel at location i, j. The output signal RGB_D[i,j] can be calculated using any known demosaicing method. The edge detect module 20 assesses the presences of an edge near the pixel located at i,j having pixel signal p_i,j and outputs an edge value E_i,j (shown generally as signal E). An edge may be defined by an abruptness in intensity and/or color change between at least a first pixel signal and a second pixel signal. Any known edge detection technique can be used, and one method of calculating the edge value E_i,j is described in more detail below. The flat-field noise reduction module 30 demosaics the input pixel signal values p_i,j creating an output signal RGB_FFNR[i,j] (shown generally as signal RGB_FFNR) with each pixel having a red component R_FFNR[i,j], green component G_FFNR[i,j], and blue component B_FFNR[i,j] also based on pixels within a kernel adjacent a particular pixel p_i,j. The output signal, RGB_FFNR[i,j], can be calculated using any known flat-field demosaicing method. One method of calculating the output signal RGB_FFNR[i,j] is described in more detail below with reference to FIGS. 3-13. It should be appreciated that the demosaic module 10, the edge detect module 20, and the flat-field noise reduction module 30 may, but need not, use the same size pixel kernel to calculate their respective outputs; further, any size pixel kernel may be selected.

[0037] The demosaiced outputs of the demosaic module 10 and the flat-field noise reduction module 30 are processed in the noise reduction module 40 to produce a noise reduced output RGB_NR[i,j] (shown generally as signal RGB_NR). The noise reduction module 40 may select the RGB_D[i,j] signal when a sufficiently large edge value (as compared to a predetermined threshold) is output from the edge detect module 20; may select the RGB_FFNR[i,j] signal when a sufficiently small edge value (as compared to a predetermined threshold) is output from the edge detect module 20 (e.g., in flat-field regions devoid of edges); or may blend the RGB_D[i,j] and RGB_FFNR[i,j] signals as a weighted sum of the two signals based on the output of the edge detect module 20 (e.g., with smaller edge values, RGB_FFNR[i,j] would be given a larger weight than RGB_D[i,j] and with larger edge values, RGB_D[i,j] would be given a larger weight than RGB_FFNR[i,j]). In a desired embodiment, the noise reduced signal, RGB_NR[i,j], output from the noise reduction module 40 is derived using the following formulas:
R_NR[i,j]=w_FFNR[i,j]·R_D[i,j]+(1−w_FFNR[i,j])·R_FFNR[i,j]  (1)
G_NR[i,j]=w_FFNR[i,j]·G_D[i,j]+(1−w_FFNR[i,j])·G_FFNR[i,j]  (2)
B_NR[i,j]=w_FFNR[i,j]·B_D[i,j]+(1−w_FFNR[i,j])·B_FFNR[i,j]  3)
If the weight w_FFNR[i,j] is 0, then the noise reduction module 40 selects the output RGB_FFNR[i,j] from the flat-field noise reduction module 30. If the weight w_FFNR[i,j] is 1, then the noise reduction module 40 selects the output RGB_D[i,j] from the demosaic module 10. If the weight w_FFNR[i,j] is between 0 and 1, then the noise reduction module 40 outputs a signal RGB_NR[i,j] derived from the outputs of both the flat-field noise reduction module 30 and the demosaic module 10. A desired implementation utilizes a pixel noise weight module 60 to calculate the weight w_FFNR[i,j] according to:

[0038] $\begin{array}{cc}{w}_{\mathrm{FFNR}\left[i,j\right]}=\{\begin{array}{cc}0,& v_{\mathrm{FFNR}\left[i,j\right]}\le 0\\ 1,& v_{\mathrm{FFNR}\left[i,j\right]}\ge 1\\ v_{\mathrm{FFNR}\left[i,j\right]},& 0<v_{\mathrm{FFNR}\left[i,j\right]}<1\end{array}& \left(4\right)\end{array}$
where v_FFNR[i,j] is a weight calculated according to:
v_FFNR[i,j]=(E_i,j−T_FFNR[i,j])·G_FFNR,r[i,j]  (5)
where E_i,j is the edge value from edge detect module 20, G_FFNR,r[i,j] is a predetermined rate of transition from flat-field noise reduction averaging to no averaging as a function of pixel brightness (e.g., G_FFNR,r[i,j]=20), and T_FFNR[i,j] is a threshold value based on an offset T_{FFNR,min[i,j]}, a constant specifying a pixel signal value such that any lesser value will always result in full-strength flat-field noise reduction averaging (e.g., T_{FFNR,min[i,j]}=0). T_FFNR[i,j] is calculated according to:
T_FFNR[i,j]=T_{FFNR,min[i,j]}+Y_FFNR[i,j]·G_FFNR,p[i,j]  (6)
where G_FFNR,p[i,j] is a pixel noise model coefficient subjecting brighter pixels to more or less averaging than darker ones (e.g., G_FFNR,p[i,j]=0.33). Constants T_FFNR,min and G_FFNR,p are selected based on sensor response characterization such that image features having amplitudes approximately equal to or less than sensor noise are subjected to noise reduction. Y_FFNR[i,j] is the pixel luminance (i.e., a weighted sum of the pixel signal's red, green, and blue components) of the output of the flat-field noise reduction module 30. Y_FFNR[i,j] can be calculated using an applicable luminance formula known in the art or derived from sensor colorimetric properties using techniques known in the art, for example, the standard red, green, blue color space (sRGB) or the International Telecommunication Union Radiocommunication Sector (ITU-R) standard ITU-R BT.601. A desired implementation of pixel luminance utilizes the ITU Radiocommunication Sector standard ITU-R BT.601 such that:
Y_FFNR[i,j]=0.299·R_FFNR[i,j]+0.587·G_FFNR[i,j]+0.114·B_FFNR[i,j]  (7)
Equation (7) can be simplified (for example, for ease of implementation in hardware) to:
Y_FFNR[i,j]=(5*R_FFNR[i,j]+9*G_FFNR[i,j]+2*B_FFNR[i,j])/16   (8)

[0039] An edge detection method used by module 20 examines pairs of neighboring pixels and outputs the maximum absolute value of the difference between pixel signal values for one of the pairs (edge value), E_i,j. Referring now to FIGS. 1C and 1D, the edge value, E_i,j, for green pixel signals p_i,j can be calculated according to:
d_1[i,j]=|p_i+1,j+1−p_i−1,j−1|  (9)
d_2[i,j]=|p_i−1,j−p_i+1,j+2|  (10)
d_3[i,j]=|p_i,j−1−p_i+2,j+1|  (11)
d_4[i,j]=|p_i+1,j−p_i−1,j+2|  (12)
d_5[i,j]=|p_i+2,j−1−p_i,j+1|  (13)
d_6[i,j]=|p_i,j−1−p_i−2,j+1|  (14)
d_7[i,j]=|p_i,j+1−p_i−2,j−1|  (15)
d_8[i,j]=|p_i+1,j+2−p_i−1,j|  (16)
d_9[i,j]=|p_i+1,j−p_i−1,j−2|  (17)
E_i,j=max(d_1[i,j],d_2[i,j],d_3[i,j],d_4[i,j],d_5[i,j],d_6[i,j],d_7[i,j],d_8[i,j],d_9[i,j])   (18)
Referring to FIGS. 1A and 1B, the edge value, E_i,j, for red and blue pixel signals p_i,j can be calculated according to:
d_1[i,j]=|p_i+1,j+1−p_i−1,j−1|  (19)
d_2[i,j]=|p_i,j+1−p_i,j−1|  (20)
d_3[i,j]=|p_i+1,j−p_i−1,j|  (21)
d_4[i,j]=|p_i,j−p_i,j−2|  (22)
d_5[i,j]=|p_i,j−p_i,j+2|  (23)
d_6[i,j]=|p_i,j−p_i+2,j|  (24)
d_7[i,j]=|p_i,j−p_i−2,j|  (25)
E_i,j=max(d_1[i,j],d_2[i,j],d_3[i,j],d_4[i,j],d_5[i,j],d_6[i,j],d_7[i,j])   (26)

[0040] The output of the noise reduction module 40 may be sharpened to produce a sharpened final output RGB_i,j (shown generally as signal RGB). Sharpening can be produced by a sharpening module 80 as a function of the output (RGB_NR) of the noise reduction module 40 and a signal from the sharpening signal generator module 50 (ΔY). The sharpening module 80 takes the output of the sharpening signal generator 50, a high-frequency sharpening signal ΔY_i,j (functioning as a high-pass filter), which is multiplied by a gain, G_A[i,j], and then added to the output of the noise reduction module 40 RGB_NR[i,j] to produce a sharpened, noise reduced signal RGB_i,j. The sharpening module 80 emulates an unsharp mask operation, without requiring additional memory and logic to calculate luminance signals in pixels surrounding the pixel being demosaiced (the pixel located at i,j) as required by conventional unsharp mask operations. The sharpened final output RGB_i,j of the sharpening module 80 is calculated according to:
R_i,j=R_NR[i,j]+G_A[i,j]·ΔY_i,j   (27)
G_i,j=G_NR[i,j]+G_A[i,j]·ΔY_i,j   (28)
B_i,j=B_NR[i,j]+G_A[i,j]·ΔY_i,j   (29)
where G_A[i,j] is the sharpening gain that controls the amount of sharpening applied to the image, ΔY_i,j, an aperture correction value, is calculated by the sharpening signal generator 50 as follows:
ΔY_i,j=max(|Y_D[i,j]−Y_FFNR[i,j]|−T_A[i,j], 0)·sgn(Y_D[i,j]−Y_FFNR[i,j])   (30)
where sgn(Y_D[i,j]−Y_FFNR[i,j]) is the sign of Y_D[i,j]−Y_FFNR[i,j] (i.e., −1 when Y_D[i,j]−Y_FFNR[i,j]<0, 1 when Y_D[i,j]−Y_FFNR[i,j]>0, and 0 when Y_D[i,j]−Y_FFNR[i,j]=0) and Y_D[i,j] and Y_FFNR[i,j] are pixel luminance values output by demosaicing module 10 and the flat-field noise reduction module 30, respectively. T_A[i,j] specifies the minimum luminance difference value necessary to produce a sharpening effect to a pixel with luminance Y_D[i,j] as calculated by the pixel noise luminance module 70 as follows:
T_A[i,j]=T_A,min[i,j]+G_A,T[i,j]·Y_D[i,j]  (31)
T_A,min[i,j] is the minimum value for T_A[i,j] and G_A,T[i,j] is a pixel noise model coefficient allowing for sharpening of brighter pixels. T_A[i,j] and G_A,T[i,j] are selected based on image sensor response such that image features having amplitudes of approximately equal to or less than sensor noise are not amplified by sharpening. It should be appreciated that Y_D[i,j] and Y_FFNR[i,j] may be calculated using techniques known in the art, such as a formula appropriate to the color space corresponding to the pre-color-correction sensor responses. One implementation calculates Y_D[i,j] using the same coefficients as Y_FFNR[i,j] in Equations (7) and (8) above, such that:
Y_D[i,j]=0.299·R_D[i,j]+0.587˜G_D[i,j]+0.114·B_D[i,j]  (32)
Equation (32) can be simplified (for example, for ease of implementation in hardware) to:
Y_D[i,j]=(5*R_D[i,j]+9*G_D[i,j]+2*B_D[i,j])/16   (33)

[0041] While a desired implementation allows for the variance of all coefficients as a function of pixel position (i,j) in the image sensor array (for example, to compensate for higher noise at an image sensor's periphery due to digital gain employed by additional modules in the image sensor, such as, for example, a lens vignetting module), it should be appreciated that these values may be constant and not vary as a function of pixel position (i,j), for example, G_A,T, G_A, G_FFNR,p, and G_FFNR,r.

[0042] In one embodiment, the flat-field noise reduction module 30 (FIG. 2) uses 5×5 kernels as shown in FIGS. 1A-1D to calculate an averaged, noise-reduced demosaiced output RGB_FFNR[i,j]. FIGS. 1A-1D show the viable color patterns for 5×5 kernels having a Bayer color filter array. Due to the Bayer pattern, the calculation of the flat-field noise reduced response varies depending on the color of the pixel being demosaiced (e.g., red, green, or blue) and the color channel of the pixel being demosaiced (e.g., blue, greenblue (green pixels in the same row as blue pixels), greenred (green pixels in the same row as red pixels), and red).

[0043] FIG. 3 shows four green pixel configurations (kernel types A-D) selected from a subset (shaded) of the pixels of the four 5×5 kernels shown in FIGS. 1A-1D (for example, FIG. 1A may be represented by kernel type B, FIG. 1B may be represented by kernel type C, FIG. 1C may be represented by kernel type D, and FIG. 1D may be represented by kernel type A). Kernel types A-D are used to average green pixel responses. The block arrows illustrate how the kernel shapes change moving one pixel left or right along a horizontal edge, up or down along a vertical edge, and diagonally along a diagonal edge. The flat-field noise reduction module 30 (FIG. 2) output for the green component G_FFNR[i,j] of a Bayer RGB pixel signal p_i,j, is constructed as a weighted sum of raw pixel responses. For ease of optimization, only a 3×3 kernel is considered. However, it should be appreciated that any size kernel may be used to generate the flat-field noise reduced output. Kernel types A and B of FIG. 3 match kernel types D and C respectively, accordingly all calculations are derived for kernel types A and B, but may be applied to types D and C respectively. To maintain image symmetry, symmetric pixels are assigned the same pixel weight (e.g., pixel weights a and b for green pixels in kernel type A and pixel weight c for green pixels in kernel type B).

[0044] Pixel weights may be selected such that the flat-field noise reduction module 30 (FIG. 2) output does not depend on the shape of the kernel. If the output depended on the shape of the kernel, the flat-field noise reduction module 30 (FIG. 2) would produce varying responses for pixels lying along edges. Such undesirable variation may appear as zipper artifacts along the edges of the image.

[0045] To derive pixel weights for kernels of various shapes and colors to produce zipper-free noise reduction, viable kernel types may be considered; edges crossing those kernel types at various locations may be considered; restrictions and dependencies on pixel weights may be generated such that the output is not kernel shape dependent; restrictions and dependencies may be expressed as a system of equations; and the equations may be solved to minimize noise. Accordingly, for kernel type A, the green component G_FFNR[i,j] can be expressed as:
G_FFNR[i,j]=a·(p_i−1,j−1+p_i+1,j+1+p_i+1,j−1+p_i−1,j+1)+b·p_i,j   (34)
and the green component G_FFNR[i,j] for kernel type B can be expressed as:
G_FFNR[i,j]=c·(p_i,j−1+p_i,j+1p_i+1,j+p_i−1,j)   (35)
For reasons of symmetry, pixels marked “a” in kernel type A must have equal pixel weights, therefore:
4a+b=1   (36)
and pixels marked “c” in kernel type B must have equal pixel weights, therefore:
4c=1(i.e., therefore) c=0.25   (37)

[0046] Additional constraints can be derived when edges crossing kernel types A-D at various locations are considered. Since flat-field noise reduction module 30 (FIG. 2) output is effectively disabled in the presence of edges (see Equations (1)-(3)), only movements along edges are considered. Movements across edges are not considered. The edges considered are shown in FIGS. 4A-4B and FIGS. 5A-5D.

[0047] FIGS. 4A-4B show a horizontal edge passing through a flat-field noise reduction kernel. The horizontal edge may be in at least two positions, including a horizontal edge 210 passing between rows i−1 and i (FIG. 4A) and a horizontal edge 220 passing between rows i−1 and i−2 (FIG. 4B). Other cases of horizontal and vertical edges can be derived by rotating FIGS. 4A-4B by 90, 180, and 270 degrees.

[0048] FIGS. 5A-5D show a diagonal edge passing through a flat-field noise reduction kernel. The diagonal edge may be in at least four positions, including position 310 covering only pixel i−2, j−2 (FIG. 5A), position 320 covering pixels from i−1, j−2 to i−2, j−1 (FIG. 5B), position 330 covering pixels from i, j−2 to i−2, j (FIG. 5C), and position 340 covering pixels i+1, j−2 to i−2, j+1 (FIG. 5D). Other cases of diagonal edges can be derived by rotating FIGS. 5A-5D by 90, 180, and 270 degrees.

[0049] Green kernel types remains identical along 45/135 degree diagonal edges (i.e., kernel type A is identical to kernel type D and kernel type B is identical to kernel type C), thus, no additional constraints on kernel pixel weights are imposed for the diagonal movement cases. When considering moving between kernel types along horizontal and vertical edges, kernel types alternate as shown in FIGS. 6A-6D. Only edges passing between row i−1 and i as shown in FIG. 6A and similar cases resulting from rotation as shown in FIGS. 6B-6D affect kernel output, thus an additional constraint is:
a+a=c2a=0.25a=0.125.   (38)
Solving equation (36) for b, b=1−4ab=1−4*0.125b=0.5. Therefore, a=0.125, b=0.5, and c=0.25. Equations (34)-(35) can be rewritten in terms of the calculated values for pixel weights a-c. Accordingly, for kernel type A, the green component G_FFNR[i,j] can be expressed as:
G_FFNR[i,j]=0.125·(p_i−1,j−1+p_i+1,j+1p_i+1,j−1+p_i−1,j+1)+0.5·p_i,j   (39)
and the green component G_FFNR[i,j] for kernel type B can be expressed as:
G_FFNR[i,j]=0.25·(p_i,j−1+p_i,j+1+p_i+1,j+p_i−1,j)   (40)

[0050] FIG. 7 shows four red and blue pixel configurations (kernel types E-H) used in the flat-field noise reduction module 30 (FIG. 2) and selected from a subset (shaded) of the pixels of the four 5×5 kernels shown in FIGS. 1A-1D (for example for red pixels, FIG. 1A may be represented by kernel type H, FIG. 1B may be represented by kernel type E, FIG. 1C may be represented by kernel type F, and FIG. 1D may be represented by kernel type G and for blue pixels FIG. 1A may be represented by kernel type E, FIG. 1B may be represented by kernel type H, FIG. 1C may be represented by kernel type G, and FIG. 1D may be represented by kernel type F). For ease of processing, kernel type H does not utilize the red or blue pixels located in the corners of the kernel (i.e., pixels i−2, j−2; i+2, j−2; i−2, j+2; or i+2, j+2); it should be appreciated that these pixels may be utilized to average red and blue pixel responses. Kernel types E-H are used to average red and blue pixel responses. The block arrows illustrate how the kernel shapes change moving one pixel left or right along a horizontal edge, up or down along a vertical edge, and diagonally along a diagonal edge. As with the green G_FFNR[i,j] component, the flat-field noise reduction module 30 (FIG. 2) output for the red R_FFNR[i,j] and blue B_FFNR[i,j] components of a Bayer RGB pixel p_i,j, is constructed as a weighted sum of the raw pixel responses. To maintain image symmetry, symmetric pixels are assigned the same pixel weight (e.g., pixel weight h for pixels in kernel type E, pixel weights e and d for pixels in kernel types F and G, and pixel weights f and g for pixels in kernel type H). As with green pixels, since flat-field noise reduction is effectively disabled in the presence of edges, only movements along edges are considered and not across. Edges must be at least one pixel away from the pixel being demosaiced.

[0051] There are three distinct red and blue kernel types, E, F, and H. Kernel type G is identical to kernel type F rotated 90 degrees. For kernel type E, the output of the flat-field noise reduction module 30 (FIG. 2) is defined as:
R_FFNR[i,j]=h·(p_i−1,j−1+p_i−1,j+1+p_i+1,j−1+p_i+1,j+1)   (41)
B_FFNR[i,j]=h·(p_i−1,j−1+p_i−1,j+1+p_i+1,j−1+p_i+1,j+1)   (42)
The output of kernel type F is calculated as:
R_FFNR[i,j]=d·(p_i−1,j−2+p_i−1,j+2+p_i+1,j−2+p_i+1,j+2)+e·(p_i−1,j+p_i+1,j)   (43)
B_FFNR[i,j]=d·(p_i−1,k−2+p_i−1,j+2+p_i+1,j−2+p_i+1,j+2)+e·(p_i−1,j+p_i+1,j)   (44)
The output of kernel type G is calculated as:
R_FFNR[i,j]=d·(p_i−2,j−1+p_i−2,j+1+p_i+2,j−1+p_i+2,j+1)+e·(p_i,j−1+p_i,j+1)   (45)
B_FFNR[i,j]=d·(p_i−2,j−1+p_i−2,j+1+p_i+2,j−1+p_i+2,j+1)+e·(p_i,j−1+p_i,j+1)   (46)
The output of kernel type H is:
R_FFNR[i,j]=g·(p_i,j−2+p_i,j+2+p_i−2,j+p_i+2,j)+f·p_i,j   (47)
B_FFNR[i,j]=g·(p_i,j−2+p_i,j+2+p_i−2,j+p_i+2,j)+f·p_i,j   (48)
For kernel type E:
4h=1h=0.25   (49)
For kernel types F and G:
2e+4d=1   (50)
For kernel type H:
4g+f=1   (51)
As with the green kernel types A-D, additional constraints can be derived when edges crossing kernel types E-H at various locations are considered. For a horizontal edge passing between row i−1 and i of kernel types E and F, kernel types E and F will alternate as shown in FIG. 8, therefore an additional constraint is:
2h=2d+e   (52)
For a horizontal edge passing between row i−2 and i−1 of kernel types E and F, kernel types E and F will alternate as shown in FIG. 9, but the edge of the non-flat field portion of the image does not cover any pixels of interest in those kernels and thus no additional constraints can be derived. For horizontal edges passing anywhere between rows i and i−2 (and its rotated equivalents) kernel types G and H will alternate as shown in FIG. 10 (while FIG. 10 only illustrates the edge passing between rows i−1 and i, an edge passing between rows i−2 and i−1 would result in the same pixels of interest being covered by the non-flat field portion of the image), therefore:
2d=g   (53)
Solving equation (51) for f and substituting from equations (50) and (53) yields:
f=1−4gf=1−4(2d)f=1−8df=1−2(1−2e)f=1−2+4ef=4e−1   (54)

[0052] Kernel types F and G alternate along a diagonal edge, as shown in FIGS. 11A-11B, but the contribution of pixels on either side of the edge remains identical regardless of kernel type so no new constraints are imposed.

[0053] Kernel types E and H alternate along a diagonal edge as shown in FIGS. 12A-12B. Since none of the kernel pixels are covered by the non-flat field portion of the image in FIG. 12A, no new constraints are imposed. However, as shown in FIG. 12B, an edge passing closer to the center yields a new constraint:
h=2g0.25=2g (substituting h from Eqn. (49))g=0.125.   (55)

• [0054] Solving Eqn. (51) for ff=1−4g; f=1−4(0.125)f=0.5.
• [0055] Solving Eqn. (54) for ef=4e−1e=(f+1)/4e=(0.5+1)/4e=0.375.
• [0056] Solving Eqn. (53) for d2d=gd=g/2d=0.125/2d=0.0625.
• [0057] Therefore, d=0.0625, e=0.375, f=0.5, g=0.125, and h=0.25. Equations (41)-(48) can be rewritten in terms of the calculated values for pixel weights d-h. For kernel type E, the output of the flat-field noise reduction module 30 (FIG. 2) can be expressed as:
  R_FFNR[i,j]=0.25·(p_i−1,j−1+p_i−1,j+1+p_i+1,j−1+p_i+1,j+1)   (56)
  B_FFNR[i,j]=0.25·(p_i−1,j−1+p_i−1,j+1+p_i+1,j−1+p_i+1,j+1)   (57)
  The output of kernel type F can be expressed as:
  R_FFNR[i,j]=0.0625·(p_i−1,j−2+p_i−1,j+2+p_i+1,j−2+p_i+1,j+2)+0.375·(p_i−1,j+p_i+1,j)   (58)
  B_FFNR[i,j]=0.0625·(p_i−1,j−2+p_i−1,j+2+p_i+1,j−2+p_i+1,j+2)+0.375·(p_i−1,j+p_i+1,j)   (59)
  The output of kernel type G can be expressed as:
  R_FFNR[i,j]=0.0625·(p_i−2,j−1+p_i−2,j+1+p_i+2,j−1+p_i+2,j+1)+0.375·(p_i,j−1+p_i,j+1)   (60)
  B_FFNR[i,j]=0.0625·(p_i−2,j−1+p_i−2,j+1+p_i+2,j−1+p_i+2,j+1)+0.375·(p_i,j−1+p_i,j+1)   (61)
  The output of kernel type H can be expressed as:
  R_FFVR[i,j]=0.125·(p_i,j−2+p_i,j+2+p_i−2,j+p_i+2,j)+0.5·p_i,j   (62)
  B_FFNR[i,j]=0.125·(p_i,j−2+p_i,j+2+p_i−2,j+p_i+2,j)+0.5·p_i,j   (63)

[0058] It should be appreciated that while the above pixel weights (pixel weights a-c for green kernels and pixel weights d-h for red and blue kernels) have been selected to reduce zipper effect, pixel weights can also be selected for noise reduction or for a combination of reduced zipper effect and improved noise reduction. In a desired embodiment, the output of kernel types F, G, and H (FIG. 7) are represented in terms of pixel weights alpha (α) and beta (β) rather than in terms of pixel weights d, e, f, and g, reducing the number of variables from four to two for ease of implementation. As shown in FIG. 13, alpha is defined to equal pixel weight f to specify how much pixel weight is placed on the kernel center in kernel type H as compared to the pixel weight g of the pixels further from the kernel center. Similarly, beta specifies how much pixel weight is placed on pixels near the kernel center in kernel types F and G compared to the pixel weight d of the pixels further away.
α=f   (64)
1−α=4g   (65)
β=2e   (66)
1−β=4d   (67)
α=2β−1 (because f=4e−1)   (68)
β=(α+1)/2   (69)
The output of kernel type F can be expressed in terms of alpha and beta as:

[0059] $\begin{array}{cc}{R}_{\mathrm{FFNR}\left[i,j\right]}=\frac{\left(1-\beta \right)}{4}·\left(p_{i-1,j-2}+p_{i-1,j+2}+p_{i+1,j-2}+p_{i+1,j+2}\right)+\frac{\beta }{2}·\left(p_{i-1,j}+p_{i+1,j}\right)& \left(70\right)\\ B_{\mathrm{FFNR}\left[i,j\right]}=\frac{\left(1-\beta \right)}{4}·\left(p_{i-1,j-2}+p_{i-1,j+2}+p_{i+1,j-2}+p_{i+1,j+2}\right)+\frac{\beta }{2}·\left(p_{i-1,j}+p_{i+1,j}\right)& \left(71\right)\end{array}$
The output of kernel type G can be expressed in terms of alpha and beta as:

[0060] $\begin{array}{cc}{R}_{\mathrm{FFNR}\left[i,j\right]}=\frac{\left(1-\beta \right)}{4}·\left(p_{i-2,j-1}+p_{i-2,j+1}+p_{i+2,j-1}+p_{i+2,j+1}\right)+\frac{\beta }{2}·\left(p_{i,j-1}+p_{i,j+1}\right)& \left(72\right)\\ B_{\mathrm{FFNR}\left[i,j\right]}=\frac{\left(1-\beta \right)}{4}·\left(p_{i-2,j-1}+p_{i-2,j+1}+p_{i+2,j-1}+p_{i+2,j+1}\right)+\frac{\beta }{2}·\left(p_{i,j-1}+p_{i,j+1}\right)& \left(73\right)\end{array}$
The output of kernel type H can be expressed in terms of alpha and beta as:

[0061] $\begin{array}{cc}{R}_{\mathrm{FFNR}\left[i,j\right]}=\frac{\left(1-\alpha \right)}{4}·\left(p_{i,j-2}+p_{i,j+2}+p_{i-2,j}+p_{i+2,j}\right)+\alpha ·p_{i,j}& \left(74\right)\\ B_{\mathrm{FFNR}\left[i,j\right]}=\frac{\left(1-\alpha \right)}{4}·\left(p_{i,j-2}+p_{i,j+2}+p_{i-2,j}+p_{i+2,j}\right)+\alpha ·p_{i,j}& \left(75\right)\end{array}$

[0062] Alpha and beta have been defined in terms of pixel weights f and e which were derived to reduce the zipper effect in images. Accordingly, to maximize zipper effect reduction:
α=0.5   (76)
β=0.75   (77)
However, it may be desirable to calculate alpha and beta for noise optimization. For example, assuming for a flat-field gray (i.e., red equals green equals blue) area all pixel responses have a standard deviation of one. Noise values for kernel type H and kernel types F and G can be derived as a function of their pixel weight mixing assignments:
σ_α=√{square root over ((α·1)²+4·((1−α)/4·1)²)}{square root over ((α·1)²+4·((1−α)/4·1)²)}  (78)
σ_β=√{square root over (4·((1−β)/4·1)²+2·(β/2·1)²)}{square root over (4·((1−β)/4·1)²+2·(β/2·1)²)}  (79)
σ=√{square root over (σ_α²+σ_β²)}  (80)
Noise reduction is optimized at approximately:
α=0.15   (81)
β=0.575   (82)

[0063] Alpha and beta may then be selected to maximize noise reduction and zipper effect (0.15<=α<=0.5 and 0.575<=β<=0.75), with ideal optimization selection in a preferred embodiment occurring at:
α=84/256=0.328125   (83)
β=172/256=0.671875   (84)
A pixel signal p for a pixel at location i,j can be demosaiced in the flat-field noise reduction module 30 (FIG. 2) as a function of the weighted sums of the values of the red, green, and blue pixels in the kernel containing the pixel at location i,j. A weighted select based on the presence of edges (as detected by the edge detect module 20 (FIG. 2)) can then be performed in the noise reduction module 40 (FIG. 2), selectively combining the outputs of the two demosaiced signals (i.e., the demosaic module 10 (FIG. 2) and the flat-field noise reduction module 30 (FIG. 2)) producing a noise reduced signal. The noise reduced signal is then sharpened in the sharpening module 80 (FIG. 2) based on a calculated luminance of the two demosaiced signals.

[0064] FIG. 14A illustrates a block diagram of an exemplary system-on-a-chip (SOC) imaging device 900 constructed in accordance with an embodiment. The imaging device 900 comprises a sensor core 805 that communicates with an image flow processor 910 that is also connected to an output interface 930. A phase locked loop (PLL) 844 is used as a clock for the sensor core 805. The image flow processor 910, which is responsible for image and color processing, includes interpolation line buffers 912, decimator line buffers 914, and a pixel processing pipeline 920. One of the functions of the color processor pipeline 920 is to perform pixel processing operations, such as, for example, demosaicing in accordance with the disclosed embodiments. The pixel processing pipeline 920 includes, among other things, a statistics engine 922. The output interface 930 includes an output first-in-first-out (FIFO) parallel output 932 and a serial Mobile Industry Processing Interface (MIPI) output 934. The user can select either a serial output or a parallel output by setting registers within the chip. An internal register bus 940 connects read only memory (ROM) 942, a microcontroller 944 and a static random access memory (SRAM) 946 to the sensor core 805, image flow processor 910 and the output interface 930.

[0065] FIG. 14B illustrates a sensor core 805 used in the FIG. 14A imaging device 900. The sensor core 805 includes an imaging sensor 802, which is connected to analog processing circuitry 808 by a greenred/greenblue channel 804 and a red/blue channel 806. Although only two channels 804, 806 are illustrated, there are effectively two green channels, one red channel, and one blue channel, for a total of four channels. The greenred (i.e., Green1) and greenblue (i.e., Green2) signals are readout at different times (using channel 804) and the red and blue signals are readout at different times (using channel 806). The analog processing circuitry 808 outputs processed greenred/greenblue signals G1/G2 to a first analog-to-digital converter (ADC) 814 and processed red/blue signals R/B to a second analog-to-digital converter 816. The outputs of the two analog-to-digital converters 814, 816 are sent to a digital processor 830.

[0066] Connected to, or as part of, the imaging sensor 802 are row and column decoders 811, 809 and row and column driver circuitry 812, 810 that are controlled by a timing and control circuit 840. The timing and control circuit 840 uses control registers 842 to determine how the imaging sensor 802 and other components are controlled, for example, controlling the mode of operation of the imaging sensor 802. As set forth above, the PLL 844 serves as a clock for the components in the core 805.

[0067] The imaging sensor 802 comprises a plurality of pixel circuits arranged in a predetermined number of columns and rows. In operation, the pixel circuits of each row in imaging sensor 802 are all turned on at the same time by a row select line and the pixel circuits of each column are selectively output onto column output lines by a column select line. A plurality of row and column lines are provided for the entire imaging sensor 802. The row lines are selectively activated by row driver circuitry 812 in response to the row address decoder 811 and the column select lines are selectively activated by a column driver 810 in response to the column address decoder 809. Thus, a row and column address is provided for each pixel circuit. The timing and control circuit 840 controls the address decoders 811, 809 for selecting the appropriate row and column lines for pixel readout, and the row and column driver circuitry 812, 810, which apply driving voltage to the drive transistors of the selected row and column lines.

[0068] Each column contains sampling capacitors and switches in the analog processing circuit 808 that read a pixel reset signal Vrst and a pixel image signal Vsig for selected pixel circuits. Because the core 805 uses greenred/greenblue channel 804 and a separate red/blue channel 806, circuitry 808 will have the capacity to store Vrst and Vsig signals for greenred, greenblue, red, and blue pixel signals. A differential signal (Vrst-Vsig) is produced by differential amplifiers contained in the circuitry 808 for each pixel. Thus, the signals G1/G2 and R/B are differential signals that are then digitized by a respective analog-to-digital converter 814, 816. The analog-to-digital converters 814, 816 supply digitized G1/G2, R/B pixel signals to the digital processor 830, which forms a digital image output (e.g., a 10-bit digital output). The digital processor 830 performs pixel processing operations. The output is sent to the image flow processor 910 (FIG. 14A).

[0069] Although the sensor core 805 has been described with reference to use with a CMOS imaging sensor, this is merely one example sensor core that may be used. Embodiments of the invention may also be used with other sensor cores having a different readout architecture. While the imaging device 900 (FIG. 14A) has been shown as a system-on-a-chip, it should be appreciated that the embodiments are not so limited. Other imaging devices, such as, for example, a stand-alone sensor core 805 coupled to a separate signal processing chip could be used in accordance with the embodiments. While the demosaicing has been described as occurring in the color processor pipeline 920 (FIG. 14A), it should be appreciated that demosaicing can be performed in the digital processing 830 (FIG. 14B). Additionally, raw RGB imaging data can be output from the 10-bit data output (FIG. 14B) and stored and demosaiced elsewhere, for example, in a system as described in relation to FIG. 15 or in a stand-alone image processing system.

[0070] FIG. 15 shows a typical system 600, such as, for example, a camera. The system 600 is an example of a system having digital circuits that could include an imaging device 900. Without being limiting, such a system could include a computer system, camera system, scanner, machine vision, vehicle navigation system, video phone, surveillance system, auto focus system, star tracker system, motion detection system, image stabilization system, and other systems employing an imaging device 900.

[0071] System 600, for example, a camera system, includes a lens 680 for focusing an image on the imaging device 900 when a shutter release button 682 is pressed. System 600 generally comprises a central processing unit (CPU) 610, such as a microprocessor that controls camera functions and image flow, and communicates with an input/output (I/O) device 640 over a bus 660. The imaging device 900 also communicates with the CPU 610 over the bus 660. The system 600 also includes random access memory (RAM) 620, and can include removable memory 650, such as flash memory, which also communicates with the CPU 610 over the bus 660. The imaging device 900 may be combined with the CPU 610, with or without memory storage on a single integrated circuit, such as, for example, a system-on-a-chip, or on a different chip than the CPU 610. As described above, raw RGB image data from the imaging sensor 802 (FIG. 14B) can be output from the imaging device 900 and stored, for example in the random access memory 620 or the CPU 610. Demosaicing can then be performed on the stored data by the CPU 610, or can be sent outside the camera and stored and operated on by a stand-alone processor, e.g., a computer, external to system 600 in accordance with the embodiments described herein.

[0072] Some of the advantages of the demosaicing and noise reduction methods disclosed herein include minimizing undesirable artifacts while maximizing noise suppression. Additionally, the disclosed demosaicing and noise reduction methods are simple to implement in hardware or software at a low cost. That is, the methods described above can be implemented in a pixel processing circuit, which can be part of the pixel processing pipeline 920 (FIG. 14A). The pixel processing circuit can be implemented as, for example, hardware logic, a programmed processor, a combination of the two, or with other signal processing circuits. For example, the methods described above can be implemented in computer instructions and stored in a computer readable medium to perform a method of adjusting a color imaging pixel signal from raw imaging data as a function of the weighted sums of a first and second calculated demosaic value of the pixel signal being adjusted, and a calculated edge value to produce a noise reduced value. Additionally, the computer instructions may be configured to calculate a sharpening value to be applied to the noise reduced value.

[0073] While the embodiments have been described in detail in connection with desired embodiments known at the time, it should be readily understood that the claimed invention is not limited to the disclosed embodiments. Rather, the embodiments can be modified to incorporate any number of variations, alterations, substitutions, or equivalent arrangements not heretofore described. For example, while the embodiments are described in connection with a CMOS imaging sensor, they can be practiced with image data from other types of imaging sensors, for example, CCD imagers and others. Additionally, three or five channels, or any number of color channels may be used, rather than four, for example, and they may comprise additional or different colors/channels than greenred, red, blue, and greenblue, such as e.g., cyan, magenta, yellow (CMY); cyan, magenta, yellow, black (CMYK); or red, green, blue, indigo (RGBI).