Method for fabricating recess pattern in semiconductor device

[0001] The present invention claims priority of Korean patent application number 10-2006-0096509, filed on Sep. 29, 2006, which is incorporated by reference in its entirety.

[0002] The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a recess pattern in a semiconductor device.

[0003] Presently, semiconductor devices have become highly integrated. In a method for forming a typical planar gate in which a gate is formed over a planarized active region, a gate channel length is decreased and an ion implantation doping concentration is increased. Thus, a junction leakage current is generated by an increased electric field. As a result, it has become difficult to secure a refresh characteristic of a device.

[0004] To overcome aforementioned limitations, a recess gate process is performed. The recess gate process includes a gate line formation method in which an active region of a substrate is etched into a recess pattern and subsequently, a gate is formed. Using the recess gate process reduces the channel length increase and the ion implantation doping concentration. Thus, the refresh characteristic is improved.

[0005] FIG. 1 illustrates a micrographic view of a typical recess pattern in a semiconductor device. An isolation structure 12 is formed in a substrate 11 to define active regions. The active regions are formed in a direction along a major axis. The active regions include line type recess patterns 14 formed in a direction along a minor axis. A method for forming the recess patterns 14 is described in FIGS. 2A to 2C.

[0006] FIGS. 2A to 2C illustrate cross-sectional views of a typical method for fabricating a recess pattern in a semiconductor device. The same or like reference numerals used for the descriptions in FIG. 1, FIGS. 2A to 2C, and FIG. 3 represent the same or like elements for convenience of description.

[0007] Referring to FIG. 2A, an isolation structure 12 is formed in a substrate 11 to define an active region. A mask pattern 13 is formed over the resultant structure, the mask pattern 13 exposing recess pattern regions. The mask pattern 13 is formed in a line type structure. The mask pattern 13 is formed over the substrate 11 with a uniform spacing distance. The mask pattern 13 is formed over the isolation structure 12 as well as the active region.

[0008] Referring to FIG. 2B, the substrate 11 is etched using the mask pattern 13 as an etch mask to form recess patterns 14. Reference numeral 12A refers to a remaining isolation structure 12A.

[0009] Referring to FIG. 2C, a gate insulation layer 15 is formed over the surface profile of the resultant structure. Gate patterns are then formed in a manner that a portion of the gate patterns is filled in the recess patterns 14 and the rest of the gate patterns protrude above the substrate 11. Each gate pattern includes a stack structure configured with a gate electrode 16 and a gate hard mask 17.

[0010] In the typical method, the recess patterns 14 are formed over both the isolation structure 12 and the active region of the substrate 11. A gate line width has decreased to 70 nm or smaller as the design rule decreases. Thus, patterning for securing a small space of 40 nm or smaller is often required.

[0011] The typical method forms the recess patterns 14 in a small space, and thus, a portion of the substrate 11 adjacent to the isolation structure 12 may be damaged (as shown with reference numeral 100 in FIG. 1). Consequently, a coupling 200 results between the active region and the gate pattern. A cell transistor may not operate due to the coupling 200. FIG. 3 illustrates a micrographic view of the coupling 200 generated during the typical method for forming the recess pattern in the semiconductor device.

[0012] Furthermore, it may be difficult to embody a pattern having a small width, e.g., ranging from 20 nm to 40 nm, due to a lack of resolution of a photoresist pattern. Such a limitation causes a device process to become more difficult to perform and diminishes mass producibility due to the decreased process margin.

[0013] Embodiments of the present invention are directed to provide a method for fabricating a recess pattern in a semiconductor device, which can decrease undesirable events caused by a coupling between an active region and a gate pattern while forming a recess pattern due to a decreased design rule. Also, a decrease in mass producibility caused by a difficult device process and a small process margin can be reduced.

[0014] In accordance with an aspect of the present invention, there is provided a method for fabricating a recess pattern in a semiconductor device, including: forming a photoresist layer over a substrate including active regions; performing a first photo-exposure process on the photoresist layer using a photo mask including repeatedly formed line structures and spaces; performing a second photo-exposure process on the photoresist layer using a photo mask exposing the active regions; performing a developing process on regions of the photoresist layer whereon both the first and second photo-exposure processes are performed; and etching the substrate to form recess patterns using the remaining photoresist layer.

[0021] Embodiments of the present invention relate to a method for fabricating a recess pattern in a semiconductor device.

[0022] FIGS. 4A and 4B illustrate top views of a two-step photo-exposure process of a photoresist layer in accordance with an embodiment of the present invention.

[0023] Referring to FIG. 4A, active regions 41A are defined in a substrate 41 and a photoresist layer (not shown) is formed over the substrate 41. Reference numeral 43 represents first photo-exposure regions 43, and reference numeral 42 represents an isolation structure 42.

[0024] The first photo-exposure regions 43 are formed using a photo mask that is substantially the same type as a typical photo mask in which line structures and spaces are repeatedly formed and using approximately 60% to approximately 80% of an energy generally required to develop a photoresist layer.

[0025] Referring to FIG. 4B, second photo-exposure regions 44 are shown. The second photo-exposure regions 44 are formed using a photo mask that exposes the active regions 41A of the substrate 41 and using approximately 20% to approximately 40% of an energy generally required to develop a photoresist layer.

[0026] Regions sufficed with an optimum energy for photoresist through the aforementioned two-step photo-exposure process, i.e., regions where the first and second photo-exposure regions 43 and 44 overlap, are developed. Thus, patterning on undesired regions is reduced. Consequently, a photoresist pattern for defining recess pattern regions within the active regions 41A of the substrate 41 is formed.

[0027] FIGS. 5A to 5F illustrate cross-sectional views of a recess pattern in a semiconductor device in accordance with an embodiment of the present invention. FIGS. 6A to 6F illustrate top views of a recess pattern in a semiconductor device in accordance with the embodiment of the present invention. The same or like reference numerals throughout the various embodiments of the present invention represent the same or like elements in different drawings for convenience of description.

[0028] Referring to FIGS. 5A and 6A, an isolation structure 52 is formed in a substrate 51. The isolation structure 52 defines active regions 51A. The isolation structure 52 is formed by selectively etching the substrate 51 to form trenches, forming an insulation layer filled in the trenches, and planarizing the insulation layer. The isolation structure 52 is formed to a larger depth than a depth of subsequent recess patterns.

[0029] Referring to FIGS. 5B and 6B, a hard mask layer 53 is formed over the substrate 51. The hard mask layer 53 is formed for use as a hard mask during a subsequent recess pattern etch process. For instance, the hard mask layer 53 includes polysilicon. The hard mask layer 53 is illustrated as being transparent for better understanding of the structure.

[0030] Referring to FIGS. 5C and 6C, a photoresist layer 54 is formed over the hard mask layer 53. The photoresist layer 54 is illustrated as being transparent for better understanding of the structure. A first photo-exposure process is performed on the photoresist layer 54. The first photo-exposure process includes using a line and space type photo mask and using approximately 60% to approximately 80% of an optimum energy (Eop) for photoresist, i.e., an energy generally required to develop a photoresist layer. The line and space type photo mask includes repeatedly formed line structures and spaces. The first photo-exposure process gives an activation energy to the photoresist layer 54. An exposure source for performing the first photo-exposure process may include krypton fluoride (KrF), argon fluoride (ArF), fluorine (F₂), or E-beam.

[0031] Referring to FIGS. 5D and 6D, a second photo-exposure process is performed over the photoresist layer 54 after the first photo-exposure process is performed. The second photo-exposure process includes using a photo mask which exposes the active regions 51A of the substrate 51 and using approximately 20% to approximately 40% of an optimum energy (Eop) for photoresist, i.e., an energy generally required to develop a photoresist layer. An exposure source for performing the second photo-exposure process may include KrF, ArF, F₂, or E-beam.

[0032] Referring to FIGS. 5E and 6E, a developing process is performed on the resultant structure to form a photoresist pattern 54A defining recess regions. The photoresist pattern 54A exposes the recess regions within the active regions 51A of the substrate 51 because regions sufficed with the optimum energy for photoresist during the first and second photo-exposure processes are developed.

[0033] Referring to FIGS. 5F and 6F, the hard mask layer 53 is etched using the photoresist pattern 54A as an etch mask. The substrate 51 is etched to form recess patterns 55 using the etched hard mask layer 53 as an etch mask. The etched hard mask layer 53 and the photoresist pattern 54A are removed.

[0034] Although not illustrated, a Vt screen oxidation process and a well/channel formation process are performed. Gate patterns including gate oxide layer, gate electrodes, and gate hard masks are formed to form a cell transistor of a recess gate.

[0035] The recess patterns 55 are formed within the active regions 51A of the substrate 51 by performing the two-step photo-exposure process, i.e., the first and second photo-exposure processes, on the photoresist layer 54 to form the photoresist pattern 54A defining the recess regions in the active regions 51A of the substrate 51. Thus, damages on the active regions 51A of the substrate 51 adjacent to the isolation structure 52 may be substantially reduced. Thus, undesired couplings between the active regions 51A of the substrate 51 and the subsequent gate patterns may be decreased even after the gate patterns are formed.

[0036] In accordance with the embodiment of the present invention, the photoresist pattern 54A defining the recess regions is formed within the active regions 51A of the substrate 51 by performing the two photo-exposure process on the photoresist layer 54. Also, the recess patterns 55 are formed using the photoresist pattern 54A as a mask. Thus, damages on the active regions 51A of the substrate 51 adjacent to the isolation structure 52 may be substantially reduced.

[0037] In accordance with the embodiment of the present invention, damage on the active regions of the substrate is substantially reduced when forming the recess patterns, and the patterning margin is secured. Thus, device reliability and a process margin are maintained. That is, undesired cell damages may be substantially decreased, the process margin may be increased, and limitations related to an etch process may be solved by forming the photoresist pattern using the two-step photo-exposure process and one developing process, without adding an etch process. Thus, a refresh characteristic of the device may be secured and a product development period may be shortened.

[0038] While the present invention has been described with respect to the specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.