Mismatched filter

[0001] This application incorporates by reference in its entirety: “Multiplicative Mismatched Filters for Optimum Range Sidelobe Suppression in Barker Code Reception,” U.S. application Ser. No. 11/559,776, filed Nov. 14, 2006.

[0002] The present application is generally directed to methods and systems for sidelobe suppression in pulse compression codes.

[0003] Pulse compression codes are designed such that the transmitted energy is uniformly spread in time while the autocorrelation function (ACF) has most of its energy in the mainlobe. Upon matched filtering of such codes, the output is their ACF. The peak sidelobe level (PSL) in the ACF of any good code is required to be as low as possible. Barker codes have the least PSL (of unity magnitude) among all biphase codes. In most applications, it is desirable to reduce the sidelobes further. This is achieved via mismatched filters.

[0004] Mismatched filters for sidelobe suppression can be based on both Infinite Impulse Response (IIR) and Finite Impulse Response (FIR) filters. FIR mismatched filters can either be designed directly or as sidelobe suppression (SLS) filters in cascade with a matched filter. Length-optimal filters for sidelobe suppression produce the best possible sidelobe suppression for a given filter length. Since all their coefficients are optimized, length optimal filters are not hardware efficient.

[0005] The present solution provides methods and systems for realizing hardware efficient mismatched filters for pulse compression codes. For pulse compression codes with sufficiently small sidelobe structures, such as in the cases of odd length Barker codes, the proposed filters require a small number of adders and multipliers per output. This translates to significantly reduced chip-area and lower power consumption when implemented on a chip.

[0006] In one aspect, the present application features a method for suppressing an undesired part of a waveform. The method includes filtering a signal via a filter. In one embodiment, the signal includes an expected waveform that can be represented as a sum of the desired part and the undesired part. The impulse response of the filter can be represented a sum of the desired part and a negative of the undesired part.

[0007] In one embodiment, the signal is an output of a matched filter. In another embodiment, a mainlobe and a plurality of sidelobes at the output of the matched filter forms the desired and the undesired part, respectively. In yet another embodiment, the expected waveform is an autocorrelation function of a pulse compression code. In one embodiment, the desired part of the autocorrelation function is a mainlobe and the undesired part is a plurality of sidelobes.

[0008] In one embodiment, the pulse compression code is a biphase code. In another embodiment, the pulse compression code is a polyphase code. The pulse compression code may include a Barker code, a Huffman sequence or a compound Barker code. Huffman sequences may also be referred to as Huffman codes. Huffman sequences are examples of variable magnitude codes that are characterized by sidelobes of unity magnitude only at two extremes of its autocorrelation function.

[0009] In one embodiment, the method further includes realizing a set of discrete coefficients of the filter from the impulse response. In another embodiment, the filter includes a finite impulse response (FIR) filter. In another embodiment, the filter includes an infinite impulse response (IIR) filter. In still another embodiment, the filter may be a combination of an FIR and an IIR filter.

[0010] In another aspect, the present application features a system for suppressing an undesired part of an expected waveform. The system includes a filter whose impulse response can be represented as a sum of a desired part and a negative of an undesired part of an expected waveform. The expected waveform can be represented as a sum of the desired part and the undesired part.

[0011] In one embodiment, the system further includes a second filter that processes the output of the filter. In one embodiment, the second filter has an impulse response that can be represented as a sum of a second desired part and a negative of a second undesired part of a second expected waveform. In another embodiment, the second expected waveform can be represented as a sum of the second desired part and the second undesired part. In still another embodiment, the second expected waveform is the expected waveform processed by the filter.

[0012] In one embodiment, the filter is connected to an output of a matched filter. In another embodiment, the expected waveform is an autocorrelation function of a pulse compression code. In still another embodiment, the pulse compression code is a biphase code. In yet another embodiment, the pulse compression code is a polyphase code. In some embodiments, the pulse compression code is a Barker code, a Huffman sequence or a compound Barker code.

[0013] In one embodiment, one or more external multipliers are connected across the filter. In some embodiments, the filter includes one or more of a multiplier, a delay unit and an adder. The multiplier, delay unit and adders are hardware units used for fabricating electronic circuits including integrated circuits as apparent to one skilled in the art.

[0014] In still another aspect, the present application features a method of realizing a filter in a device. In one embodiment, the method includes representing a waveform expected at an input of a filter as a sum of a desired part and an undesired part. The method further includes defining an impulse response of the filter as a sum of the desired part and a negative of the undesired part and realizing a filter represented by the impulse response. In some embodiments, the method may include identifying a discrete set of filter coefficients from the impulse response.

[0032] Referring to FIG. 1, a block diagram of an embodiment of a system including a multistage mismatched filter in cascade with a matched filter is shown and described. In brief overview, the system 100 includes a matched filter 105. The system further includes a filter 110 In some embodiments, the filter 110 includes one or more filter stages 115a-115n (in general 115).

[0033] The system 100 may be implemented and operated on any type and form of electronic or computing device 101 (not shown). In one embodiment, the device 101 may be a computing device such as a desktop computer or a laptop computer. In another embodiment, the device 101 may be a microcomputer. In still another embodiment the device 101 may be a microcontroller. In yet another embodiment, the device 101 may be a digital signal processor (DSP) such as manufactured by Texas Instruments of Dallas, Tex. The device 101 and the system 100 may also be implemented on a software platform such as MATLAB or SIMULINK manufactured by MathWorks Inc. of Natick, Mass. In some embodiments, software simulating a microcomputer, microcontroller or a DSP may also be used to implement and execute the device 101. Examples of such software include MPLAB Integrated Development Environment developed by Microchip Technology Inc. of Chandler, Ariz. In one embodiment, the system 100 may be implemented on an integrated circuit. In another embodiment, the integrated circuit may be an application specific integrated circuit (ASIC). In still another embodiment, the system 100 may be implemented on a programmable chip such as a field programmable gate array (FPGA) via programming using any hardware description language (HDL). In some embodiments, the system 100 may be implemented as a combination of software and hardware as apparent to one skilled in the art. In another embodiment, the device 101 is implemented on a charge coupled device (CCD) or charge transfer device (CTD).

[0034] The device 101 may include any type and form of operating system. In some embodiments, the device 101 can be running any operating system such as any of the versions of the Microsoft® Windows operating systems, the different releases of the Unix and Linux operating systems, any version of the Mac OS® for Macintosh computers, any embedded operating system, any real-time operating system, any open source operating system, any proprietary operating system, any operating systems for mobile computing devices, or any other operating system capable of running on the device 101 and performing the operations described herein.

[0035] The device 101 may be a part of any system using a pulse compression code. In some embodiments, the device 101 may be a part of a radar system. In one of these embodiments, pulse compressed waveforms used in radar systems may require preprocessing before being fed to an input of the system 100. In other embodiments, the device 101 may be a part of an imaging system such as ultrasonic imaging, magnetic resonance imaging (MRI), computerized axial tomography (CAT) imaging or any other imaging as apparent to one skilled in the art. In still other embodiments, the device 101 can be a part of geophysical exploration systems, remote sensing systems, well logging electronics, seismological systems or any other systems employing pulse compression codes. In some embodiments, the methods and systems described herein may be used in optics applications such as inverse convolution for removing point-source distortion. In another embodiment, device 101 may be used in systems for correcting known channel distortions. In still another embodiment, the device 101 may be a part of an optical communication system using one or more of a laser source and a fiber optic channel. In yet another embodiment, the device 101 may be a part of a system using sonar waves.

[0036] An incoming signal 102 serves as an input to the system 100. In one embodiment, a signal is a physical quantity that carry information. In another embodiment, any quantity that varies over time and space can be taken as a signal. In still another embodiment, the signal may include electrical impulses or electromagnetic radiation. In some embodiments the signal can be discrete in nature. In some other embodiments, the signal may be continuous. A signal may also be one of an analog signal and a digital signal. In some embodiments, a signal may include a combination of a plurality of signal types. Examples of a signal may include but are not limited to voltage, current, electromagnetic waves, sound and light.

[0037] The incoming signal may include a waveform X(z) related to a pulse compression code. In FIG. 1 the waveform is represented in the z domain as X(z). It should be noted that the waveform can be expressed in any other form in other embodiments without deviating from the scope of the present application. In some embodiments, the pulse compression code is a biphase or binary code. Examples of biphase pulse compression codes include but are not limited to Barker codes, minimum peak sidelobe codes and compound Barker codes. In other embodiments, the pulse compression code can be a polyphase code including but not limited to polyphase or generalized Barker codes, Frank codes and P1-P4 codes generally denoted as Px codes. In some embodiments, the pulse compression code can be a variable magnitude code such as a Huffman sequence or Huffman code. Even though FIG. 1 represents an incoming signal simply as X(z), it should be apparent to one of ordinary skill in the art that in reality, the incoming signal may be corrupted by noise, interference and/or any other form of unwanted signals.

[0038] The incoming signal 102 is passed through a matched filter 105. The matched filter is matched to the pulse compression code being used in the system 100. In FIG. 1, the matched filter is represented in the z-domain purely for notational purposes and should not be considered limiting in any sense. The matched filter may be expressed in any other domain or form without deviating from the scope of the current application. The matched filter detects the presence of the waveform X(z) in the incoming signal 102. In some embodiments, the incoming signal 102 includes the pulse compressed waveform X(z) and the autocorrelation function R(z) is obtained at the matched filter output.

[0039] The matched filter transfer function, matched to the pulse compressed waveform X(z), is X(z⁻¹) and the matched filter output is the autocorrelation function waveform given by:
R(z)=X(z)X(z⁻¹)  (1)
In the absence of any noise or other spurious signals, R(z) includes a mainlobe of height substantially equal to the length of the pulse compression code and a plurality of sidelobes. For notational purposes, we consider the autocorrelation function R(z) to be symmetric around the origin. The sidelobes are collectively denoted as S(z). It should be apparent to one of skill in the art that in practice, the system should be made causal by adding appropriate delays. R(z) is denoted by:
R(z)=N+S(z)  (2)

[0040] It should be appreciated that in the presence of noise or other spurious signals, R(z) will also include components attributable to the noise and other spurious signals. However, in this example, R(z) can be considered to be an expected waveform at the input of the filter. The waveform R(z) can be represented as a sum of a part representing the mainlobe and a part representing the plurality of sidelobes. In some embodiments, the part associated with the mainlobe is a desired part of the response while the part representing the plurality of sidelobes is the undesired part of the waveform. In such embodiments, it is of interest to suppress the undesired part associated with the sidelobes and enhance the desired part, i.e. the mainlobe.

[0041] The system 100 includes a filter 110. The output of the matched filter, which may include the waveform R(z), is connected to the input of the filter 110. The filter 110 includes one or more filter stages 115. The transfer function of the first stage 115a of the filter 110 is given by:
H₁(z)=N−S(z)  (3)

[0042] In some embodiments, the transfer function may also be referred to as an impulse response. In one embodiment, the first stage 115a of the filter 110 is implemented as an FIR filter. In other embodiments, the first stage 115a of the filter 110 may include an IIR filter. Examples of such embodiments will be described in more details with respect to FIGS. 2A and 2B. In some embodiments, the output of the first stage 115a of the filter 110 is connected to the input of the second stage 115b. In other embodiments, the filter 110 comprises only one stage 115a and the output of the first stage is the output Y(z) of the filter 100.

[0043] Although FIG. 1 depicts a plurality of stages 115a-115k of the filter 110, it should be appreciated that the filter 110 may comprise any number of stages. The expected input waveform at the nth stage of the filter 110 will be the expected waveform at the filter input R(z) processed by (n−1) preceding stages 115 where n>2. As shown in greater details below, in some embodiments, the expected waveform at the input of each stage can be represented as a sum of a desired part and an undesired part.

[0044] In the example where R(z) is the expected waveform at the input of the filter 100 and the plurality of sidelobes S(z) are the undesired part, the output of the first stage is given by:

[0045] $\begin{array}{cc}\begin{array}{c}{Y}_1\left(z\right)=\left[N+S\left(z\right)\right]\times \left[N-S\left(z\right)\right]\\ =N^2-{\left[S\left(z\right)\right]}^2\end{array}& \begin{array}{c}\left(4\right)\\ \left(5\right)\end{array}\end{array}$
When the undesired sidelobes are sufficiently small compared to the desired part, the first stage of the filter increases the ratio of the peak magnitude of the desired part and the undesired part. In case of pulse compression codes a metric for measuring the ratio of these peak magnitudes is the mainlobe to peak sidelobe ratio (MSR).

[0046] Referring now to FIG. 2A, a block diagram depicting an example embodiment of the first stage 115a of the filter 110 is shown and described. In one embodiment, the first stage 115a includes a multiplier 210 representing the mainlobe of the expected waveform R(z). In some embodiments, the first stage 115a further includes a filter 220 whose impulse response represents the undesired plurality of sidelobes of the expected waveform R(z). Since the overall impulse response of the first stage 115a represents a sum of the desired part and the undesired part, in some embodiments the first stage 115a includes an adder 215 to compute the sum of the mainlobe and a negative of the plurality of sidelobes. In other embodiments, the first stage 115a includes one or more delay units 205. In one embodiment, the one or more delay units 205 are used to ensure causality. In another embodiment, the number of delay units depends on the position of the mainlobe with respect to the plurality of sidelobes.

[0047] If further sidelobe suppression is desired, output of the first stage 115a is connected to an input of the second stage 115b. In some embodiments, the output of the first stage Y₁(z) can be represented as a sum of a desired part and an undesired part. From the example in equation (5), the desired part can be identified to be N² while the undesired part is {−S(z)²}. The transfer function of the second stage 115b of the filter 110 for this example is therefore given by:
H₂(z)=N²+[S(z)]²  (6)

[0048] Referring now to FIG. 2B, an example embodiment of the second stage 115b of the filter 110 is depicted. In one embodiment, the second stage includes a multiplier 310 representing a magnitude of the desired part of the input waveform (N² in this case). In some embodiments, the second stage 115b includes one or more filters 220 such that the overall impulse response of the one or more filters represents the undesired part of the input. The second stage 115b may also include one or more delay units 305 and an one or more adder 315.

[0049] In one embodiment, the output of the second stage 115b is taken as the output Y(z) of the filter 110. In other embodiments, the output Y₂(z) of the second stage 115b is connected to an input of a third stage 115c. An example embodiment of the third stage 115c is depicted in FIG. 2C. The desired part of the input waveform for the third stage 115c is N⁴ while the undesired part is {−S(z)⁴}. In some embodiments, more number of stages 115 of the filter 110 can be implemented to achieve a predetermined level of suppression of the undesired part of the waveform. If k stages are used, the transfer function of the kth stage is given by:
H_k(z)=N^2k−1+[S(z)]^2k−1  (7)
for k=2, 3, . . . . The output of the kth stage is given by:
Y_k(z)=N^2k=[S(z)]^2k  (8)

[0050] In some embodiments, the expected waveform needs to satisfy certain conditions in order for the filter 110 to function satisfactorily. It should be understood that the favorable conditions described herein are not limiting in any sense and does not exclude other favorable conditions that may be derived under different assumptions. In some embodiments, the filter 110 may function even when the favorable conditions are not met exactly. In other embodiments, one stage of the filter 110 may not meet these favorable conditions while one or more other stages meet them.

Favorable Conditions

[0051] Consider the output of the first stage 115a of the filter 110 given by equation (5). In the time domain, the output is given by:
y₁(n)=N²δ(n)−[s(n)*s(n)]  (9)
where s(n) denotes the sidelobes of the autocorrelation function in the time domain.

[0052] In some embodiments, in order for the first stage 115a of a filter to work satisfactorily, the mainlobe to peak sidelobe ratio (MSR) at the output should be higher than the MSR of the input waveform. Let the peak sidelobe magnitude of the autocorrelation function be denoted by ŝ. Therefore, a condition for the filter 110 to work is given by:

[0053] $\begin{array}{cc}\frac{N^2-\sum {s\left(n\right)}^2}{{\max }_{\left(n>0\right)}s\left(n\right)*s\left(n\right)}>\frac{N}{\hat{s}}& \left(10\right)\end{array}$
For subsequent stages of the filter, the MSR at the output should be higher than the MSR at the input for that stage.

[0054] For Barker codes, since the peak sidelobe magnitude is unity, the condition for the first stage becomes:

[0055] $\begin{array}{cc}\frac{N^2-\sum {s\left(n\right)}^2}{{\max }_{\left(n>0\right)}s\left(n\right)*s\left(n\right)}>\frac{N}{1}& \left(11\right)\end{array}$
The condition is satisfied for Barker codes of length 3, 4, 5, 7, 11 and 13 as shown in table 1.

[0056] Therefore, for Barker codes, the MSR is improved at the output of the first stage 115a of the filter 110. Filters for Barker codes are discussed next with examples of filters for the important cases of length 13 and 11.

[0057]

TABLE 1
MSR at the output of first stage for Barker codes
Length of
Barker Code (N)	Σ|s(n)|2	max(n>0)|s(n) * s(n)|	MSR at output
3	2	1	7
4	4	2	6
5	4	2	10.5
7	6	4	10.75
11	10	8	13.875
13	12	10	15.7

[0058] Filters for Barker Codes

[0059] An example implementation of the filter 100 is shown below using the example of a Barker code of length 13. The use of the Barker code of length 13 is used purely for illustrative purposes and should not be considered limiting in any sense. The autocorrelation function of a Barker code of length 13 is given by:
R₁₃(z)=13+(z¹²+z¹⁰+ . . . +z²+z⁻²+ . . . +z⁻¹⁰+z⁻¹²)  (12)

[0060] In one embodiment, the first stage 115a of the filter 100 for the Barker code of length 13 is implemented as:
H₁(z)=13−(z¹²+z¹⁰+ . . . +z²+z⁻²+ . . . +z⁻¹⁰+z⁻¹²)  (13)

[0061] In another embodiment, the first stage 115a may also be represented as follows:

[0062] $\begin{array}{c}{H}_1\left(z\right)=13-\{(z^{12}+z^{10}+\dots +z^2+1+z^{-2}+\dots +z^{-10}+\left(14\right)\\ z^{-12})-1\}\\ =14-z^{12}\left(1+z^{-2}+z^{-4}+\dots +z^{-12}+z^{-14}+\dots +z^{-24}\right)\left(15\right)\\ =14-\frac{z^{12}\left(1-z^{-26}\right)}{\left(1-z^{-2}\right)}\left(16\right)\end{array}$

[0063] In one embodiment, the first stage 115a for a Barker code of length 13 is implemented as represented in equation (14). A block diagram of such an embodiment is shown in FIG. 3A. In one embodiment, the filter 220 in this example may be implemented as a recursive running sum filter or any other form of IIR filter as shown in FIG. 3A. In another embodiment, the filter 220 may include one or more delay element 205. In still another embodiment, the filter 220 may include one or more adder 215. The filter structure of FIG. 3A depicts an example embodiment. In practice, the first stage 115a for a filter 100 for a Barker code may be implemented in any other form or structure as apparent to one skilled in the art.

[0064] In some embodiments, a filter structure of the first stage 115a may be modified as a design choice. For example, the one or more delay units 205 inside and outside the filter 220 may be shared to make the filter structure more hardware efficient. In one embodiment, such modification may affect a value of the multiplier 210. FIG. 3B depicts a block diagram of such an embodiment. The design modifications depicted in FIG. 3B are expressed in equations (15) and (16). It should be noted that such design modifications can result in using less hardware. For example, the design modifications, as depicted in FIG. 3B, result in a decreased number of adders 215 and/or delay units 205. It can be seen from FIG. 3B that 3 adders and 1 multiplier are required to implement this embodiment of the first stage 115a. In other embodiments, the value of the multiplier (14 in this case), can be represented in terms of powers of 2 as (2⁴−2). Thus, the multiplier can be replaced by one equivalent adder and two shifts. This means that the first stage 115a may be implemented without any multipliers and using only 4 adders. In applications where multipliers are significantly more expensive to implement than adders, this alternative offers further reduction in implementation cost.

[0065] Referring now to FIG. 3C, a second stage 115b of the filter 100 is shown. The second stage 115b of the filter 100 can be implemented as:

[0066] $\begin{array}{cc}{H}_2\left(z\right)=N^2+{\left[S\left(z\right)\right]}^2& \left(17\right)\\ ={13}^2+\left[\frac{z^{12}\left(1-z^{-26}\right)}{\left(1-z^{-2}\right)}-1\right]\left[\frac{z^{12}\left(1-z^{-26}\right)}{\left(1-z^{-2}\right)}-1\right]& \left(18\right)\end{array}$

[0067] It should be noted that the (−1) term associated with the series of sidelobes in equation (14) is adjusted as a part of the mainlobe in equation (15). In some embodiments, this is avoided second stage onwards, in order to preserve the computational advantage of the filter. In some embodiments, the second stage 115b of the filter 100 for a length 13 Barker code is implemented as given by equation (18) and shown in FIG. 3C. For higher levels of sidelobe suppression, additional stages in the mismatched filters may be implemented following equation (7). As an example, the third stage 115c of the filter 110 for the length 13 Barker code is given by:

[0068] $\begin{array}{cc}{H}_3\left(z\right)=N^4+{\left[S\left(z\right)\right]}^4& \left(19\right)\\ ={13}^4+{\left[\frac{z^{12}\left(1-z^{-26}\right)}{\left(1-z^{-2}\right)}-1\right]}^4& \left(20\right)\end{array}$
The corresponding filter structure is shown in FIG. 3D.

[0069] In some embodiments, the multipliers used in one or more of the stages 115 can be represented by equivalent adders to reduce the computational complexity and hardware requirements. Table 2 shows examples how the multipliers in the different stages of the filters 110 for Barker codes of length 13 and 11 may be replaced by a small number of adders.

[0070]

TABLE 2
Schemes to replace multipliers in different stages with equivalent adders
	Multiplier	Equivalent representation	No. of adders
Filter for b13
Stage 1	14	24 − 2	1
Stage 2	132	27 + 25 + 23 + 20	3
Stage 3	134	215 − 212 − 27 + 24 + 20	4
Filter for b11
Stage 1	10	23 + 2	1
Stage 2	112	27 − 23 + 20	2
Stage 3	114	(27 − 23 + 20)(27 − 23 + 20)	4

[0071] In one embodiment, the filter 110 and any adder, multiplier, delay unit or other hardware included as a part thereof may be implemented via fixed point implementation (viz. 2's complement). In other embodiments, floating point implementation may be used. In some embodiments, random errors due to ionization, interference etc. may affect the system performance. If such factors are expected and/or floating point implementation is used, then the filter may be implemented as one or more FIR filters and/or by using the concept of switching and resetting as presented in: T. Saramaki and A. T. Fam, “Properties and structures of linear-phase FIR filters based on switching and resetting of IIR filters,” IEEE International Symposium on Circuits and Systems, Vol. 4, pp. 3271-3274, May 1990.

[0072] In some embodiments, performance of the filter 110 may be improved using additional hardware. In one embodiment, one or more multipliers may be connected across one or more stages 115 of the filter 110. In another embodiment, values for the one or more multipliers may be optimized for any cost function. In still another embodiment, the values of the one or more multipliers may be optimized for a best MSR performance for a given filter structure. An example embodiment 100a of such a filter structure is depicted in FIG. 4A. In one embodiment, an external multiplier m₁ 120a is connected across the first stage 115a. In some embodiments, the filter 110 performs well when the sidelobes of the preceding stage output is lower than a certain degree. Therefore, in these embodiments, a logical method to improve the performance of the filter is to produce considerably low sidelobes at the output of the first stage 115a. After that the performance of the filter 110 improves significantly for the subsequent stages. Therefore, connecting an external multiplier 120a across the first stage 115a to have an improved MSR at the input of the second stage thus is advantageous for the performance of the subsequent stages 115b. It should be appreciated that one or more multipliers and/or other hardware that improves the filter performance may be used across any stage 115. However, addition of multipliers and/or other hardware in any stage increases the computational burden on the subsequent stages. The effects that a multiplier across the first stage 115a has on the filter structures of subsequent stages are discussed next with respect to FIGS. 4B-4D. It should be apparent to one of ordinary skill in the art that introduction of multipliers and/or other hardware across other stages 115 would further complicate the filter structures and should be done judiciously. In some embodiments, an external multiplier 120b may be connected across the last stage 115n to improve the performance of the filter 110. Obviously, the multiplier 120b across the last stage 115n adds insignificant computational and hardware burden.

[0073] Referring now to FIG. 4B, an example embodiment of the first stage 115a with an external multiplier 120a connected across it shown. In one embodiment, the external multiplier 120a may be connected to one or more delay elements and/or other hardware elements. In the example when the expected waveform at the input to the first stage is denoted by R(z)=N+S(z), the output of the first stage 115a is given by:

[0074] $\begin{array}{c}{Y}_1\left(z\right)=N^2-S^2\left(z\right)+m_1\left[N+S\left(z\right)\right]\\ =\left(N^2+m_{1}N\right)+S\left(z\right)\left[m_1-S\left(z\right)\right]\end{array}\hspace{1em}$

[0075] Therefore the second stage 115b of the filter 110 in this example is given by:
H₂(z)=(N²+m₁N)−S(z)[m₁−S(z)]
An example embodiment of the modification in the structure of the second stage 115b is shown in FIG. 4C. The output of the second stage 115b will therefore be given by:
Y₂(z)=(N²+m₁N)²−S²(z)[m₁−S(z)]²

[0076] Following a substantially similar method as described with respect to FIGS. 3A-3D, one embodiment of the third stage of the sidelobe inversion filter is given by:
H₃(z)=(N²+m₁N)²+S²(z)[m₁−S(z)]²
FIG. 4D depicts an embodiment of the filter structure of the third stage 115c. In some embodiments, more stages 115 of the filter 110 may be implemented in cascade.
Filter Performance

[0077] Performance of the filter 110 is discussed herein for a Barker code of length 13. Hardware requirements both with and without the external multipliers 120 across one or more stages are shown. It should be noted that these calculations are intended to be purely indicative of the performance and hardware efficiency of an example embodiment of the filter 110 and should not be construed to be limiting in any sense. These calculations may include several assumptions and simplifications.

[0078] In one embodiment, the filter 110 requires one multiplier per stage for its implementation. In another embodiment, the number of adders that may be used is a function of the stage 115 for which it is being calculated. In still another embodiment, the number of adders required for the rth stage is given by:
A_r=2^r−1×3+1

[0079] In one embodiment, one adder in the first stage 115a can be incorporated into the multiplier 210. In this embodiment, the total number of adders for k stages is given by:

[0080] $\begin{array}{c}A\left(k\right)=\sum _{r=1}^k\left(2^{r-1}\times 3+1\right)-1\\ =\left(k-1\right)+3\left(\sum _{r=0}^{k-1}{2}^r\right)\\ =\left(k-1\right)+3\times \left(2^k-1\right)\\ =3\times 2^k-4+k\end{array}\hspace{1em}$

[0081] The performance of the filter 110 for the Barker code of length 13, with different number of stages is given in table 3. The filter 110 with no external multiplier 120 connected across any stage is denoted as a simple cascaded filter structure.

[0082]

TABLE 3
Performance of the simple cascaded filter structure with
different number of stages for Barker 13
		stage	stage	stage	stage	stage
	MF	1	2	3	4	5
MSR in dB	22.28	23.92	29.67	35.99	45.74	62.04
Mul. used in this stage	0	1	1	1	1	1
Total mul. used upto this	0	1	2	3	4	5
stage
Add used in this stage	12	3	7	18	35	40
Total add used upto this	12	15	22	35	60	100
stage
Suppression per mul.	—	23.02	14.84	11.99	11.48	12.41
(dB)
Suppression per add	1.80	1.59	1.35	1.03	0.76	0.57
(dB)

[0083] The performance of the filter 110 for the Barker code of length 13, with external multipliers 120 connected across the first stage 115a and the last stage 115n is tabulated in table 4. The filter 110 with the external multipliers is denoted as a modified filter. It can be seen that the introduction of the increased number of multipliers significantly improves the performance of the filters. The advantage is evident from the fact that both the suppression per multiplier and the suppression per adder are found to improve in the case of the modified filter.

Comparison with Optimal Filters

[0084] Optimal or length-optimal filters for sidelobe suppression are defined to be filters of a given length that achieve the best sidelobe suppression in either a peak sidelobe level (PSL) sense or an integrated sidelobe level (ISL) sense.

[0085] Performance of the filter 110 is compared to that of the optimal peak sidelobe (PSL) and optimal integrated sidelobe (ISL) filters. For fixed point arithmetic, the multipliers and adders are considered separately while for floating point implementation, a total number of arithmetic operations as the sum of the number of adders and multipliers is considered. The sidelobe suppression i) per adder, ii) per multiplier (fixed point arithmetic) and iii) per arithmetic operation (floating point arithmetic), are calculated in each case. Table 5 compares the performance of the filters 110 with length-optimal filters reported in the literature that achieve the nearest MSR.

[0086]

TABLE 4
Performance of the modified filter with different
number of stages for Barker 13
		stage	stage	stage	stage	stage
	MF	1	2	3	4	5
MSR in dB	22.28	33.98	54.03	103.19	107.84	321.85
Mul. used in this stage	0	2	2	3	5	10
Total mul. used upto	0	2	5	8	19	28
this stage
Add used in this stage	12	4	8	16	30	59
Total add used upto	12	10	25	40	71	139
this stage
Suppression per mul.	—	10.00	10.81	12.80	12.91	13.09
(dB)
Suppression per add	1.80	2.12	2.10	0.57	2.30	3.48
(dB)

[0087]

TABLE 5
Comparison with optimal filters for length 13 Barker code
		Mult.	Add	Arithmetic	sidelobe suppression per	sidelobe suppression per	sidelobe suppression per
	MSR	per	per	operation	multiplier (dB)	adder (dB)	arithmetic op. (dB)
Filter	(dB)	output	output	per output	(fixed point)	(fixed point)	(floating point)
min PSL	32.50	25	24	49	1.3	1.35	0.66
proposed filter	33.96	2	16	18	16.99	2.12	1.89
(modified and with 1 stage)
min ISL	58.85	65	64	129	0.9	0.91	0.45
proposed filter	54.03	5	25	30	10.31	2.16	1.80
(modified and with 2 stages)
min PSL	72.87	85	84	169	0.85	0.86	0.43
proposed filter	103.19	8	40	48	12.89	2.57	2.15
(modified and with 3 stages)

[0088] From table 5, it can be seen that the length-optimal filters are superior to the filters 110 in terms of suppression per unit filter length but the filters 110 outperform the length-optimal filters in terms of suppression per arithmetic operation as well as per unit chip area in terms of VLSI implementation. In some embodiments, the computational efficiency of the filters 110 is achieved at the expense of a longer filter length as compared to the optimal filters.

[0089] Table 6 presents the savings in area achieved by the filters 110 compared to length optimal filters, when implemented in VLSI. In this comparison, it has been assumed that the number of bits for the length-optimal filter coefficients is chosen to satisfy a required precision. The bit-widths of the coefficients of length-optimal filters comparable to the 1 stage, 2 stage and 3 stage versions of the filters 110 have been chosen to be 16, 32 and 47 bits, respectively. In order to facilitate a precise comparison, the area of each filter per dB of suppression achieved has been normalized before calculating the savings. It is also assumed that the ratio of the areas of the proposed and length-optimal filters is not very sensitive to the bit-width of the input data. As observed from table 6, the filters 110 in the example considered achieve significant savings in implementation area compared to the length optimal filters. Furthermore, assuming the average power consumption to be proportional to area×activity, the savings in power consumption, as shown in table 7, approximately follow the area savings. It is pointed out that gate-level power analysis was used to determine the power consumption of the filter 110 and the length-optimal filters.

[0090]

TABLE 6
Area savings compared to equivalent length optimal filters for Barker 13
No. of stages	Ratio of area	Area
of proposed filter	(normalized per dB)	savings
1	0.1195	88.04%
2	0.0629	93.71%
3	0.0422	95.77%

[0091]

TABLE 7
Power savings compared to equivalent length
optimal filters for Barker 13
No. of stages	Ratio of power consumption	Power
of proposed filter	(normalized per dB)	savings
1	0.1092	89.08%
2	0.0572	94.28%
3	0.0389	96.11%

Extension to Compound Codes

[0092] If a code C_N1 of length N₁ is compounded with another code C_N2 of length N₂, the z-domain representation for such compounding is given by:
C_N1,N2(z)=C_N2(z)×C_N1(z^N2)

[0093] where C_N1 is the outer code and C_N2 is the inner code.

[0094] The filter 110 for the compound code can be implemented as a cascade of two filters M_N2(z) and M_N1(z^N2) such that:
M_N1,N2(z)=M_N2(z)×M_N1(z^N2)

[0095] In some embodiments, one or more of the individual mismatched filters M_N2(z) and M_N1(z^N2) may be implemented as filters 110 as described herein. Therefore, the filter 110 for the compound code may be implemented as a cascade of the filters 110 of the component codes. In some embodiments, if additional multipliers are used to optimize the performance of the individual filters, the cascaded implementation may not be optimal for the compound code. However, it can be appreciated that such a cascaded implementation would allow a straightforward extension to a filter for the compound code that would inherit the computational efficiency of the individual filters.

Extension to Polyphase Codes

[0096] In some embodiments, the methods and systems herein may be used for polyphase pulse compression codes. Examples of polyphase pulse compression codes include but are not limited to Generalized Barker codes, Frank codes, P1, P2, P3, P4 codes and Chu codes. As an example, filters 110 for Frank codes are described.

[0097] Aperiodic Frank codes have good main to peak sidelobe ratio (MSR). They are generated by concatenating of the rows of the Discrete Fourier Transform (DFT) matrix of size N×N. In the following example w=exp(j2πp/N) and N and p are relatively prime. This aperiodic code, which is just one period of a periodic code, is of length N². In some embodiments, the period starts by concatenating the complete set of rows in their natural order as in

[0098] $\hspace{1em}\left[\begin{array}{ccccc}1& 1& 1& \dots & 1\\ 1& w& w^2& \dots & w^{N-1}\\ 1& w^2& w^4& \dots & w^{2\left(N-1\right)}\\ ⋮& ⋮& ⋮& \ddots & ⋮\\ 1& w^{N-1}& w^{2\left(N-1\right)}& \dots & w^{{\left(N-1\right)}^2}\end{array}\right]\hspace{1em}$
since this seems to produce the best MSR. The Z transform of this code could be represented by the efficient form given by:

[0099] $X\left(z\right)=\left(1-z^{-N}\right)\sum _{r=0}^{N-1}\frac{z^{-\mathrm{rN}}}{1-w^r{z}^{-1}}$
The foregoing representation does not require N and p to be relatively prime.

[0100] The matched filter for periodic and aperiodic Frank codes may be implemented using the following equation which is combined with appropriate delay elements to render it causal:

[0101] $X^{*}\left(z^{-1}\right)z^{-\left(N^2-1\right)}=\left(z^{-N}-1\right)\sum _{r=0}^{N-1}\frac{z^{-\left(N^2-\left(r+1\right)N\right)}}{z^{-1}-w^{-r}}$

[0102] In one embodiment, N is the size of the DFT matrix. This efficient structure is in IIR form, and its marginally stable poles are canceled by some of its zeros. In some embodiments, due to finite word length effect the cancellation might be inexact. In such a case, two copies of each block should be used with a switching and resetting technique to in effect stabilize pole-zero cancellation.

[0103] In one embodiment, if a Frank code is used to produce a pulse compressed waveform, the expected waveform at the input of the filter 110 is given by:
R(z)=X(z)X*(z⁻¹)
X*(z⁻¹) is the matched filter that depends on the polyphase code. In one embodiment, the operation * denotes complex conjugation. In some embodiments, the system is made causal by adding the appropriate delays. In one embodiment, the autocorrelation function can be expressed as:
R(z)=M+S(z)

[0104] In some embodiments, M=N² is the length of the code and S(z) represents the sidelobes which are either symmetric in real values or have conjugate symmetry in polyphase codes. In one embodiment, M=N² represents the desired part of the expected waveform while S(z) denotes the undesired part. In some embodiments, S(z) may be represented as:
S(z)=R(z)−M
The transfer function of the first stage 115a of the filter 110 is therefore given by:
H₁(z)=M−S(z)=2M−R(z)
In one embodiment, the output of the first stage 115a may be represented as:
Y₁(z)=R(z)·H₁(z)=M²−[S(z)]²
Following the methods and systems described herein, the second stage 115b of the filter 110 may be represented as:
H₂(z)=M²+[S(z)]²=M²+[R(z)−M]²
In this example, the MSR is improved at the output of the second stage 115b. In some embodiments, a multiplier is added across one or more stages 115 to further increase the MSR.

[0105] Referring now to FIG. 5A, a first stage 115a of the filter 110 for an aperiodic Frank code is shown and described. The first stage is given as:
H₁(z)=2M−R(z)
Where R(z), optionally with appropriate delays, is given by:

[0106] $\begin{array}{c}{R}_d\left(z\right)=R\left(z\right)·z^{-\left(N^2-1\right)}\\ ={\left(1-z^{-N}\right)}^2\sum _{r=0}^{N-1}\frac{z^{-\left(N^2-N\right)}}{{w^r\left(z^{-1}-w^{-r}\right)}^2}\end{array}\hspace{1em}$

[0107] Referring now to FIG. 5B, an example embodiment of the first stage 115a with an external multiplier μ₁ is shown. In one embodiment, the output of such a modification of the first stage 115a produces the output:

[0108] $\begin{array}{c}{Y}_1\left(z\right)=\left[R\left(z\right)·H_1\left(z\right)\right]+{\mu }_1·R\left(z\right)\\ =\left[M^2-{\left[S\left(z\right)\right]}^2\right]+{\mu }_1\left[M+S\left(z\right)\right]\\ =\left[M^2+{\mu }_{1}M\right]-\left[{\left[S\left(z\right)\right]}^2-{\mu }_{1}S\left(z\right)\right]\end{array}\hspace{1em}$

[0109] The optimal value of μ₁ is evaluated via computer search. Table 8 shows the optimal value of μ1 to get the maximum MSR at the output of the first stage 115a for codes up to length N²=32². The MSR gain is also evaluated.

[0110]

TABLE 8
N	MSR R(z) (dB)	MSR Y1(z) (dB)	MSR gain (dB)	μ1
3	19.0849	21.6534	2.5686	2.8
4	21.0721	25.9178	4.8457	7
5	23.7790	27.3273	3.5483	32.4
6	25.1055	29.5782	4.4727	31.7
7	26.7720	30.6548	3.8828	46.4
8	27.7804	32.2027	4.4223	57
9	28.9837	33.0885	4.1048	76.8
10	29.7996	34.1818	4.3822	90.1
11	30.7413	34.9058	4.1645	113.2
12	31.4272	35.8073	4.3801	132.8
13	32.2007	36.4136	4.2129	159.3
14	32.7925	37.1308	4.3383	181.3
15	33.4489	37.6816	4.2327	213.1
16	33.9695	38.3190	4.3495	241.5
17	34.5396	38.7777	4.2381	274.9
18	35.0043	39.3142	4.3099	305.6
19	35.5082	39.7588	4.2506	346.2
20	35.9279	40.2408	4.3130	381.9
21	36.3793	40.6212	4.2420	423.8
22	36.7619	41.0519	4.2900	463.3
23	37.1708	41.4245	4.2537	512.6
24	37.5224	41.8084	4.2860	555.3
25	37.8961	42.1355	4.2395	606
26	38.2213	42.4959	4.2746	654.4
27	38.5654	42.8128	4.2474	711.8
28	38.8679	43.1350	4.2671	762.2
29	39.1867	43.4219	4.2352	821.8
30	39.4695	43.7320	4.2625	879
31	39.7665	44.0037	4.2372	943.4
32	40.0320	44.2851	4.2530	1002.7

[0111] In one embodiment, further sidelobe suppression can be achieved by using a second filter stages 115b. In one embodiment, the modification of the first stage 115a filter by adding the multiplier μ₁, results in the following modified structure for the second stage 115b:

[0112] $\begin{array}{c}{H}_2\left(z\right)=\left[M^2+{\mu }_{1}M\right]+\left[{S\left(z\right)}^2-{\mu }_{1}S\left(z\right)\right]\\ =\left[M^2+{\mu }_{1}M\right]+\left[{\left(R\left(z\right)-M\right)}^2-{\mu }_1\left(R\left(z\right)-M\right)\right]\end{array}\hspace{1em}$

[0113] FIG. 5C depicts an example embodiment of the second stage 115b of the filter 110 for the aperiodic Frank code being discussed herein. In one embodiment, μ₁ is optimized to get the best MSR at the output of the first stage. In another embodiment, the multiplier μ₁ is reoptimized to optimize the MSR at the output of the second stage. In still another embodiment, a second multiplier μ₂ is added across the second stage 115b. In yet another embodiment, one or more of μ₁ and μ₂ are optimized for a best MSR at the output of the second stage 115b. FIG. 5D depicts an example embodiment of the second stage 115b with the multiplier μ₂ across it.

[0114] The methods and systems described herein have been described for waveforms and filters related to signals in one dimension. It should be understood that the concepts presented herein may be extended to two or more dimensions without deviating from the scope of the current application.

[0115] In view of the structure and functions of the systems and methods described herein, the present solution provides a simple and computationally efficient mismatched filter for suppressing undesired parts in a waveform. Having described certain embodiments of methods and systems for such a filter, it will now become apparent to one of skill in the art that other embodiments incorporating the concepts of the invention may be used. Therefore, the invention should not be limited to certain embodiments, but rather should be limited only by the spirit and scope of the following claims: