Integrated III-nitride devices

[0001] This application is based on and claims priority to the of U.S. Provisional Application Ser. No. 60/757,371, filed on Jan. 9, 2006, entitled Integrated FETs in Common Drain Configuration Using Metal Via For Connection to Substrate, to which a claim of priority is hereby made and the disclosure of which is incorporated by reference.

[0002] III-nitride as used herein refers to a semiconductor alloy from the InAlGaN system that includes at least Nitrogen and another alloying element from group III. Examples of a III-nitride alloy are AlN, GaN, AlGaN, InGaN, InAlGaN, or any combination that includes nitrogen or at least one element from group III.

[0003] The present invention relates to semiconductor devices and more particularly to III-nitride heterojunction semiconductor devices.

[0004] Conventional III-nitride power heterojunction semiconductor devices include at least two power electrodes and a gate arrangement disposed therebetween all disposed on one surface of a semiconductor die. Consequently, conventional III-nitride heterojunction semiconductor devices are typically lateral conduction devices.

[0005] In many applications, including power applications, two or more devices need to be integrated. Integration of lateral conduction devices results in relatively complex routing and the like which results, among other drawbacks, parasitic drain to source capacitance.

[0006] In accordance with the invention, the substrate of a III-nitride heterojunction semiconductor device is used as a third access path to a set of active contacts, rather than simply shorting the substrate to a source or drain, or just floating.

[0007] More specifically, in a device according to the present invention a third power electrode residing on a top surface of the device is connected vertically down to the substrate using a metal plug or via. The third power electrode may be disposed between the two other power electrodes.

[0008] The third electrode may be a drain electrode while the other two electrodes may be the first source electrode and the second source electrode. Thus, the electrodes may be arranged in the sequence source 1, drain, source 2, or, in the case of a half bridge arrangement, source 1, source 2, drain, source 2, source 2, source 1, source 2, drain, and so on.

[0009] In a device according to the present invention, the basic idea is to use the vertical direction through the device to facilitate the integration of multiple switches, which results in the following:

• • [0010] ease of metal routing;
  • [0011] reduction of high voltage metal cross-overs;
  • [0012] reduction of drain to source capacitance from those cross-overs; and
  • [0013] device symmetry with respect to substrate in a common drain configuration.

[0014] Other features and advantages of the present invention will become apparent from the following description of the invention which refers to the accompanying drawings.

[0022] Referring to FIG. 1, a III-nitride device according to the present invention may include a first gate contact 10, a second gate contact 12, a first power contact 14 (e.g. first source contact), and a second power contact 16 (e.g. second source contact). First power contact 14 is connected to a plurality of first power runners 18, while second power contact 16 is connected to a plurality of second power runners 20 spaced from said first power runners. Preferably, first and second power runners are parallel and alternately arranged in an interdigitated manner.

[0023] Referring next to FIG. 2, in each active cell of a device according to the present invention, each first power runner 18 is electrically connected to a plurality of first power electrodes 22 (e.g. first source electrodes), while second runner 20 is connected to a plurality of second power electrodes 24 (e.g. second source electrodes) spaced from said first power electrodes 22. Preferably, first and second power electrodes 22, 24 are parallel one another and are arranged in an interdigitated manner. In each active cell, a third power electrode 26 (e.g. drain electrode) is disposed between a respective first power electrode 22 and a second power electrode 24, and a first gate arrangement 28 is disposed between a first power electrode 22 and a third power electrode 26, while a second gate arrangement 30 is disposed between a second power electrode 24 and a third power electrode 26.

[0024] Referring now to FIG. 3, a III-nitride device according to the present invention includes an electrically conductive substrate 32, which may be highly conductive silicon, or SiC, a III-nitride transition layer 34 over substrate 32, which may be graded or uniform AN, a III-nitride buffer layer 36 over transition layer 34, which may be composed of GaN, and III-nitride active heterojunction 38. III-nitride active heterojunction 38 may include a III-nitride channel layer, e.g. GaN, disposed preferably on III-nitride buffer layer 36, and a III-nitride confinement layer, e.g. AlGaN, disposed on and making a heterojunction with the channel layer. The thickness and composition of the channel layer and the confinement layer are selected to generate a two-dimensional electron gas (2-DEG) in the channel layer close to the heterojunction of the two layers. As is well known the 2-DEG is an electron rich region that carries the current. To transmit the current, first power electrode 22 and second power electrode 24 are coupled to heterojunction 38 preferably through a direct ohmic contact to the confinement layer of heterojunction 38, which preferably is under each power electrode.

[0025] According to one aspect of the present invention, a trench 40 extends through the stack of heterojunction 38, III-nitride buffer layer 36, and transition layer 34 and reaches substrate 32. A metallic plug 42 fills trench 40 and is electrically connected to third power electrode 26, whereby a direct electrical connection is made between third power electrode 26 and substrate 32. Note that optionally a dielectric body 44 may line the sidewalls of trench 40 and insulate plug 42 from the trench sidewalls.

[0026] In the first embodiment of the present invention (FIG. 3), first gate arrangement 28 and second gate arrangement 30 are bodies that make Schottky contact with III-nitride heterojunction 38.

[0027] FIG. 4 illustrates a circuit diagram of a device according to the present invention.

[0028] Referring to FIG. 5, in which like numerals identify like features, in a device according to the second embodiment each gate arrangement 28, 30 includes a gate electrode 28′, 30′ disposed on a respective gate dielectric body 28″, 30″, which is itself disposed on heterojunction 38. Gate dielectric body 28″, 30″ may be any suitable insulation such as SiO₂, or Si₃N₄.

[0029] Referring to FIG. 6, in which like numerals identify like features, in a device according to the third embodiment, regions 46 under each gate arrangement 28, 30 are implanted with appropriate doping species (e.g. P-type) to interrupt the 2DEG in heterojunction 38, whereby the device may be rendered normally off. That is, an enhancement mode device can be obtained.

[0030] Referring next to FIG. 7, in which like numerals identify like features, in a device according to the third embodiment, each gate arrangement 28, 30 is received partially inside a recess 45 in III-nitride buffer 36. Note that heterojunction 38 is also disposed at least partially inside recess 45, and third power electrode 26 is disposed over heterojunction 38 that resides over the bottom of recess 45. A portion of each gate arrangement 28, 30 is disposed on heterojunction 38 that is laterally outside of recess 45. A recess 45 in the third embodiment interrupts the 2-DEG in heterojunction 38, thereby rendering the 2-DEG normally off. As a result an enhancement mode device can be obtained.

[0031] The concept disclosed herein is applicable to devices which will operate in the enhancement mode, such as planar devices with oxidation of the AlGaN layer under the gate; recess etching under the gate; and ion implantation/doping under the gate. The concept disclosed herein also applies to non-planar gate devices with regrowth of the barrier layer, to devices employing the use of N-Polar material, as is described in my copending application IR-3052 Prov entitled NITROGEN POLAR III-N HJFET filed Dec. 30, 2005 the subject matter of which is incorporated herein by reference. It is further possible to employ the concept disclosed herein to devices containing a mix of one or more enhancement mode devices and one or more depletion mode devices.

[0032] Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention be limited not by the specific disclosure herein, but only by the appended claims.