Method and apparatus for data recovery in an optical transmission system

[0001] This application is a Continuation-in-Part of and claims priority to U.S. patent application Ser. No. 10/424,964, filed Apr. 28, 2003, now U.S. Pat. No. 7,254,343, which is incorporated herein by reference in its entirety.

[0002] This invention relates to the field of optical transmission systems and, more specifically, to improving the data recovery in such optical transmission systems via electrical decision feedback.

[0003] The maximum reach of long haul on-off keying transmission systems (such as a wavelength division multiplexed (WDM) transmission system operating at 20 Gbits/s or above) is typically limited by three types of signal distortion. Examples of such distortions are optical signal-to-noise ratio (OSNR) degradation, cross-talk and intersymbol interference (ISI). For the purposes of this discussion, ISI-related distortion are of further interest. ISI occurs when received data pulses are altered by pulse broadening or multi-path propagation (e.g., reflections) in the channel in which they travel. Pulse broadening can occur because of chromatic or polarization mode dispersions or receiver bandwidth limitations as described below. The results of such interference result in poor transmission characteristics.

[0004] One specific transmission characteristic that can drastically limit transmission in high-bit-rate systems, particularly for standard single-mode fibers (SSMF), is pulse-spreading type of ISI. This condition is shown in FIGS. 1a and 1b. Specifically, FIG. 1a depicts a graph 100 of the signal intensity I over time T for an input fiber of a WDM transmission system. The graph 100 is broken up into bit slots (denoted by sections 102, 104 and 106, respectively) which define the time slots available for data to be transmitted in such a system. At a first bit slot, bit slot 102, a “1” data bit (encoded in a non-return to zero (NRZ) format) is being transmitted followed by a “0” data bit in a second bit slot, bit slot 104. In a perfect WDM transmission system with perfectly formed fibers, the output intensity of these data pulses would be identical to the input data pulses shown in graph 100. Unfortunately, due to the above-identified interference conditions (pulse-spreading and the like), the signal sent to the output fiber is not identical to the signal sent to the input fiber.

[0005] More specifically, a graph of the signal intensity at the output fiber is seen in graph 120 of FIG. 1b. The graph 120 shows the same bit slots 102, 104 and 106 after the “1” and “0” data bits have passed through the transmission system. The resultant data stream is more rounded and not as well defined in the first bit slot 102 for the “1” data bit and furthermore extending into the second bit slot 104 which must represent the “0” data bit. ISI occurs when pulses propagating in the fiber spread out and overlap with each other. This condition can occur due to any of the above-described dispersion (or other) phenomena or by the bandwidth of a particular receiver being smaller than the system data rate (i.e., a 10 Gbits/s signal received by a 8 Gbit/s bandwidth limited receiver). The overlap, along with fiber nonlinearity, creates the ISI at locations of the “0” bits in a sequence of pulses, representing logical “1's” and “0's”. If the ISI becomes too large, it is detected by a receiver as logical “1's”, which can lead to transmission errors. These deleterious transmission characteristics are evidenced at the 10 Gbit/s transmission rate. As the bit rates of such a WDM transmission system increases, (i.e., for 20 Gbit/s, 40 Gbit/s and higher), the pulse broadening and subsequent ISI severely restricts the usable bandwidth of the system.

[0006] Methods of mitigating ISI and the effects it has on circuitry is found in various references including J. H. Winters, R. D. Gitlin, “Electrical Signal Processing Techniques in Long-haul Fiber-optic Systems”, IEEE Transactions on Communications, Vol. 38, Issue 9, September 1990, pp. 1439-1453; L. Möller, A. Thiede, S. Chandrasekhar, W. Benz, M. Lang, T. Jakobus, M. Schlechtweg, “ISI Mitigation Using Decision Feedback Loop Demonstrated with PMD Distorted 10 Gbit/s signals”, Electronics Letters, Nov. 25, 1999, Vol. 35, No. 24, pp. 2092-2093; H. Bülow, F. Buchali, W. Baumert, R. Ballentin, T. Wehren, “PMD Mitigation at 10 Gbit/s Using Linear and Nonlinear Integrated Electronic Equaliser Circuits”, Electronics Letters, Jan. 20, 2000, Vol. 36, No. 2, pp. 163-164; and J. H. Winters, S. Kasturia, “Adaptive Nonlinear Cancellation for High-speed Fiber-optic Systems”, IEEE Journal of Lightwave Technology, Vol. 10, No. 7, July 1992, pp. 971-977. However, as bit rates increase, such solutions will not be able to adequately compensate for the inevitable signal distortions.

[0007] As such, there remains a need for optical fiber transmission systems that can handle high-capacity communications while reducing the deleterious consequences of linear and/or non-linear distortions and PMD.

[0008] The present invention advantageously provides a method and apparatus for data recovery in an optical transmission system, where the method and apparatus provide a reduction of intra-channel distortions of received data resulting from linear and/or non-linear signal propagation. In one embodiment of the invention, an apparatus includes a plurality of parallel detection subcircuits for determining output values of a plurality of sequentially provided input optical data bits such that said sequentially provided input optical data bits are alternately processed by respective ones of said plurality of parallel detection subcircuits. For example, in one an embodiment of the present invention, clock values provided to the first parallel detection subcircuit to be used for timing are 180° out of phase with clock values provided to the second parallel detection subcircuit, such that the first parallel detection subcircuit and the second parallel detection subcircuit alternately process the input optical data bits according to odd valued clock signals and even valued clock signals, respectively.

[0009] In an alternate embodiment of the present invention, a method for data recovery includes comparing, in each of a plurality of parallel detection subcircuits, a received electrical representation of an optical data bit to a high voltage threshold and a low voltage threshold to determine an output value for the received electrical representation of an optical data bit, where sequentially provided electrical representations of optical data bits are alternately processed by the plurality of parallel detection subcircuits.

[0020] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures.

[0021] FIG. 2a depicts a circuit diagram of a decision feedback equalizer (DFE) 200 in accordance with the subject invention. The DFE 200 of the subject invention is capable of accepting electrical input data signals V_in based upon optical data signals, appropriately converted, and analyzing such data at a variety of circuit elements to output an appropriately recovered data signal component V_out1 or V_out2. More specifically, the DFE 200 compares the incoming data V_in to reference voltages denoting threshold detection points for data analysis. Dependent upon clock signaling and the prior data bit value, the DFE 200 will output the data signal component at either a first data output line V_out1 or a second data output line V_out2. The configuration of the DFE 200 is such that it facilitates processing of a data pulse stream (i.e., the incoming data signal V_in) of 10 Gbits/s and higher (e.g., 20 Gbits/s, 40 Gbits/s and the like) by splitting the incoming signal V_in into odd and even clock valued bits. As such, corresponding odd and even clock value actuated detection subcircuits are operating at only half of the transmission system data rate. The reader should note that FIG. 2a represents a simplified drawing of the circuit of the subject invention. Specifically, each line that connects circuit elements actually represents two lines, each of which carry complementary values of the signal traveling along the depicted line. Additional details are provided in the following description where necessary.

[0022] The DFE 200 comprises a plurality of parallel detection subcircuits 210_n for processing incoming data pulses V_in. In one embodiment of the subject invention, a first parallel subcircuit 210₁ and a second parallel subcircuit 210₂ are provided. Each subcircuit 210_n further comprises a plurality of input analyzers 202_n. The signal analyzers 202_n compare the incoming data V_in to threshold references (V_ref+ and V_ref−) in order to accurately recover data from V_in. As discussed above, each line in the depicted circuit represents two lines of complementary input. Accordingly, each signal analyzer 202_n has four actual inputs that are represented by the two depicted inputs. For example, the line carrying V_in to first signal analyzer 202₁ is actually one line connecting V_in to a non-inverting input (V_in+) and a second line connecting V_in to an inverting input on the first signal analyzer 202₁ (V_in−). The line carrying V₁ on the first signal analyzer 202₁ is actually one line connecting V_ref+ to a non-inverting input on the first signal analyzer 202₁ and a second line connecting V_ref− to an inverting input on the first signal analyzer 202₁ for a total of four inputs. Accordingly the line carrying V_ref2 on the second signal analyzer 202₂ is actually online connecting V_ref− to a non-inverting input on the signal analyzer 202₂ and a second line connecting V_ref+ to an inverting input on the second signal analyzer 202₂ for again a total of four inputs. Similar connections are made to the third and fourth signal analyzers 202₃ and 202₄, respectively. The results of the signal analyzers 202_n are passed on to a plurality of memory devices 204_n.

[0023] In the first subcircuit 210₁, the first signal analyzer 202₁ receives data V_in and compares it to an upper detection threshold (V_ref+) and sends the results to first memory unit 204₁. A second signal analyzer 202₂ receives input from V_in and compares it to a lower detection threshold reference (V_ref−). The result of the second signal analyzer 202₂ is passed on to second memory device 204₂. More specifically, each signal analyzer 202_n has two outputs (represented by the single output line shown). Each memory device 204_n has a non-inverting input D+ to accept one of the signal analyzer outputs and an inverting input D− to accept another of the signal analyzer outputs. Each of the plurality of memory devices 204_n is also provided with input that is correlated to the timing of the transmission system. In one embodiment, the memory devices 204_n are provided with input timing pulses at timing intervals that correspond to half of the system clock rate (CLK/2).

[0024] The single CLK/2 line represents two clock inputs (CLK/2)+ and (CLK/2)− applied to each memory device 204_n. The specific and strategic reason for designing the circuit with a complementary line configuration is that at the high operational speed of the circuit, it is easier to decide about the difference between two voltages (applied signals) than to decide about their absolute value. In other words, common mode distortions are more easily suppressed with the described configuration. The output of each of the plurality of memory units 204_n is provided to a selector unit 206_n. Specifically, and in one embodiment, the output from first memory device 204_i and the output of second memory device 204₂ is provided to first selector 206₁.

[0025] The second subcircuit 210₂ is similarly configured and wired as the first subcircuit 210₁. Specifically, a third signal analyzer 202₃ receives inputs from V_in and upper threshold reference V_ref1 and outputs the results to third memory device 204₃. Similarly, fourth signal analyzer 202₄ is provided with input from V_in and the lower detection threshold V_ref2. The output of fourth signal analyzer 202₄ is provided as input to a fourth memory device 204₄. Each of the third and fourth memory devices 204₃ and 204₄ are also provided with timing pulses that are correlated to the transmission system timing. Specifically, and in one embodiment, second subcircuit 210₂ is provided with input timing pulses at timing intervals that are half of the system clock. However, these timing pulses are opposite or 180° out of phase with pulses provided to the first subcircuit 210₁ (i.e., CLK/2). Outputs from the third and fourth memory units 204₃ and 204₄ are provided to a second selector 206₂.

[0026] The selector 206 from each subcircuit 210_n is crosswired to its counterpart in the other subcircuit. In this manner, each subcircuit 210_n is connected to its parallel counterpart so that each subcircuit controls the selection for the next bit in the other subcircuit 210_n. The output from each selector 206₁ and 206₂ is provided as input to first and second secondary memory units 208₁ and 208₂, respectively. First secondary memory unit 208₁ is provided with an input clock signal one half the clock rate of the transmission system (CLK/2). Second secondary memory unit 208₂ is provided with an input clock signal one half the clock rate of the transmission system but at 180° out of phase with the first subcircuit 210₁ ( CLK/2). Accordingly, if the input data pulse at V_in is an odd clock valued data pulse, its recovered output can be found at V_out1. If incoming data V_in is an even clock valued data pulse, the output can be found out at V_out2. Effectively, each subcircuit 210_n divides the data recovery tasks so that each subcircuit 210_n is only working at one half the system clock rate (CLK typically 10, 20 Gbits/s or higher).

[0027] The DFE 200 of FIG. 2a, is created using a plurality of switching and logic components. In one embodiment, the DFE 200 is realized using an enhancement-depletion AlGaAs/GaAs HEMT technology with a 0.2 μm gate length and a threshold frequency of about 60 GHz. Optionally, the DFE 200 is built in source-coupled FET logic for better common-mode noise rejection and high speed circuit operation. Differential coplanar waveguides are implemented on a single chip for providing both clock pulses and data pulses to the circuit 200. In one particular example, the entire DFE circuit 200 comprises approximately 310 FETs on a chip area of approximately 2.5 mm² and operates at a power consumption level of approximately 1.9 W. Accordingly, the subject invention has the capabilities of providing differential feedback equalization to a 20 Gbits/s signal. This design takes advantage of parallel signal processing which reduces electrical bandwidth requirements of the circuit while increasing the gain of a received signal with greater accuracy then previously realizable. One skilled in the art can also understand that since the typical delays associated with a basic feedback loop configuration have been eliminated, incoming signal rates of up to 20 Gbits/s and higher can be processed with the same or better results than the processing of slower signals in the conventional manner.

[0028] Another embodiment of the invention is seen in FIG. 2b depicting an optical receiver 250 incorporating the DFE 200. Specifically, optical receiver 250 receives a train of broad spectrum (WDM) optical data pulses from transmission line 252. The pulses are provided to an optical demultiplexer 254 which segregates the broad spectrum pulses into individual wavelength pulses. The optical receiver may or may not incorporate a single broad spectrum or individual wavelength amplifiers (not shown, but understood by those skilled in the art) to improve incoming pulse quality prior to further processing. Subsequent to demultiplexing, the individual wavelength pulses are provided to a plurality of converters 256 which convert the optical signal into an electrical signal (a logical “1” or “0”). These electrical signals are then provided to a plurality of DFE's 200 for analysis and data recovery as described to provide a plurality of data recovered electrical signals 258.

[0029] There are several types of optical data receivers, which can benefit from the above-identified DFE. More specifically, two basic types of optical data receivers are a PIN receiver and an optically pre-amplified receiver. Typically, PIN receivers include, among other components, a photodiode for receiving optical data signals from a transmission line followed by an electrical amplifier. Such a receiver configuration introduces a certain amount of terminal noise into the received signal prior to threshold detection (or recovery); hence, such a receiver requires a relatively higher degree of received power than an optically pre-amplified receiver. The optically pre-amplified receiver contains, among other components, an optical amplifier which receives optical data signals from a transmission line and amplifies them. Subsequent to optical pre-amplification, the received data signal is passed through a band-pass filter (BPF) so as to filter undesirable optical components and sharpen the received signal. Subsequent to band-pass filtering, the received signal is passed to a photodiode which converts the optical signal into an electrical signal.

[0030] The performance gain of a PIN and optically pre-amplified receivers with implemented DFE is described as follows. For PIN receivers, symbol independent thermal noise is the main noise source. For optically pre-amplified receivers, the signal-ASE beat noise becomes dominant. Consequently there will be different performance gains for DFE operation in both receiver types. The amount of InterSymbol Interference (ISI) in both receivers in the examples was the same. For the purpose of equalization gain estimation, FIG. 4 shows an eye diagram 400 of an ISI distorted NRZ signal. For a PIN receiver, the Q factor of the unequalized signal is given by

[0031] $Q\approx \left(\frac{I_{\max }-I_{\min }}{2{\sigma }_{\mathrm{th}}}\right)$
where I_max, I_min and σ_th stand for the inner eye borders (traces) and the variance of the thermal noise respectively. Perfect cancellation of the trace representing I_min by means of the DFE would improve the receiver sensitivity by a penalty reduction of

[0032] $\Delta =-20\log \lfloor \frac{Q_{\mathrm{DFE}}}{Q_{\mathrm{ISI}}}\rfloor =-20\log \lfloor \frac{I_{\max }-I_{\min }}{I_{\max }}\rfloor$
In the case of an optically pre-amplified receiver, the noise variance becomes symbol dependent. Good approximations for Q factors with and without DEE operation are then given by

[0033] $Q\approx \frac{I_{\max }-I_{\min }}{X_{\mathrm{ASE}}\sqrt{I_{\max }}+X_{\mathrm{ASE}}\sqrt{I_{\min }}}$ $Q_{\mathrm{DFE}}\approx \frac{I_{\max }^{\prime }}{X_{\mathrm{ASE}}\sqrt{I_{\max }^{\prime }}+X_{\mathrm{ASE}}\sqrt{I_{\min }^{\prime }}}$ $\Delta =10\log \lfloor \frac{I_{\max }}{I_{\max }^{\prime }}\rfloor {❘}_{Q_{\mathrm{DFE}=Q}}$
where X_ASE is a parameter that describes the signal ASE beat noise. When assuming that _Imax and I_min are proportional to each other, the penalty reduction in the case of the optically pre-amplified receiver is expected to be twice than that for the PIN receiver. Also the ISI amount can be estimated after the penalty is measured.

[0034] In one example, a 20 Gb/s signal was generated by polarization multiplexing of two orthogonally polarized and de-correlated 10 Gb/s 33% RZ data streams. By time interleaving of the 2³¹-1 PRBS data streams with 50 ps phase offset the ISI was minimized. A lightwave converter with relative small electrical bandwidth was used to detect the 20 Gb/s signal. After launching the signal to the decision circuit that included a 2:1 electrical de-mux, the bit error rate measurement was performed at 10 Gb/s data rate. FIG. 3 depicts graphs denoting the characteristics of each type of receiver described above. Specifically, FIG. 3a shows a graph 300 plotting received power of a PIN receiver versus the bit error rate (in logarithmic scale). FIG. 3b depicts a graph 310 plotting received power of an optically pre-amplified receiver versus the bit error rate (in logarithmic scale). First line 302 (corresponding to the star data points) denote the received power versus bit error rate with a DFE equipped PIN receiver, while a line at 304 (corresponding to the square data points) reflects the same characteristics without DFE. Inspection readily reveals that it is possible to lower the power of a transmitted data signal to the PIN receiver simply by virtue of DFE recovery techniques as described in the subject invention. Similarly, FIG. 3b shows similar lines for a pre-amplified receiver. That is, line 306 (corresponding to the star data points) reveals a lower power of a transmitted signal to the optically pre-amplified receiver with DFE than that of a line at 308 (corresponding to the square data points) of such receiver not using DFE. Specifically, the gain from feedback equalization from the subject invention was about 3 dB for the PIN receiver and about twice that for the optically pre-amplified receiver. This is in good agreement with the derivations. The experimental result estimates the ISI to be about 50% (0.5 I_max≈I_min) in front of the decision element without feedback operation. From this we conclude the overall electrical bandwidth of the front end to be around 10 GHz. Accordingly, the results shown herein indicate that there is an improvement in systems using the DFE of the subject invention in that the received power of a transmitted data signal can be reduced and yet still maintain accurate data recovery.

[0035] FIG. 5 depicts a circuit diagram of an alternate embodiment of a decision feedback equalizer (DFE) 500 in accordance with the subject invention. The DFE 500 of FIG. 5 comprises the same components and provides substantially the same function as the DFE 200 of FIG. 2 however, in the DFE 500 of FIG. 5, the first and second secondary memory devices are included within the feedback loop. More specifically, the DFE 500 of FIG. 5 comprises a plurality of parallel detection subcircuits (illustratively two parallel detection subcircuits) 510₁-510₂ for processing incoming data pulses V_in. Each subcircuit 510_n further comprises a plurality of input analyzers 502_n. The signal analyzers 502_n compare the incoming data V_in to threshold references (V_ref1 and V_ref2) in order to accurately recover data from V_in. As discussed above, each line in the depicted circuit represents two lines of complementary input. Accordingly, each signal analyzer 502_n has four actual inputs that are represented by the two depicted inputs. The results of the signal analyzers 502_n are communicated to a plurality of memory devices 504_n (at least one respective memory device for each signal analyzer), illustratively depicted as flip-flops.

[0036] As in the DEF 200 of FIG. 2, in the first subcircuit 510₁ of the DEF 500 of FIG. 5, the first signal analyzer 502₁ receives data V_in, compares it to an upper detection threshold (V_ref1) and communicates the results to the first memory device 504₁. The second signal analyzer 502₂ receives input from V_in and compares it to a lower detection threshold reference (V_ref2). The result of the second signal analyzer 502₂ is communicated to the second memory device 504₂. As described above, each memory device 504_n has a non-inverting input to accept one of the signal analyzer outputs and an inverting input to accept another of the signal analyzer outputs. Each of the plurality of memory devices 504_n is also provided with an input that is correlated to the timing of the transmission system. For example, in the DFE 500 the memory devices 504_n are provided with input timing pulses at timing intervals that are half of the system clock rate (CLK/2).

[0037] Again, the single CLK/2 line represents two clock inputs (CLK/2)+ and (CLK/2)− applied to each memory device 504_n. The output of each of the memory devices 504_n of the first subcircuit 510₁ is provided to a first selector 506₁.

[0038] The second subcircuit 510₂ is similarly configured and arranged as the first subcircuit 510₁. Specifically, a third signal analyzer 502₃ receives inputs from V_in and upper threshold reference V_ref1 and communicates the results to a third memory device 504₃. Similarly, a fourth signal analyzer 502₄ is provided with input from V_in and the lower detection threshold (V_ref2). The output of the fourth signal analyzer 502₄ is communicated to a fourth memory device 504₄. Each of the third and fourth memory devices 504₃ and 504₄ are also provided with timing pulses that are correlated to the transmission system timing. Specifically, in the embodiment of FIG. 5, the second subcircuit 510₂ is provided with input timing pulses at timing intervals that are half of the system clock. However, these timing pulses are 180° out of phase with pulses provided to the first subcircuit 510₁. The outputs of the third and fourth memory devices 504₃ and 504₄ are provided to a second selector 506₂.

[0039] The output from each selector 506₁ and 506₂ is provided as an input to respective first and second secondary memory devices 508₁ and 508₂. The first secondary memory device 508₁ is provided with an input clock signal one half the clock rate of the transmission system (CLK/2). The second secondary memory device 508₂ is provided with an input clock signal one half the clock rate of the transmission system but at 180° out of phase with the first subcircuit 510₁. Accordingly, if the input data pulse at V_in is an odd clock valued data pulse, its recovered output can be found at V_out1. If incoming data V_in is an even clock valued data pulse, the output can be found out at V_out2. Effectively, each subcircuit 510_n divides the data recovery tasks so that each subcircuit 510₁-510₂ is only working at one half the system clock rate.

[0040] However, in the DFE 500 of FIG. 5, unlike in the DFE 200 of FIG. 2, instead of cross-feeding the output of each of the selectors 506_n to its parallel counterpart (i.e., feeding back as a control signal the output of the first selector 506₁ in the first subcircuit 510₁ to the second selector 506₁ in the second subcircuit 510₂), a feedback signal is coupled to each of the selectors 506_n from the output of the secondary memory device 508_n in the parallel counterpart circuit. More specifically and as depicted in the DFE 500 of FIG. 5, at least a portion of the output of the first secondary memory device 508₁ in the first subcircuit 510₁ is fed back as a control signal to the second selector 506₂ in the second subcircuit 510₂. Similarly, at least a portion of the output of the second secondary memory device 508₂ in the second subcircuit 510₂ is fed back as a control signal to the first selector 506₁ in the first subcircuit 510₁. In this configuration, the control signal and the input data to the selectors 506₁ are synchronized. As such, the control signals from the respective subcircuits have no influence on each other and unwanted pulse spikes in the output of the selectors 506_n, due to timing differences between the input data and the control data to the selectors 506_n, are avoided.

[0041] FIG. 6 depicts a circuit diagram of an alternate embodiment of a decision feedback equalizer (DFE) 600 in accordance with the subject invention. The DFE 600 of FIG. 6 comprises substantially the same components as the DFE 200 of FIG. 2 and the DFE 500 of FIG. 5 and provides the synchronization of the control signals and the input data to the selectors 506_n as in the DFE 500 of FIG. 5 however, in the DFE 600 of FIG. 6, the input data in at least one of the subcircuits is sampled twice before being communicated to the selectors. More specifically, the DFE 600 of FIG. 6 comprises a plurality of parallel detection subcircuits (illustratively two parallel detection subcircuits) 610₁-610₂ for processing incoming data pulses V_in. Each subcircuit 610_n further comprises a plurality of input analyzers 602_n. The signal analyzers 602_n compare the incoming data V_in to threshold references (V_ref1 and V_ref2) in order to accurately recover data from V_in. As discussed above, each line in the depicted circuit represents two lines of complementary input. Accordingly, each signal analyzer 602_n has four actual inputs that are represented by the two depicted inputs. The results of the signal analyzers 602_n are communicated to a plurality of memory devices 604_n (at least one respective memory device for each signal analyzer), illustratively depicted as flip-flops.

[0042] As in the DEF 200 of FIG. 2 and the DEF 500 of FIG. 5, in the first subcircuit 610₁ of the DEF 600 of FIG. 6, the first signal analyzer 602₁ receives data V_in and compares it to an upper detection threshold (V_ref1) and communicates the results to the first memory device 604₁. The second signal analyzer 602₂ receives the input from V_in and compares it to a lower detection threshold reference (V_ref2). The result of the second signal analyzer 602₂ is communicated to the second memory device 604₂. As described above, each memory device 604_n has a non-inverting input to accept one of the signal analyzer outputs and an inverting input to accept another of the signal analyzer outputs. Each of the plurality of memory devices 604_n is also provided with an input that is correlated to the timing of the transmission system. For example, in the DFE 600 the memory devices 604_n are provided with input timing pulses at timing intervals that are half of the system clock rate (CLK/2). In the first subcircuit 610₁, the outputs of the first memory device 604₁ and the second memory device 604₂ are communicated to the first selector unit 606₁. The output of the first selector unit 606₁ is communicated to a first secondary memory device 608₁.

[0043] In the second subcircuit 610₂ of the DFE 600 of FIG. 6, a third signal analyzer 602₃ receives inputs from V_in and the upper threshold reference V_ref1 and communicates the results to a third memory device 604₃. Similarly, a fourth signal analyzer 602₄ is provided with an input from V_in and the lower detection threshold (V_ref2). The output of the fourth signal analyzer 602₄ is provided as an input to a fourth memory device 604₄. The third and fourth memory devices 604₃ and 604₄ are also provided with timing pulses that are correlated to the transmission system timing. Specifically, in the embodiment of FIG. 6, the second subcircuit 610₂ is provided with input timing pulses at timing intervals that are half of the system clock. However, these timing pulses are 180° out of phase with pulses provided to the first subcircuit 610₁.

[0044] Unlike in the DFE 200 of FIG. 2 and the DFE 500 of FIG. 5, in the second subcircuit 610₂ of the DFE 600 of FIG. 6, the output of the third memory device 604₃ is communicated to a second secondary memory device 608₂ and the output of the fourth memory device 604₄ is communicated to a third secondary memory device 608₃. As evident in the DFE 600 of FIG. 6, with such a configuration, the input data is sampled twice in the second subcircuit 610₂ before being communicated to a respective selector 606_n. More specifically, the outputs of the second secondary memory device 608₂ and the third secondary memory device 608₃ are communicated to a second selector 606₂. It should be noted that in the DFE 600 of FIG. 6, the clock signals (clock tones) provided to the second secondary memory device 608₂ and the third secondary memory device 608₃ are in phase.

[0045] In the DFE 600 of FIG. 6, the output of the first secondary memory device 608₁ in the first subcircuit 610₁ is cross-fed as a control signal to the second selector 606₂ in the second subcircuit 610₂. In the second subcircuit 610₂, the output of the second selector 606₂ is cross-fed as a control signal to its parallel counterpart, the first selector 606₁ in the first subcircuit 610₁. With such a configuration, in the first subcircuit 610₁ the input data of the first selector 606₁ arrives earlier than the control signal fedback from the second subcircuit 610₂. As such, some pulse spikes in the output of the first selector 606₁ may occur, however the sampling of the output of the first selector 606₁ taken by the first secondary memory device 608₁ occurs at a time away from any produced pulse spike. One advantage of the configuration of the DFE 600 of FIG. 6 over the configuration of the DFE 500 of FIG. 5 is that in the DFE 500 of FIG. 5 the delay limit for the selectors 506_n and the respective secondary memory devices 608_n is limited to within half of period of half of the system clock rate (CLK/2), which limits the maximum input data rate of an input signal to the DFE 500. In contrast, the configuration of the DFE 600 of FIG. 6 relaxes the speed limitation of the components in the feedback path, which allows for a higher input data rate for the DFE 600 of FIG. 6.

[0046] A DFE in accordance with the present invention is capable of being constructed using SiGe:C Heterobipolar technology described in “Novel collector design for high-speed SiGe:C HBTs”, B. Heinemann et al., IEDM, 2002, which herein incorporated by reference in its entirety. More specifically, the SiGe:C Heterobipolar technology is an epi-free and single-poly technology with 0.25 μm minimum lithographic feature size and four metal layers. The technology incorporates low concentration of carbon into the SiGe region of a heterojunction bipolar transistor (HBT), which significantly suppresses boron outdiffusion caused by subsequent processing steps and improves HBT performance. The transit frequency and oscillation frequency of DFE circuits in accordance with the present invention constructed in SiGe:C Heterobipolar technology measure up to 200 GHz at a breakdown voltage of 2.0 volts and display extremely low ring oscillator delay of 4.2 ps.

[0047] Although various embodiments that incorporate the teachings of the present invention have been shown and described in detail herein, those skilled in the art can readily devise many other varied embodiments that still incorporate these teachings.