Method for fast SATD estimation

[0001] The present invention generally relates to image processing and, more particularly, to a method and device for fast SATD (Sum of Absolute Transformed Differences) estimation.

[0002] In recent years, it has become increasingly popular to transmit multimedia data, in particular, dynamic digital video data, via the Internet. Compression of digital video data is required for the transmission of multimedia data over bandwidth-constrained channels. To achieve efficient compression, complex, computationally intensive processes are used for encoding (i.e., compressing) and decoding (i.e., decompressing) the digital video data. For example, although MPEG-2 (Moving Pictures Expert Group, International Organization for Standards, Geneva, Switzerland) is known as an efficient technique for encoding video data, more efficient standards are being developed, such as the H.264/AVC (“Advanced Video Coding”) standard proposed by International Telecommunication Union Telecommunication Standardization Sector, Geneva, Switzerland.

[0003] The prediction mode of the H.264/AVC may be categorized into an inter mode and an intra mode. The inter mode is used to describe the temporal correlation between blocks within an image frame and a reference frame, while the intra mode is used to describe the spatial correlation between neighboring blocks within a same image frame. In the inter mode, a block of an image frame may be further divided into multiple blocks in accordance with seven partition modes, i.e., the inter 16×16, inter 16×8, inter 8×16, inter 8×8, inter 8×4, inter 4×8 and inter 4×4 modes. On the other hand, in the intra mode, the intra 16×16 and intra 4×4 modes are used as the partition modes. An encoder conducts a best-mode search to determine the encoding cost of each of the partition modes under the inter mode and the intra mode, respectively. The encoder then compares the inter mode that has the lowest encoding cost and the intra mode that has the lowest encoding cost to determine the final best mode. The above-mentioned process is typically called mode decision, which is the most computationally intensive task for an H. 264/AVC encoder.

[0004] In the H.264/AVC reference software, SATD (Sum of Absolute Transformed Differences) is used to determine the encoding cost. The SATD is usually the most important term and the largest computational load for making a mode decision. As compared to the conventional SAD (Sum of Absolute Differences), SATD is more precise in estimating the cost and provides better encoding quality. However, SATD may require larger computation capacity and a larger hardware budget due to its computation complexity.

[0005] The existing methods for fast SATD operation are generally directed to a Hadamard transform. Specifically, most of the existing methods are based on the FHT (Fast Hadamard Transform) algorithm, which is an FFT-like (Fast Fourier Transform) method. Other methods may be related to reducing the number of video samples taken or performing only a part of transform, which decreases the operation time at the sacrifice of SATD precision. It is therefore desirable to have a system and method to reduce the computation complexity and increase the speed in SATD operation without compromising the SATD performance.

[0006] In accordance with an embodiment of the present invention, there is provided a method for determining an encoding cost for a block of video data that comprises providing an image frame, partitioning the image frame into multiple blocks, obtaining a difference matrix for one of the multiple blocks, performing a part of an FHT (Fast Hadamard Transform) for the difference matrix including at least one butterfly step to obtain outputs in a sequence, the at least one butterfly step in number being one butterfly step less than that required for performing the entire FHT, performing an absolute value operation for each of the outputs, comparing the absolute values of every two of the outputs according to the sequence to determine a greater value for each of the every two absolute values, and adding the greater value of each of the every two absolute values thereby obtaining the encoding cost as a sum of absolute transformed differences (SATD) of the difference matrix.

[0007] Also in accordance with the present invention, there is provided a method for determining an encoding cost for a block of video data that comprises providing an image frame, partitioning the image frame into multiple blocks including one having a size of N×M, N and M being integers, obtaining a difference matrix of N×M for the one block, performing a part of an FHT (Fast Hadamard Transform) for the difference matrix including a number of [(log₂ NM)−1] butterfly steps to obtain outputs in a sequence, performing an absolute value operation for each of the outputs, comparing the absolute values of every two of the outputs according to the sequence to determine a greater value for each of the every two absolute values, and adding the greater value of each of the every two absolute values thereby obtaining the encoding cost as a sum of absolute transformed differences (SATD) of the difference matrix.

[0008] Further in accordance with the present invention, there is provided a method for determining an encoding cost for a block of video data that comprises providing an image frame, partitioning the image frame into multiple blocks, obtaining a difference matrix for one of the multiple blocks, performing a part of an FHT (Fast Hadamard Transform) for the difference matrix including at least one butterfly step to obtain outputs in a sequence, the at least one butterfly step in number being one butterfly step less than that required for performing the entire FHT, performing a summing operation for every two of the outputs according to the sequence to obtain a sum, performing a first comparison operation for every two of the outputs according to the sequence, and performing a second comparison operation for the sum and zero thereby obtaining the encoding cost as a sum of absolute transformed differences (SATD) of the difference matrix.

[0009] Still in accordance with the present invention, there is provided a method for determining an encoding cost for a block of video data that comprises providing an image frame, partitioning the image frame into multiple blocks, obtaining a difference matrix for one of the multiple blocks, performing a part of an FHT (Fast Hadamard Transform) for the difference matrix including at least one butterfly step to obtain outputs in a sequence, the at least one butterfly step in number being one butterfly step less than that required for performing the entire FHT, and performing comparison operations for values corresponding to every two of the outputs according to the sequence thereby obtaining the encoding cost as a sum of absolute transformed differences (SATD) of the difference matrix.

[0010] Yet still in accordance with the present invention, there is provided a device for determining an SATD (Sum of Absolute Transformed Differences) for a difference matrix that comprises a fast Hadamard transformer for performing a part of an FHT (Fast Hadamard Transform) for the difference matrix including at least one butterfly step to obtain outputs in a sequence, the at least one butterfly step in number being one butterfly step less than that required for performing the entire FHT, a processing unit for performing an absolute value operation for each of the outputs, a comparator unit for comparing the absolute values of every two of the outputs according to the sequence to determine a greater value for each of the every two absolute values, and a summing unit for adding the greater value of each of the every two absolute values.

[0025] The differences between a predict block provided in accordance with the prediction mode of the H.264/AVC and an actual block are called residual differences, generally in the form of a matrix, denoted as D_N×M={d_i,j}, where N×M is a block size, N=2ⁿ, M=2^m, 0≦i<N, 0≦j<M, N and M being integers. The SATD (Sum of Absolute Transformed Differences) and SAD (Sum of Absolute Differences) are defined below as:

[0026] $\begin{array}{cc}{\mathrm{SAD}}_{N\times M}\left(D_{N\times M}\right)=\sum _{i=0}^{N-1}\sum _{j=0}^{M-1}d_{i,j}& \mathrm{Equation}\left(1\right)\\ {\mathrm{SATD}}_{N\times M}\left(D_{N\times M}\right)={\mathrm{SAD}}_{N\times M}\left(T\left(D_{N\times M}\right)\right)& \mathrm{Equation}\left(2\right)\end{array}$

[0027] where T is an orthogonal transform function for transforming an N×M matrix into another N×M matrix. An SATD operation includes transforming the residual differences of two blocks into a frequency domain, and computing the sum of the absolute differences thereafter.

[0028] In the H.264/AVC reference software, the orthogonal transform used in the SATD is the Hadamard transform. One of the advantages of the Hadamard transform is its simplicity in computation, which may be composed of two types of operators, i.e., addition and shifting. The Equation (2) can be rewritten as follows.

[0029] $\begin{array}{cc}{\mathrm{SATD}}_{N\times M}\left(D_{N\times M}\right)=\frac{2}{\sqrt{\mathrm{NM}}}·{\mathrm{SAD}}_{N\times M}\left(H_n{D}_{N\times M}{H}_m\right)& \mathrm{Equation}\left(3\right)\end{array}$

[0030] where H_n and H_m are Hadamard matrixes of N×N and M×M, respectively, 1/√{square root over (N)} and 1/√{square root over (M)} are the orthogonal coefficients of the matrixes H_n and H_m, respectively, and the constant 2 is a parameter to balance the SATD and SAD scales in the H.264/AVC reference software.

[0031] The Hadamard matrix used in the Equation (3) may be defined in the recursive form below.

[0032] $\begin{array}{cc}{H}_1=\left[\begin{array}{cc}1& 1\\ 1& -1\end{array}\right]& \mathrm{Equation}\left(4\right)\\ H_{k+1}=\left[\begin{array}{cc}{H}_k& H_k\\ H_k& -H_k\end{array}\right],\forall k\ge 1& \mathrm{Equation}\left(5\right)\end{array}$

[0033] If matrix multiplication is directly used to implement the SATD, as an example of SATD_4×4, a total number of 111 operations are required, of which 96 operations account for the H₂D_4×4H₂ part, and 15 operations account for the SAD_4×4 part in the Equation (3). However, using a fast computation method similar to a Fast Fourier Transform algorithm, i.e., FHT (Fast Hadamard Transform) algorithm, the number of operations required in the Hadamard transform may be reduced. For example the FHT requires only 12 (=4×3) addition/subtraction operations to calculate a matrix multiplication below.

[0034] $\left[\begin{array}{c}{y}_0\\ y_1\\ y_2\\ y_3\end{array}\right]=\left[\begin{array}{cccc}1& 1& 1& 1\\ 1& -1& 1& -1\\ 1& 1& -1& -1\\ 1& -1& -1& 1\end{array}\right]\left[\begin{array}{c}{x}_0\\ x_1\\ x_2\\ x_3\end{array}\right]$

[0035] Further, if a butterfly structure is employed to compute the FHT, only 8 (=4×log₂ 4) addition/subtraction operations are required. FIG. 1A illustrates a butterfly structure used in an FHT application. A butterfly structure including addition and subtraction operations in N-point transforms is called an N-point butterfly. Referring to FIG. 1A, the butterfly structure, which is a 4-point butterfly, includes a first butterfly step and a second butterfly step. Each of the first and second butterfly steps includes the crossing flow of data from input to output. However, the topology of data crossing in the first butterfly step is different from that in the second butterfly step, and therefore the butterfly structure does not include any recursion. For the H₂D_4×4H₂ part in the Equation (3), the number of addition operations required is reduced to 64 (=16×log₂ 16) if the butterfly structure illustrated in FIG. 1A is used.

[0036] The butterfly structure illustrated in FIG. 1A may be revised to another form. FIG. 1B illustrates another butterfly structure used in an FHT application. The butterfly structure, also a 4-point butterfly, includes a first butterfly step and a second butterfly step, having the same topology of data crossing as the first step. Such a butterfly structure includes recursion and is advantageous in hardware and software design, even though the number of addition/subtraction operations required is not further reduced as compared to the butterfly structure illustrated in FIG. 1A. Given an N×M block, in accordance with the butterfly structure illustrated in FIG. 1B, the H_nD_N×MH_m part in the Equation (3) is expressed in but is not limited to a recursive form as follows.

[0037] $\begin{array}{cc}{t}_{i·M+j}^0=d_{i,j}& \mathrm{Equation}\left(6\right)\\ \{\begin{array}{c}{t}_{2l}^{k+1}=t_l^k+t_{l+\frac{\mathrm{NM}}{2}}^k\\ t_{2l+1}^{k+1}=t_l^k-t_{l+\frac{\mathrm{NM}}{2}}^k\end{array},\forall k\ge 0& \mathrm{Equation}\left(7\right)\end{array}$

[0038] where the Equation (6) defines an initial value and the Equation (7) defines the recursive body.

[0039] With the Equations (6) and (7), the Equation (3) can be rewritten as follows.

[0040] $\begin{array}{cc}{\mathrm{SATD}}_{N\times M}\left(D_{N\times M}\right)=\frac{2}{\sqrt{\mathrm{NM}}}\sum _{l=0}^{\mathrm{NM}-1}t_l^{n+m}& \mathrm{Equation}\left(8\right)\end{array}$

[0041] In view of the Equation (8), it is known that a total number of (n+m) recursion operations are required for k=0 to k=(n+m−1). Since a number of N×M addition operations are required for each of the recursion operations, the total number of addition operations required for the H_nD_N×MH_m part in the Equation (8) is NM×(n+m), i.e., NM×log₂ (NM). As a comparison, the total number for the H_nD_N×MH_m part in the Equation (3) is NM×(N+M−2).

[0042] To reduce the number of operations required in the Equation (8), an equation as given below may be used.
|a+b|+|a−b|=2·max(|a|,|b|)  Equation (9)

[0043] That is, a maximum value operation, which refers to one for comparing two values to select a greater one, is used to reduce the number of addition operations. By substituting the Equation (9), the Equation (8) is rewritten as follows.

[0044] $\begin{array}{cc}{\mathrm{SATD}}_{N\times M}\left(D_{N\times M}\right)=\frac{4}{\sqrt{\mathrm{NM}}}\sum _{l=0}^{\frac{\mathrm{NM}}{2}-1}\max \left(t_l^{n+m-1},t_{l+\frac{\mathrm{NM}}{2}}^{n+m-1}\right)& \mathrm{Equation}\left(10\right)\end{array}$

[0045] In the Equation (10), the number of recursion operations is (n+m−1). Table 1 lists the number of operations required for each of the operators in the Equations (8) and (10), given SATD_4×4.

[0046]

TABLE 1
operator/
equation	add	max	abs	total
Equation	79	0	16 (=NM)	95 (=NM (n +
(8)	(=NM (n + m) +			m + 2) − 1)
	(NM − 1))
Equation	55 (=NM (n +	8	16 (=NM)	79 (=NM (n +
(10)	m − 1) +	(=NM/2)		m + 1) − 1)
	NM/2 − 1)

[0047] A total number of 16 operations are eliminated in the Equation (10) as compared to the Equation (8) because one recursion operation is eliminated. If it is assumed that the operation time required for each of the addition (add), maximum value (max) and absolute value (abs) operators is the same, given SATD_4×4, such elimination advantageously results in the improvement of the operation speed as well as the reduction in physical operators, and in turn a decrease in the hardware cost. Furthermore, the elimination of one recursion operation and the use of maximum value operation saves memory space requirement for computing the SATD.

[0048] FIGS. 2A and 2B illustrate the number of bits required for the SATD in a conventional method. Referring to FIG. 2A, given SATD_N×M and a pixel size of p bits, for the residual differences of 2ⁿ×2^m, a total number of (p+1)×2^(n+m) bits are required. A Hadamard transform including (n+m) times of recursion operations is performed, resulting in a total memory space requirement of (p+1+n+m)×2^(n+m) bits. Next, absolute value operations are performed, which require (p+n+m)×2^(n+m) bits due to the elimination of sign bits. After addition operations, the size of the SATD is (p+2n+2m)-bit. FIG. 2B illustrates an example given SATD_4×4 and a pixel size of 8 bits (i.e., d_i,j having a size of 9 bits and having a value ranging from −255 to 255), resulting in a 16-bit SATD.

[0049] FIG. 3A is a schematic structure 30 for implementing the conventional method illustrated in FIG. 2B. Referring to FIG. 3A, the structure 30 includes a 2-step FHT device 12, absolute-value devices 14, summing devices 16 and 17 including adders or subtractors, and a shifter 18. The FHT device 12 performs an entire FHT including two butterfly steps for input difference values x₀, x₁, x₂ and x₃ of a difference matrix to obtain a plurality of outputs y₀, y₁, y₂ and y₃ in a sequence. The absolute value of each of the outputs y₀, y₁, y₂ and y₃ is calculated in the absolute-value devices 14. These absolute values are added in summing devices 16 and 17 to obtain a binary resultant value. The resultant value in its binary form is then shifted right by one bit in the shifter 18 to obtain an SATD.

[0050] FIG. 3B is a schematic diagram illustrating the calculation of an SATD in the structure 30 illustrated in FIG. 3A. Referring to FIG. 3B, it is presumed that the FHT device 12 employs the butterfly structure illustrated in FIG. 1B and the input difference values x₀, x₁, x₂ and x₃ are 3, −1, −2 and 4, respectively. After the first butterfly step, also referring to FIG. 1B, the outputs are 1, 5, 3 and −5. After the second butterfly step, the outputs y₀, y₁, y₂ and y₃ are 6, −4, −2 and 8, respectively. The absolute-values devices 14 calculate the absolute values of the outputs y₀, y₁, y₂ and y₃, which are 6, 4, 2 and 8, respectively. The absolute values of the outputs y₀ and y₁, and y₂ and y₃ are added in the first-stage summing devices 16. First resultant values, i.e., 10 and 10, are then added in the second-stage summing device 17 to obtain a second resultant value, 20. The second resultant value in binary form is shifted right by one bit at the shifter 18 to obtain the SATD, 10.

[0051] FIGS. 4A and 4B illustrate the number of bits required for the SATD in a method in accordance with one embodiment of the present invention. Referring to FIG. 4A, given SATD_N×M and a pixel size of p, for the residual differences of 2ⁿ×2^m, a total number of (p+1)×2^(n+m) bits are required. In accordance with a method of the present invention, a part of an FHT including (n+m−1) butterfly steps, either including recursion or not, is performed, resulting in a total memory space requirement of (p+n+m)×2^(n+m) bits. Next, absolute value operations are performed, which require (p+n+m−1)×2^(n+m) bits due to the elimination of sign bits. Next, maximum value operations are performed, which require (p+n+m−1)×2^(n+m−1) bits. After addition operations, the size of the SATD is (p+2n+2m−2)-bit, which is 2-bit smaller in size than that of the SATD of the conventional method shown in FIG. 2A. FIG. 4B illustrates an example given SATD_4×4 and a pixel size of 8 bits, resulting in a 14-bit SATD.

[0052] FIG. 5A is a schematic structure 50 for implementing the method illustrated in FIG. 4B. Referring to FIG. 5A, the structure 50 includes a 1-step FHT device 22, absolute-value devices 24, comparators 26 for performing maximum or minimum operations, and a summing device 28. The FHT device 22 performs a part of an FHT including one butterfly step for input difference values x₀, x₁, x₂ and x₃ of a difference matrix to obtain a plurality of outputs y₀, y₁, y₂ and y₃ in a sequence. The absolute value of each of the outputs y₀, y₁, y₂ and y₃ is calculated in the absolute-value devices 24. The absolute values of every two of the outputs y₀, y₁, y₂ and y₃ in the sequence are compared in comparators 26 to determine a greater value for each of the every two absolute values. The greater value of each of the every two absolute values are added in summing device 28 to obtain an SATD.

[0053] FIG. 5B is a schematic diagram illustrating the calculation of an SATD in the structure 50 illustrated in FIG. 5A. Referring to FIG. 5B, it is presumed that the FHT device 22 employs the butterfly structure illustrated in FIG. 1B and the input difference values x₀, x₁, x₂ and x₃ are 3, −1, −2 and 4, respectively. After the butterfly step, also referring to FIG. 1B, the outputs y₀, y₁, y₂ and y₃ are 1, 5, 3 and −5, respectively. As compared to the conventional method illustrated in FIG. 3A, one butterfly step in an FHT device is eliminated. The absolute-values devices 24 calculate the absolute values of the outputs y₀, y₁, y₂ and y₃, which are 1, 5, 3 and 5, respectively. The absolute values of the outputs y₀ and y₁, the first every two values in the sequence, are compared in one of the comparators 26 to determine a greater value, i.e., 5. Likewise, the absolute values of the outputs y₂ and y₃, the second every two values in the sequence, are compared in the other of the comparators 26 to determine a greater value, i.e., 5. The greater values, 5 and 5, are added in the summing device 28 to obtain the SATD, 10, which is the same as the SATD obtained by the conventional method illustrated in FIG. 3B. As a result, as compared to the conventional method, the present invention reduces the computation complexity and increase the operation speed in calculating the SATD without distorting the SATD.

[0054] FIG. 6 is a flow diagram illustrating a method for determining an SATD in accordance with one embodiment of the present invention. Referring to FIG. 6, at step 41, an image frame is provided. The image frame is partitioned into multiple blocks at step 42, of which one block has a size of N×M in accordance with a partition mode, N and M being positive integers. At step 43, a difference matrix of N×M is obtained for the one block. In one aspect, the difference matrix is obtained in accordance with an inter prediction mode, where a block of the image frame is compared with a block predicted from a reference frame different from the image frame. In another aspect, the difference matrix is obtained in accordance with an intra prediction mode, where a block of the image frame is compared with another block predicted in the same image frame. At step 44, a part of an FHT for the difference matrix including a number of [(log₂ NM)−1] butterfly steps is performed to obtain outputs in a sequence. An absolute value operation for each of the outputs is then performed at step 45. Next, at step 46, the absolute values of every two of the outputs in the sequence is compared to determine a greater value of each of the two absolute values. The greater value of each of the every two absolute values are added to determined the SATD at step 47.

[0055] From the viewpoint of hardware, the operation costs for the operators add, max and abs are substantially the same. However, from the viewpoint of software, the operation costs for the operators abs and max are higher that that for the operator add. For example, if Intel's MMX instructions sets are used for background analysis, a weight of approximately 3 must be assigned to the operator abs because it takes one operation instruction to complete a maximum operation or an addition operation, while it takes three operation instructions to complete an absolute value operation including, for example, a first instruction to copy a value, a second instruction to calculate the complement of the value and a third instruction to compare the value and its complement to determine a greater value of the two. In consideration of the software cost, in a method in accordance with another embodiment of the present invention, the absolute value operations are replaced by maximum operations and addition operations given below.

[0056] $\begin{array}{cc}\max \left(a,b\right)=\max \left(a+b,0\right)-\min \left(a,b\right)& \mathrm{Equation}\left(11\right)\\ {\mathrm{SATD}}_{N\times M}\left(D_{N\times M}\right)=\frac{4}{\sqrt{\mathrm{NM}}}\sum _{l=0}^{\frac{\mathrm{NM}}{2}-1}\left(\max \left(t_l^{n+m-1}+t_{l+\frac{\mathrm{NM}}{2}}^{n+m-1},0\right)-\min \left(t_l^{n+m-1},t_{l+\frac{\mathrm{NM}}{2}}^{n+m-1}\right)\right)& \mathrm{Equation}\left(12\right)\end{array}$

[0057] Based on the Equation (11), the Equation (10) can be rewritten as the Equation (12). Table 2 lists the number of operations required for each of the operators in the Equations (8) and (12), given SATD_4×4 and a weight of 3 assigned to each absolute value operation, which shows that the method according to one embodiment of the present invention is advantageous in operation speed.

[0058]

TABLE 2
operator/
equation	add	max/min	abs (×3)	total
Equation (8)	79	0	48 (=NM × 3)	127
	(=NM (n + m) +
	(NM − 1))
Equation	71 (=NM	16	0	87 (=NM
(12)	(n + m − 1) +	(=NM)		(n + m +
	3NM/2 − 1)			3/2) − 1)

[0059] In addition to the Equation (11), other equations may be used to replace the absolute operations in the Equation (10), which are given below.
max(|a|,|b|)=max(a,b)−min(a+b,0)  Equation (13)
max(|a|,|b|)=−min(−a−b,0)−min(a,b)  Equation (14)
max(|a|,|b|)=max(a,b)+max(−a−b,0)  Equation (15)

[0060] FIG. 7 is a schematic structures 70 for determining an SATD in accordance with one embodiment of the present invention based on the Equation (11). Referring to FIG. 7, the structure 70 includes a 1-step FHT device 72, first summing devices 73-1 and first comparators 74-1, second comparators 74-2, second summing devices 73-2 and a third summing device 73-3. The FHT device 72 performs a part of an FHT including one butterfly step for input difference values x₀, x₁, x₂ and x₃ of a difference matrix to obtain a plurality of outputs y₀, y₁, y₂ and y₃ in a sequence. The first summing devices 73-1 and first comparators 74-1 are used to replace the absolute-value devices 24 of the structure 50 illustrated in FIG. 5A. Specifically, the values of every two of the outputs y₀, y₁, y₂ and y₃ in the sequence are added in first summing devices 73-1 to obtain a first resultant value, and compared in the first comparators 74-1 to determine a smaller value for each of the every two values. The first resultant value is compared to zero in the second comparators 74-2 to determine a greater value. The smaller value is subtracted from the greater value at the second summing deices 73-2 to determine a second resultant value. The second resultant value for each of the every two output values are added in the third summing device 73-3 to obtain an SATD. The SATD equals 10 if the same input difference values of x₀, x₁, x₂ and x₃ of a difference matrix in FIG. 5B are used.

[0061] As compared to the structure 50 illustrated in FIG. 5A, the structure 70 has a higher hardware cost but enjoys a much lower software cost as reflected in the above Table 2. Skilled persons in the art will realize that the structure 50 may be advantageously implemented in hardware and the structure 70 may be advantageously implemented in software, even though both of hardware and software implementation are available.

[0062] FIG. 8 is a schematic structure 80 for determining an SATD in accordance with another embodiment of the present invention based on the Equation (13). Referring to FIG. 8, the structure 80 includes a 1-step FHT device 82, first summing devices 83-1 and first comparators 84-1, second comparators 84-2, second summing devices 83-2 and a third summing device 83-3. The FHT device 82 performs a part of an FHT including one butterfly step for input difference values x₀, x₁, x₂ and x₃ of a difference matrix to obtain a plurality of outputs y₀, y₁, y₂ and y₃ in a sequence. The first summing devices 83-1 and first comparators 84-1 are used to replace the absolute-value devices 24 of the structure 50 illustrated in FIG. 5A. Specifically, the values of every two of the outputs y₀, y₁, y₂ and y₃ in the sequence are added in first summing devices 83-1 to obtain a first resultant value, and compared in the first comparators 84-1 to determine a greater value for each of the every two values. The first resultant value is compared to zero in the second comparators 84-2 to determine a smaller value. The smaller value is subtracted from the greater value at the second summing deices 83-2 to determine a second resultant value. The second resultant value for each of the every two output values are added in the third summing device 83-3 to obtain an SATD. The SATD equals 10 if the same input difference values of x₀, x₁, x₂ and x₃ of a difference matrix in FIG. 5B are used. Skilled persons in the art will realize that the structure 80 may be advantageously implemented in software.

[0063] FIG. 9 is a schematic structure 90 for determining an SATD in accordance with still another embodiment of the present invention based on the Equation (14). Referring to FIG. 9, the structure 90 includes a 1-step FHT device 92, first summing devices 93-1 and first comparators 94-1, second comparators 94-2, second summing devices 93-2 and a third summing device 93-3. The FHT device 92 performs a part of an FHT including one butterfly step for input difference values x₀, x₁, x₂ and x₃ of a difference matrix to obtain a plurality of outputs y₀, y₁, y₂ and y₃ in a sequence. The first summing devices 93-1 and first comparators 94-1 are used to replace the absolute-value devices 24 of the structure 50 illustrated in FIG. 5A. Specifically, the values of every two of the outputs y₀, y₁, y₂ and y₃ in the sequence are added in first summing devices 93-1 to obtain a first resultant value, and compared in the first comparators 94-1 to determine a first smaller value for each of the every two values. The first resultant value in its negative form is compared to zero in the second comparators 84-2 to determine a second smaller value. The first smaller value and the second smaller value are added at the second summing deices 93-2 to determine a second resultant value. The second resultant value for each of the every two output values are added in the third summing device 93-3 to obtain an SATD in its negative form. The SATD equals 10 if the same input difference values of x₀, x₁, x₂ and x₃ of a difference matrix in FIG. 5B are used. Skilled persons in the art will realize that the structure 90 may be advantageously implemented in software.

[0064] FIG. 10 is a schematic structure for determining an SATD in accordance with yet another embodiment of the present invention based on the Equation (15). Referring to FIG. 10, the structure 100 includes a 1-step FHT device 102, first summing devices 103-1 and first comparators 104-1, second comparators 104-2, second summing devices 103-2 and a third summing device 103-3. The FHT device 102 performs a part of an FHT including one butterfly step for input difference values x₀, x₁, x₂ and x₃ of a difference matrix to obtain a plurality of outputs y₀, y₁, y₂ and y₃ in a sequence. The first summing devices 103-1 and first comparators 104-1 are used to replace the absolute-value devices 24 of the structure 50 illustrated in FIG. 5A. Specifically, the values of every two of the outputs y₀, y₁, y₂ and y₃ in the sequence are added in first summing devices 103-1 to obtain a first resultant value, and compared in the first comparators 104-1 to determine a first greater value for each of the every two values. The first resultant value in its negative form is compared to zero in the second comparators 104-2 to determine a second greater value. The first greater value and the second smaller value are added at the second summing deices 103-2 to determine a second resultant value. The second resultant value for each of the every two output values are added in the third summing device 103-3 to obtain an SATD. The SATD equals 10 if the same input difference values of x₀, x₁, x₂ and x₃ of a difference matrix in FIG. 5B are used. Skilled persons in the art will realize that the structure 100 may be advantageously implemented in software.

[0065] In describing representative embodiments of the present invention, the specification may have presented the method and/or process of the present invention as a particular sequence of steps. However, to the extent that the method or process does not rely on the particular order of steps set forth herein, the method or process should not be limited to the particular sequence of steps described. As one of ordinary skill in the art would appreciate, other sequences of steps may be possible. Therefore, the particular order of the steps set forth in the specification should not be construed as limitations on the claims. In addition, the claims directed to the method and/or process of the present invention should not be limited to the performance of their steps in the order written, and one skilled in the art can readily appreciate that the sequences may be varied and still remain within the spirit and scope of the present invention.

[0066] It will be appreciated by those skilled in the art that changes could be made to the preferred embodiments described above without departing from the broad inventive concept thereof. It is understood, therefore, that this invention is not limited to the particular embodiments disclosed, but is intended to cover modifications within the spirit and scope of the present application as defined by the appended claims.