Writing method and system for a phase change memory

[0001] 1. Field of the Invention

[0002] The invention relates to a writing method and system, and more particularly to a writing method and system for phase change memory.

[0003] 2. Description of the Related Art

[0004] With the growth in the use of portable electronic devices, the desire for non-volatile memory has increased. Among the various kinds of non-volatile memory, phase change memory is the most competitive next generation non-volatile memory due to its high speed, low power consumption, high capacity, reliable, easy process integration and lower cost. Excessive driving current prevents the density of the phase change memory from being efficiently increased, thus diminishing competitiveness of phase change memory.

[0005] Recently, several solutions have been proposed to eliminate high driving current, these solutions include a new memory structure, such as an edge contact structure or a confined structure, and a new recording material, such as N-doped GST material or O-doped material. Another issue of incomplete crystalline or amorphous states exists, preventing correct increase or decrease in resistance of the phase change memory. The crystalline and amorphous states of phase change memory have dramatically different electrical resistivity values, and this forms the basis by which data are stored. The amorphous, high resistance state is used to represent a binary 0, and the crystalline, low resistance state represents a binary 1. If the difference between the resistances in the amorphous state and the crystalline state, i.e. the sensing margin, is not large enough, thus, the logic state of the phase change memory may not be correctly determined. Additionally, the incomplete crystalline and amorphous state also causes non-uniformity of the phase change memory. In order to solve the issue of the incomplete crystalline or amorphous states, the conventional solution increases the operating time of a SET operation and a RESET operation, power consumption is thus increased and the programming speed is decreased.

[0006] The SET and RESET operations are mainly achieved by inputting two current pulses with different current magnitude to the phase change memory to switch the phase change memory between the amorphous state and crystalline state. According to Ohm-Joule's Law, when the current is input to the phase change memory, the phase change memory is heated. The phase change memory may thus be crystallized or melted based on different current. Based on the described illustration, the logic state of the phase change memory can be switched by inputting different currents, enabling data storage. FIG. 1 is a schematic diagram showing the writing current pulse and the reading current pulse of the phase change memory. When a RESET operation is applied to the phase change memory, a reset current I_RESET with high amplitude and short pulse width is applied, the phase change memory is thus melted because the temperature of the phase change memory exceeds the melting temperature of the phase change material of the phase change memory, T_m. When the temperature of the phase change memory decreases, the state of the phase change memory is transformed to the amorphous state due to the insufficient cool down period. Thus the phase change memory has high resistance. When a SET operation is applied to the phase change memory, a set current I_SET with lower amplitude and longer pulse width is applied. The phase change memory is heated by the set current I_SET, and the temperature of the phase change memory is held substantially between the melting temperature T_m and a crystallizing temperature T_c of the phase change material used by the phase change memory. During the SET operation, the melted phase change memory has sufficient time for crystallizing and the phase change memory thus has a low resistance.

[0007] As described, the phase change memory respectively stores data with logic state 1 and 0 by the RESET operation and the SET operation. When reading the phase change memory, a read current I_READ the amplitude of which less than the set current I_SET, is applied to the phase change memory to determine the logic state of the data stored in the phase change memory.

[0008] With the novel phase change memory development technique, the size of the phase change memory cell is reduced. When the size of the phase memory cell is reduced, the SET operation of phase change memory cell becomes problematic. The SET operation of the memory cell may result in incomplete crystallization of part of the active area of the memory cell, increasing the resistance of the memory cell and the sensing margin of the memory cell is reduced. Additionally, the incomplete crystalline and amorphous states also cause non-uniformity of the phase change memory. In order to solve the issue of the incomplete crystalline and amorphous states, the conventional solution increases the duration of the SET operation, i.e. increasing the SET pulse width, but the power consumption is increased. The memory may be overheated and the programming speed of the memory is decreased.

[0009] A writing method for a phase change memory is provided. An exemplary embodiment of a writing method comprises: inputting a first writing pulse signal to the phase change memory to raise the temperature of the phase change memory to above a first temperature; inputting a second writing pulse signal to the phase change memory to maintain the temperature of the phase change memory substantially at a second temperature.

[0010] Another exemplary embodiment of a writing method for a phase change memory comprises a reset procedure and a set procedure. The reset procedure comprises inputting a first amorphous pulse signal to the phase change memory to raise the temperature of the phase change memory to above or equal to a melting temperature of the phase change memory; inputting a second amorphous pulse signal to the phase change memory to maintain the temperature of the phase change memory substantially at a first temperature. The set procedure comprises inputting a first crystallizing pulse signal to the phase change memory to raise the temperature of the phase change memory to above a crystallizing temperature of the phase change memory; inputting a second crystallizing pulse signal to the phase change memory to maintain the temperature of the phase change memory substantially at a second temperature.

[0011] Another exemplary embodiment of a writing method for a phase change memory comprises: inputting a first writing pulse signal to the phase change memory to raise the temperature of the phase change memory higher than or equal to a melting temperature of the phase change memory; inputting a second writing pulse signal to the phase change memory to maintain the temperature of the phase change memory substantially at a first temperature.

[0012] An exemplary embodiment of a writing system comprises a phase change memory, a first writing pulse signal generator to generate a first writing pulse signal, a second writing pulse signal generator to generate a second writing pulse signal; and a controller to control the first writing pulse signal generator and the second writing pulse signal generator outputting the first writing pulse signal and the second writing pulse signal based on the temperature of the phase change memory, wherein the second writing pulse signal is input to the phase change memory to maintain the temperature of the phase change memory substantially at a second temperature in response to the temperature of the phase change memory exceeding a first temperature.

[0013] A detailed description is given in the following embodiments with reference to the accompanying drawings.

[0022] The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.

[0023] FIG. 2 is a schematic diagram of an embodiment of the SET pulse of the invention. The SET pulse shown in FIG. 1 is a pulse with lower current and longer duration, and the degree of crystallizing of the phase change memory increases due to the longer pulse duration. This may, however, cause the phase change memory to overheat and transforming the phase change memory state to the amorphous state. To prevent the described issue, the SET pulse shown in FIG. 2 can lengthen the duration of the crystallizing period of the phase change memory and avoids transformation of the phase change memory state to the amorphous state due to overheating.

[0024] Please refer to FIG. 2. A first crystallizing pulse signal S1 with a duration t1 is applied to heat the phase change memory until the temperature of the phase change memory exceeds a lowest crystallizing temperature T_c but does not exceed the melting temperature T_m. In other words, the temperature of the phase change memory reaches an optimum crystallizing temperature range Tc_opt, wherein the optimum crystallizing temperature range Tc_opt is the range between the crystallizing temperature T_c and the melting temperature T_m. In this embodiment, the optimum crystallizing temperature represents the phase change memory at the optimum crystallizing temperature has the maximum crystallizing time exceeding the maximum operating time of the writing operation. In FIG. 2, the optimum crystallizing temperature Tc_opt is within a temperature range, however, in the following description, the optimum crystallizing temperature Tc_opt may only indicate a temperature at within the optimum crystallizing temperature range Tc_opt shown in FIG. 2.

[0025] After the temperature of the phase change memory exceeds the crystallizing temperature T_c, a second crystallizing pulse S2 is applied to maintain the temperature of the phase change memory in the optimum crystallizing temperature range Tc_opt, put simply, T_c<Tc_opt<T_m. In this embodiment, the second crystallizing pulse signal S2 is a pulse width modulation, PWM signal, and the duration of each pulse at the current I_set can be adjusted by adjusting the duty cycle of the PWM signal. In this embodiment, the duration t2 may or may not be equal to the duration t3. In this embodiment, a temperature controller is applied to detect the temperature of the phase change memory. The temperature controller further provides adaptive control by outputting a control signal adjusting the duty cycle of the second crystallizing pulse signal S2 to adjust the duration of each pulse at the current I_set. In this embodiment, the current peak value of the first crystallizing pulse signal S1 is the same as the current peak value of the second crystallizing pulse signal S2. In other embodiments, the current peak value of the first crystallizing pulse signal S1 is not equal to the current peak value of the second crystallizing pulse signal S2.

[0026] FIG. 3 is a schematic diagram of an embodiment of the RESET pulse of the invention. The RESET pulse shown in FIG. 1 is a pulse with high current and short duration, i.e. narrow pulse width. The temperature of the phase change memory can be rapidly heated by the high current exceed the melting temperature T_m thus the phase change memory enters the amorphous state. The phase change memory may, however, be overheated due to the excessive current. Once overheated, the phase change memory may become over amorphous easily causing incomplete crystallization when a SET operation is applied to the over amorphous phase change memory.

[0027] Please refer to FIG. 3. A first amorphous pulse signal S1 with duration t1 is applied to heat the phase change memory until the temperature of the phase change memory exceeds a melting temperature T_m. When the temperature of the phase change memory exceeds a melting temperature T_m, a second amorphous pulse signal S2 is applied to keep the temperature of the phase change memory higher than the melting temperature T_m. To avoid the over amorphous issue due to the overheated, a predetermined optimum amorphous temperature range Ta_opt is determined, such as that shown in FIG. 3. In other words, the second amorphous pulse signal S2 maintains the temperature of the phase change memory between the melting temperature T_m and a optimum amorphous temperature (T_m+Ta_opt). In this embodiment, the optimum amorphous temperature is within the temperature range Ta_opt. In this embodiment, the second amorphous pulse signal S2 is a pulse width modulation, PWM signal, and the duration of each pulse at the current I_Reset can be adjusted by adjusting the duty cycle of the PWM signal. In this embodiment, the duration t2 may be or may be not equal to the duration t3. In this embodiment, a temperature controller is applied to detect the temperature of the phase change memory, and the temperature controller outputs a control signal adjusting the duty cycle of the second amorphous pulse signal S2 to adjust the duration of each pulse at the current I_Reset for adaptive control. In this embodiment, the current peak value of the first amorphous pulse signal S1 is the same as the current peak value of the second amorphous pulse signal S2. In another embodiment, the current peak value of the first amorphous pulse signal S1 is not equal to the current peak value of the second amorphous pulse signal S2.

[0028] FIG. 4 is a schematic diagram of an embodiment of a writing signal of the invention. In this embodiment, the writing signal comprises a first writing signal S1 and a second writing signal S2. The first writing signal S1 has a first voltage peak value V1 and the duration of the first voltage peak value V1 is t1. The first writing signal S1 heats the phase change memory until the temperature of the phase change memory exceeds a predetermined temperature, such as the crystallizing temperature T_c for the SET operation shown in FIG. 2 or the melting temperature T_m for the RESET operation shown in FIG. 3.

[0029] The second writing signal S2 has the first voltage peak value V1 and the duration of the first voltage peak value V1 is t3 and t5, and the second writing signal S2 further has a second voltage peak value V2 and the duration of the second voltage peak value V2 is t2 and t4. The second writing signal S2 maintains the temperature of the phase change memory within a predetermined temperature range. In FIG. 4, the second writing signal S2 maintains the temperature of the phase change memory within the optimum crystallizing temperature range Tc_opt or the optimum amorphous temperature range Ta_opt by switching the voltage of the second writing signal S2 between the first voltage peak value V1 and the second voltage peak value V2.

[0030] The embodiment of the writing signal shown in FIG. 4 illustrates the writing signal with rectangular pulse, but the first writing signal S1 and the second writing signal S2 are not limited thereto. The first writing signal S1 and the second writing signal S2 may be triangular wave of other non-rectangular pulse to achieve the same object. Implementation of the triangle wave or other non-rectangular pulse, well known to those of ordinary skill in the art and is thus not described here for brevity.

[0031] FIG. 5 is a schematic diagram of an embodiment of a writing signal generator generating the writing signal shown in FIG. 4. The first signal generator 51 produces a rectangular pulse with a voltage peak value V2 and transmits the pulse to the adder 56 via a first amplifier 56. In this embodiment, the magnification of the first amplifier 56 is 1. In this embodiment, the first signal generator 51 can also provide a DC bias voltage V2, and a control signal (not shown in FIG. 5) is applied to determine whether the first signal generator 51 output the DC bias voltage V2. The second signal generator 53 produces a rectangular pulse with a voltage peak value (V1-V2) and transmits the pulse to the adder 56 via a second amplifier 54 and a switch 55. In this embodiment, the magnification of the second amplifier 54 is 1.

[0032] When the signal generator 50 outputs the first writing signal S1, the switch 55 is turned on, thus, the adder 56 adds and outputs the sum of the output signals from the first signal generator 51 and the second signal generator 53. When the signal generator 50 outputs the second writing signal S2, the adder 56 outputs the output signals from the second signal generator 53 or the sum of the output signals from the first signal generator 51 and the second signal generator 53 based on a turn-on signal. Take the second writing signal S2 shown in FIG. 4 for example, the switch 55 is sequentially turned off for a duration t2, turned on for a duration t3, turned off for a duration t4 and turned on for a duration t5 by the turn-on signal, thus, the signal generator 50 can output the second writing signal S2 shown in FIG. 4. The circuit of the signal generator 50 is simple and easy to implement. In this embodiment, the turn-on signal of the switch 55 is a clock signal or a periodicity signal. A controller is applied to detect the temperature of the phase change memory, and the controller outputs a control signal to adjust the turn-on signal to control the time which the signal generator 50 outputs the output signal from the second signal generator 53 for adaptive control.

[0033] FIG. 6 is a schematic diagram of another embodiment of a writing signal of the invention. In this embodiment, the writing signal comprises a first writing signal S1 and a second writing signal S2. The first writing signal S1 has a first voltage peak value V1 and the duration of the first voltage peak value V1 is t1. The first writing signal S1 heats the phase change memory until the temperature of the phase change memory exceeds a predetermined temperature, such as the crystallizing temperature T_c for the SET operation shown in FIG. 2 or the melting temperature T_m for the RESET operation shown in FIG. 3.

[0034] In this embodiment, the second writing signal S2 is a three-step signal, having a first voltage peak value V1, second voltage peak value V2 and third voltage peak value V3. The second writing signal S2 maintains the temperature of the phase change memory within a predetermined temperature range. In the FIG. 6, the second writing signal S2 maintains the temperature of the phase change memory within the optimum crystallizing temperature range Tc_opt or the optimum amorphous temperature range Ta_opt by switching the voltage of the second writing signal S2 among the first voltage peak value V1, the second voltage peak value V2 and the third voltage peak value V3. The second writing signal S2 shown in FIG. 6 consumes less power than the conventional writing signal. The embodiment of the writing signal shown in FIG. 6 illustrates the writing signal with rectangular pulse, but the first writing signal S1 and the second writing signal S2 is not limited thereto.

[0035] The second writing signal S2 shown in FIG. 6 can be implemented by the writing signal generator similar to the writing signal generator shown in FIG. 5. On an embodiment of the writing signal generator generating the second writing signal S2 shown in FIG. 6 comprises three signal generators respectively outputting pulses with voltage peak values V3, (V2-V3), and (V1-V3). The durations of the second writing signal t2 to t9 shown in FIG. 6 can be achieved by a switch and a turn-on signal, such as the switch 55 and the turn-on signal in FIG. 5

[0036] FIG. 7 is a schematic diagram of another embodiment of a writing signal generator of the invention. The temperature detector 76 detects and transmits the temperature of the phase change memory 71 to the controller 72. The controller 72 receives a first writing signal S1 from the first writing signal generator 73 to heat the phase change memory 71 until the temperature of the phase change memory 71 exceeds a predetermined temperature. When the temperature detector 76 detects that the temperature of the phase change memory 71 exceeds the predetermined temperature, the controller 72 stops inputting the first writing signal generator 73 to the phase change memory 71. The controller 72 receives and inputs a second writing signal S2 from a second writing signal generator 74 to maintain the temperature of the phase change memory 71 within a predetermined temperature range.

[0037] When a SET operation is applied to the phase change memory 71, the predetermined temperature is the crystallizing temperature T_c of the phase change memory 71, and the second writing signal S2 maintains the temperature of the phase change memory 71 between the crystallizing temperature T_c and melting temperature T_m of the phase change memory 71. When a RESET operation is applied to the phase change memory 71, the predetermined temperature is the melting temperature T_m of the phase change memory 71, and the second writing signal S2 maintains the temperature of the phase change memory 71 being within a optimum amorphous temperature range Ta_opt. The controller 72 can also generate a third writing signal S3 by the adder 75, which adds the first writing signal S1 and the second writing signal S2. In this embodiment, the first writing signal generator 73 and the second writing signal generator 74 adjust the current, voltage or power peak value and the duration at the peak value of the first writing signal S1 and the second writing signal S2 by a control signal.

[0038] While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.