High density trench MOSFET with single mask pre-defined gate and contact trenches

[0001] This invention generally relates to high density trench MOSFET devices and more particularly to a method for making gate and contact trenches of the MOSFET devices with a single mask.

[0002] A MOSFET transistor that includes a trench gate structure offers important advantages over a planar transistor for high current, low voltage switching applications. A trench gate of a MOSFET device typically includes a trench extending from the source to the drain and having sidewalls and a floor that are each lined with a layer of thermally grown silicon dioxide. The lined trench is filled with doped polysilicon. The structure of the trench gate allows less constricted current flow and, consequently, provides lower values of specific on-resistance. Furthermore, the trench gate makes possible a decreased cell pitch in an MOSFET channel extending along the vertical sidewalls of the trench from the bottom of the source across the body of the transistor to the drain below. Channel density is thereby increased, which reduces the contribution of the channel to on-resistance.

[0003] A high density trench MOSFET device also includes a contact trench for making contact to source and body regions. Conventional processes for manufacturing of the high density trench MOSFET devices have used two independent masks for making gate trenches and contact trenches. FIG. 1A and FIG. 1B are cross-sectional views illustrating fabrication of a gate trench and contact trench of a vertical MOSFET structure of the prior art. As shown in FIG. 1A, a gate trench mask 102 is used to make a vertical gate trench 108. In a separate step, shown in FIG. 1B, a trench contact mask 104 is used to make a contact trench 110 on a same substrate 106 after the gate trench 108 has been formed. However, a mask overlay issue occurs when two masks 102 and 104 are used to form a vertical MOSFET structure because a well controlled spacing between the gate trench and nearby contact trench is required for high density MOSFET devices, which have increasingly smaller dimensions.

[0004] Schemes based on self-alignment processes have been proposed to solve this mask overlay issue. However, these proposed schemes, which use various constructs of alternating oxide and nitride blocking planar or sidewall spacers to create a contact trench that is self-aligned to the gate trench, are complicated to implement. In addition, the spacers may have uniformity problems, wherein spacers at the wafer center may be thicker or thinner than those at the wafer edge.

[0005] It is within this context that embodiments of the present invention arise. It would be desirable to develop a process which would use a single mask to pre-define both gate and contact trenches without using complicated multiple spacer approaches.

[0009] Although the following detailed description contains many specific details for the purposes of illustration, anyone of ordinary skill in the art will appreciate that many variations and alterations to the following details are within the scope of the invention. Accordingly, the exemplary embodiments of the invention described below are set forth without any loss of generality to, and without imposing limitations upon, the claimed invention.

[0010] Embodiments of the present invention present a process that uses a single mask to define both gate and contact trenches without utilizing complicated multiple spacer approaches. An example of a fabrication process according to an embodiment of the present invention is shown in FIGS. 2A-2T.

[0011] The process uses a semiconductor substrate 202 as a starting material. The substrate 202 may be divided into multiple die. Each die may include an active cell area 201 and a gate pickup/contact area 203 at the periphery of a die as shown in FIG. 2A. Generally, the active cell area 201 contains multiple cells (e.g., MOSFET cells) having the same or similar structure. For the sake of example, a single cell is shown in the active area 201. This is done to illustrate the general fabrication process and is not meant as a limitation on any embodiment of the invention.

[0012] A hard mask 204, made of a suitable material (e.g., oxide,) is formed on top of the semiconductor substrate 202. The thickness of the hard mask 204 may be about 0.3 um. A background trench photoresist (not shown) is formed on the hard mask 204 and patterned to define a pattern for the trenches. Body contact trenches 206 and gate trenches 208 are formed on the active cell area 201 and gate contact trenches 210 are formed on the gate pickup/contact area 203 by etching away portions of the hard mask 204 that are exposed to an etchant through openings in the photoresist and then etching corresponding portions of the underlying semiconductor substrate 202 to a first predetermined depth of, e.g., about 0.3 um as shown in FIG. 2B. The photoresist may or may not be removed during etching of the exposed portions of the underlying semiconductor substrate 202. This first masking step predefines the gate trenches, gate contact trenches and body contact trenches. Since the trenches 206,208, 210 are all aligned in a common masking step, issues of non-uniform trench spacing across a wafer that are inherent to self-alignment processes employing spacers may be avoided.

[0013] As shown in FIG. 2C, a gate trench mask 212, e.g., a patterned layer of a resist, such as a photoresist, may be deposited and patterned on top of the hard mask 204. The gate trench mask 212 includes openings at the gate trenches 208 and gate contact trenches 210 with the openings being larger than the dimensions of the trenches 208, 210. The remaining portions of the gate trench mask 212 cover the body contact trenches 206 to protect them during a subsequent etch step. As shown in FIG. 2D, the trenches 208 and 210 are then simultaneously etched deeper into the semiconductor substrate 202 to a second predetermined depth. Because the openings in the gate trench mask 212 have wider widths w_mo than the widths w_t of the corresponding trenches, and because the hard mask 204 has already predefined all trench locations the gate trench mask 212 can have a relatively large alignment budget. As a result, overlay issues may be made much more manageable than in the prior art. The openings may be made wide since the edges of the trenches 208, 210 are protected during etching by the hard mask 204. In general, the mask openings may be made as wide as desired, provided that they do not expose body contact trenches 206 to undesired etching.

[0014] The ability to initiate simultaneous fabrication of the gate trenches and body contact trenches for trench gate MOSFET devices demanding a higher packing density of unit cells with a single mask and to form the gate trenches with a second mask having loose alignment tolerances is particularly advantageous when a high degree of trench spacing uniformity across the wafer is critical in order to achieve stable and consistent device characteristics, e.g. the threshold voltage, in the active cell area 201. By way of example, control of the spacing between the body contact trenches 206 and the gate trenches 208 may become critical when a spacing S between them is less than about 0.3 microns, e.g., about 0.25 microns or less.

[0015] By way of example, and not by way of limitation, the trenches 208, 210 may be etched at a sufficient taper angle, e.g., about 87 degrees, to facilitate gate material backfilling in the trenches, e.g., polysilicon gapfilling. Preferably, the hard mask 204 is selectively etched at a much lower rate than the semiconductor substrate 202. By way of example, and not by way of limitation, the substrate may be preferentially etched with an etch selectivity between about 30:1 and about 40:1 relative to the hard mask 204. Because the gate trench mask 212 covers the body contact trenches 206, these trenches are protected from the etch process and are not deepened by the etch process. Because the hard mask 204 is etched at a lower rate than the substrate 202 the etching deepens the trenches 208, 210 but does not affect the edges of the trenches, which are protected by the hard mask 204. After etching, a thick layer of insulating material 214, such as an oxide, may optionally be formed at the bottoms of the trenches 208 and 210 to form a thick bottom oxide for the gate.

[0016] The gate trench mask 212 is then removed as shown in FIG. 2E. A unique silicon round hole etch, e.g., an isotropic silicon etch, may be carried out to round off the trench bottom corners to extend the bottom of the trench to the lateral direction and the vertical direction. A layer of gate insulating material 216 may be formed, e.g., by an oxidation reaction that forms a gate oxide layer after a standard sacrificial oxide growth and etch cycle on the sidewalls and the bottoms of the trenches 208 and 210.

[0017] A conductive material 218, e.g., in-situ doped or undoped polysilicon, is deposited to fill in the trenches 208 and 210 as shown in FIG. 2F. The thickness of the conductive material 218 is such that it will completely fill up all trenches, e.g., 1.2 microns in one design and 0.8 microns in another. The conductive material layer 218 may then be etched back to target depth either above, at, or below the surface of semiconductor substrate 202. As shown in FIG. 2G, the conductive layer 218 may be etched back below the semiconductor substrate's surface to form a gate 209 in the gate trench and gate contact 211 in the gate contact trench. In some cases, two or more conductive materials may be used to form these contacts.

[0018] As shown in FIG. 2H, a gate trench mask 220, e.g., a photoresist, may be deposited and patterned on top of the hard mask 204. The gate trench mask 220 includes openings at the locations of the gate trench 208 and the gate contact trench 210. The conductive material 218 forming the gate 209, and gate contact 211 and portions of the sidewalls of the trenches 208 and 210 that are not covered by the conductive material 218 may optionally be implanted with suitable dopant species 222, such as Arsenic (As), Phosphorus (P), or Boron (B). The dopants 222 may be implanted perpendicular or at an oblique angle, e.g., 85 degrees, relative to the substrate surface, so that dopants may be implanted into the sidewalls of the trenches 208, 210. Angled dopant implantation into sidewalls of the trenches may provide a more consistent control of channel resistance and device threshold voltage.

[0019] As shown in FIG. 2I, the gate trench mask 220 and the hard mask 204 are removed. The hard mask 204 may be removed using dry etch or wet dip. Uncovered portions of the gate insulating layer 216 may also be removed. An insulating layer 224 may then be formed on top of the semiconductor substrate 202 and the conductive material forming the gate 209 and gate contact 211 as shown in FIG. 2J. By way of example, and not by way of limitation, the insulating layer 224 may be an oxide layer deposited using chemical vapor deposition (CVD). The pad insulating layer 224 may then be etched back to target depth at the surface of the semiconductor substrate 202 surface as shown in FIG. 2K. Alternatively, the insulating layer 224 may be removed by Chemical Mechanical Polishing (CMP).

[0020] A pad insulating layer 226 with a thickness of about 200 Å is then grown or deposited on top of the structure for ion implantation. A body photo mask (not shown) is applied on the pad insulating layer 226 for body implantation. Dopants are then implanted into the top portions of the semiconductor substrate 202 and heat is applied to activate dopant atoms and drive dopant diffusion to form a body region 227 (e.g., a p-type or n-type body region depending on the type of dopants implanted) in the substrate 202 as shown in FIG. 2L. The heat treatment also drives dopants to a target p/n junction J indicated by a dashed line.

[0021] A source mask 228 with a gate contact opening 231 may be applied on top of the pad insulating layer 226. The source mask 228 may cover the gate pickup/contact area 203 and leave the active cell area 201 uncovered for source implantation. Then, standard source dopant implant may be performed through exposed portions of the pad insulating layer 226 and diffusion processes may be carried out to form the source regions 229 in the active cell area 201 as shown in FIG. 2M. These processes may be identical to corresponding stages of the current standard trench MOSFET process.

[0022] As shown in FIG. 2N, the source mask 228 is then removed. An inter-layer dielectric (ILD) layer 230 may then be deposited over the surface of the semiconductor substrate 202. The thickness of the ILD layer 230 may be about 0.2 um. The ILD layer 230 can be formed by a low temperature oxidation process with material of silicon oxide, tetraethyl orthosilicate (TEOS), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG) or any combination of above.

[0023] As shown in FIG. 2O, second source mask 232 having a gate contact opening 233 on top of the gate contact 211 is applied on top of the gate pickup/contact area 203 with the active cell area 201 uncovered. The mask 232 may have the same pattern as the source mask 228. By way of example, a common mask e.g., a photomask, may be used to pattern both masks 228, 232. The ILD layer 230 may then be removed from the active cell region 201 and from beneath the opening 233 in a subsequent etch step. The mask 232 may then be removed as shown in FIG. 2P.

[0024] As shown in FIG. 2Q, a contact photo mask 236 may be applied on top of the active cell area 201 and the gate pickup/contact area 203. The contact photo mask 236 includes openings 235 that are wider than the body contact trenches 206 and an opening 237 narrower than the gate contact 211. The contact mask 236 covers the gate 209 to protect it during a subsequent etch step. The insulating material 224 may then be etched back and the etching stopped at the surface of the semiconductor substrate 202. Then, standard processes of contact implant and diffusion may be carried out to form contact regions 234 proximate to the bottoms of the contact trenches 206 as shown in FIG. 2Q. The contact implant also goes into portions of the source region 229. However, since the source region 229 is much more heavily doped (e.g., 2-3 orders of magnitude higher), the body contact implant does not affect the doping of the source region 229.

[0025] The contact photo mask 236 is then stripped as shown in FIG. 2R. Optionally, the top surface of the semiconductor substrate 202 is slightly etched to remove dopant-induced damage. A subsequent light etch may be performed to remove insulating material remaining on top of source region 229, in the body contact trenches 206 and under the opening 237 above the gate contact 211. Titanium (Ti) and Titanium Nitride (TiN) may now be blanket deposited and then followed by silicidation to form a Titanium Silicide (TiSi_x) layer 238 as shown in FIG. 2S. A conductive material 239, such as Tungsten (W), may then be blanket deposited in the trenches 206 and 210 and then etched back to form conductive plugs. Finally, a metal layer 240, such as AlCu, is blanket deposited on top of the active cell area 201 and the gate pickup/contact area 203 and patterned. In the active cell area 201, the metal layer 240 contacts the source and body.

[0026] As shown in FIG. 2T, a metal photo mask (not shown) may be applied for patterning metal layer 240. The photoresist may be stripped after etching.

[0027] While the above is a complete description of the preferred embodiment of the present invention, it is possible to use various alternatives, modifications and equivalents. Therefore, the scope of the present invention should be determined not with reference to the above description but should, instead, be determined with reference to the appended claims, along with their full scope of equivalents. Any feature, whether preferred or not, may be combined with any other feature, whether preferred or not. In the claims that follow, the indefinite article “A”, or “An” refers to a quantity of one or more of the item following the article, except where expressly stated otherwise. The appended claims are not to be interpreted as including means-plus-function limitations, unless such a limitation is explicitly recited in a given claim using the phrase “means for.”